| blob | 8baea59cadb727c0b94aa0cebf9d3e6df2a82790 |
1 /* Modified by Broadcom Corp. Portions Copyright (c) Broadcom Corp, 2012. */
2 /*
3 * linux/arch/arm/mm/proc-v7.S
4 *
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This is the "shell" of the ARMv7 processor support.
12 */
13 #include <linux/init.h>
14 #include <linux/linkage.h>
15 #include <asm/assembler.h>
16 #include <asm/memory.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/hwcap.h>
19 #include <asm/pgtable-hwdef.h>
20 #include <asm/pgtable.h>
22 #include "proc-macros.S"
24 #define TTB_S (1 << 1)
25 #define TTB_RGN_NC (0 << 3)
26 #define TTB_RGN_OC_WBWA (1 << 3)
27 #define TTB_RGN_OC_WT (2 << 3)
28 #define TTB_RGN_OC_WB (3 << 3)
29 #define TTB_NOS (1 << 5)
30 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
31 #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
32 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
33 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
35 #ifndef CONFIG_SMP
36 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
37 #define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
38 #define PMD_FLAGS PMD_SECT_WB
39 #else
40 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
41 #define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
42 #define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
43 #endif
45 ENTRY(cpu_v7_proc_init)
46 mov pc, lr
47 ENDPROC(cpu_v7_proc_init)
49 ENTRY(cpu_v7_proc_fin)
50 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
51 bic r0, r0, #0x1000 @ ...i............
52 bic r0, r0, #0x0006 @ .............ca.
53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
54 mov pc, lr
55 ENDPROC(cpu_v7_proc_fin)
57 /*
58 * cpu_v7_reset(loc)
59 *
60 * Perform a soft reset of the system. Put the CPU into the
61 * same state as it would be if it had been reset, and branch
62 * to what would be the reset vector.
63 *
64 * - loc - location to jump to for soft reset
65 */
66 .align 5
67 ENTRY(cpu_v7_reset)
68 mov pc, r0
69 ENDPROC(cpu_v7_reset)
71 /*
72 * cpu_v7_do_idle()
73 *
74 * Idle the processor (eg, wait for interrupt).
75 *
76 * IRQs are already disabled.
77 */
78 ENTRY(cpu_v7_do_idle)
79 dsb @ WFI may enter a low-power mode
80 wfi
81 mov pc, lr
82 ENDPROC(cpu_v7_do_idle)
84 ENTRY(cpu_v7_dcache_clean_area)
85 #ifndef TLB_CAN_READ_FROM_L1_CACHE
86 dcache_line_size r2, r3
87 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
88 add r0, r0, r2
89 subs r1, r1, r2
90 bhi 1b
91 dsb
92 #endif
93 mov pc, lr
94 ENDPROC(cpu_v7_dcache_clean_area)
96 /*
97 * cpu_v7_switch_mm(pgd_phys, tsk)
98 *
99 * Set the translation table base pointer to be pgd_phys
100 *
101 * - pgd_phys - physical address of new TTB
102 *
103 * It is assumed that:
104 * - we are not using split page tables
105 */
106 ENTRY(cpu_v7_switch_mm)
107 #ifdef CONFIG_MMU
108 mov r2, #0
109 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
110 orr r0, r0, #TTB_FLAGS
111 #ifdef CONFIG_ARM_ERRATA_430973
112 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
113 #endif
114 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
115 isb
116 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
117 isb
118 mcr p15, 0, r1, c13, c0, 1 @ set context ID
119 isb
120 #endif
121 mov pc, lr
122 ENDPROC(cpu_v7_switch_mm)
124 /*
125 * cpu_v7_set_pte_ext(ptep, pte)
126 *
127 * Set a level 2 translation table entry.
128 *
129 * - ptep - pointer to level 2 translation table entry
130 * (hardware version is stored at -1024 bytes)
131 * - pte - PTE value to store
132 * - ext - value for extended PTE bits
133 */
134 ENTRY(cpu_v7_set_pte_ext)
135 #ifdef CONFIG_MMU
136 ARM( str r1, [r0], #-2048 ) @ linux version
137 THUMB( str r1, [r0] ) @ linux version
138 THUMB( sub r0, r0, #2048 )
140 bic r3, r1, #0x000003f0
141 bic r3, r3, #PTE_TYPE_MASK
142 orr r3, r3, r2
143 orr r3, r3, #PTE_EXT_AP0 | 2
145 tst r1, #1 << 4
146 orrne r3, r3, #PTE_EXT_TEX(1)
148 tst r1, #L_PTE_WRITE
149 tstne r1, #L_PTE_DIRTY
150 orreq r3, r3, #PTE_EXT_APX
152 tst r1, #L_PTE_USER
153 orrne r3, r3, #PTE_EXT_AP1
154 tstne r3, #PTE_EXT_APX
155 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
157 tst r1, #L_PTE_EXEC
158 orreq r3, r3, #PTE_EXT_XN
160 tst r1, #L_PTE_YOUNG
161 tstne r1, #L_PTE_PRESENT
162 moveq r3, #0
164 str r3, [r0]
165 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
166 #endif
167 mov pc, lr
168 ENDPROC(cpu_v7_set_pte_ext)
170 cpu_v7_name:
171 .ascii "ARMv7 Processor"
172 .align
174 __INIT
176 /*
177 * __v7_setup
178 *
179 * Initialise TLB, Caches, and MMU state ready to switch the MMU
180 * on. Return in r0 the new CP15 C1 control register setting.
181 *
182 * We automatically detect if we have a Harvard cache, and use the
183 * Harvard cache control instructions insead of the unified cache
184 * control instructions.
185 *
186 * This should be able to cover all ARMv7 cores.
187 *
188 * It is assumed that:
189 * - cache type register is implemented
190 */
191 __v7_ca9mp_setup:
192 #ifdef CONFIG_SMP
193 mrc p15, 0, r0, c1, c0, 1
194 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
195 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
196 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
197 #endif
198 __v7_setup:
199 @ temporary local stack in RAM, physical address, MMU is off
200 #ifdef CONFIG_SPARSEMEM
201 ldr r0, =(PAGE_OFFSET+SZ_128M)
202 ldr r1, =__v7_setup_stack
203 cmp r1, r0
204 bge 1f
205 ldr r0, =PAGE_OFFSET
206 sub r12, r1, r0
207 b 2f
208 1:
209 sub r1, r1, r0
210 ldr r0, =PHYS_OFFSET2
211 add r12, r1, r0
212 2:
213 #else
214 ldr r12, =__virt_to_phys(__v7_setup_stack)
215 #endif
217 stmia r12, {r0-r5, r7, r9, r11, lr}
218 bl v7_flush_dcache_all
219 ldmia r12, {r0-r5, r7, r9, r11, lr}
221 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
222 and r10, r0, #0xff000000 @ ARM?
223 teq r10, #0x41000000
224 bne 3f
225 and r5, r0, #0x00f00000 @ variant
226 and r6, r0, #0x0000000f @ revision
227 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
228 ubfx r0, r0, #4, #12 @ primary part number
230 /* Cortex-A8 Errata */
231 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
232 teq r0, r10
233 bne 2f
234 #ifdef CONFIG_ARM_ERRATA_430973
235 teq r5, #0x00100000 @ only present in r1p*
236 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
237 orreq r10, r10, #(1 << 6) @ set IBE to 1
238 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
239 #endif
240 #ifdef CONFIG_ARM_ERRATA_458693
241 teq r6, #0x20 @ only present in r2p0
242 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
243 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
244 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
245 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
246 #endif
247 #ifdef CONFIG_ARM_ERRATA_460075
248 teq r6, #0x20 @ only present in r2p0
249 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
250 tsteq r10, #1 << 22
251 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
252 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
253 #endif
254 b 3f
256 /* Cortex-A9 Errata */
257 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
258 teq r0, r10
259 bne 3f
260 #ifdef CONFIG_ARM_ERRATA_742230
261 cmp r6, #0x22 @ only present up to r2p2
262 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
263 orrle r10, r10, #1 << 4 @ set bit #4
264 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
265 #endif
266 #ifdef CONFIG_ARM_ERRATA_742231
267 teq r6, #0x20 @ present in r2p0
268 teqne r6, #0x21 @ present in r2p1
269 teqne r6, #0x22 @ present in r2p2
270 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
271 orreq r10, r10, #1 << 12 @ set bit #12
272 orreq r10, r10, #1 << 22 @ set bit #22
273 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
274 #endif
275 #ifdef CONFIG_ARM_ERRATA_743622
276 teq r6, #0x20 @ present in r2p0
277 teqne r6, #0x21 @ present in r2p1
278 teqne r6, #0x22 @ present in r2p2
279 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
280 orreq r10, r10, #1 << 6 @ set bit #6
281 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
282 #endif
284 3: mov r10, #0
285 #ifdef HARVARD_CACHE
286 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
287 #endif
288 dsb
289 #ifdef CONFIG_MMU
290 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
291 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
292 orr r4, r4, #TTB_FLAGS
293 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
294 mov r10, #0x1f @ domains 0, 1 = manager
295 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
296 /*
297 * Memory region attributes with SCTLR.TRE=1
298 *
299 * n = TEX[0],C,B
300 * TR = PRRR[2n+1:2n] - memory type
301 * IR = NMRR[2n+1:2n] - inner cacheable property
302 * OR = NMRR[2n+17:2n+16] - outer cacheable property
303 *
304 * n TR IR OR
305 * UNCACHED 000 00
306 * BUFFERABLE 001 10 00 00
307 * WRITETHROUGH 010 10 10 10
308 * WRITEBACK 011 10 11 11
309 * reserved 110
310 * WRITEALLOC 111 10 01 01
311 * DEV_SHARED 100 01
312 * DEV_NONSHARED 100 01
313 * DEV_WC 001 10
314 * DEV_CACHED 011 10
315 *
316 * Other attributes:
317 *
318 * DS0 = PRRR[16] = 0 - device shareable property
319 * DS1 = PRRR[17] = 1 - device shareable property
320 * NS0 = PRRR[18] = 0 - normal shareable property
321 * NS1 = PRRR[19] = 1 - normal shareable property
322 * NOS = PRRR[24+n] = 1 - not outer shareable
323 */
324 ldr r5, =0xff0a81a8 @ PRRR
325 ldr r6, =0x40e040e0 @ NMRR
326 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
327 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
328 #endif
329 adr r5, v7_crval
330 ldmia r5, {r5, r6}
331 #ifdef CONFIG_CPU_ENDIAN_BE8
332 orr r6, r6, #1 << 25 @ big-endian page tables
333 #endif
334 mrc p15, 0, r0, c1, c0, 0 @ read control register
335 bic r0, r0, r5 @ clear bits them
336 orr r0, r0, r6 @ set them
337 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
338 mov pc, lr @ return to head.S:__ret
339 ENDPROC(__v7_setup)
340 .ltorg
342 .type v7_crval, #object
343 v7_crval:
344 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
346 .type v7_processor_functions, #object
347 ENTRY(v7_processor_functions)
348 .word v7_early_abort
349 .word v7_pabort
350 .word cpu_v7_proc_init
351 .word cpu_v7_proc_fin
352 .word cpu_v7_reset
353 .word cpu_v7_do_idle
354 .word cpu_v7_dcache_clean_area
355 .word cpu_v7_switch_mm
356 .word cpu_v7_set_pte_ext
357 .size v7_processor_functions, . - v7_processor_functions
359 .type cpu_arch_name, #object
360 cpu_arch_name:
361 .asciz "armv7"
362 .size cpu_arch_name, . - cpu_arch_name
364 .type cpu_elf_name, #object
365 cpu_elf_name:
366 .asciz "v7"
367 .size cpu_elf_name, . - cpu_elf_name
368 .align
370 .section ".proc.info.init", #alloc, #execinstr
372 .type __v7_ca9mp_proc_info, #object
373 __v7_ca9mp_proc_info:
374 .long 0x410fc090 @ Required ID value
375 .long 0xff0ffff0 @ Mask for ID
376 .long PMD_TYPE_SECT | \
377 PMD_SECT_AP_WRITE | \
378 PMD_SECT_AP_READ | \
379 PMD_FLAGS
380 .long PMD_TYPE_SECT | \
381 PMD_SECT_XN | \
382 PMD_SECT_AP_WRITE | \
383 PMD_SECT_AP_READ
384 b __v7_ca9mp_setup
385 .long cpu_arch_name
386 .long cpu_elf_name
387 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
388 .long cpu_v7_name
389 .long v7_processor_functions
390 .long v7wbi_tlb_fns
391 .long v6_user_fns
392 .long v7_cache_fns
393 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
395 /*
396 * Match any ARMv7 processor core.
397 */
398 .type __v7_proc_info, #object
399 __v7_proc_info:
400 .long 0x000f0000 @ Required ID value
401 .long 0x000f0000 @ Mask for ID
402 .long PMD_TYPE_SECT | \
403 PMD_SECT_AP_WRITE | \
404 PMD_SECT_AP_READ | \
405 PMD_FLAGS
406 .long PMD_TYPE_SECT | \
407 PMD_SECT_XN | \
408 PMD_SECT_AP_WRITE | \
409 PMD_SECT_AP_READ
410 b __v7_setup
411 .long cpu_arch_name
412 .long cpu_elf_name
413 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
414 .long cpu_v7_name
415 .long v7_processor_functions
416 .long v7wbi_tlb_fns
417 .long v6_user_fns
418 .long v7_cache_fns
419 .size __v7_proc_info, . - __v7_proc_info
421 .bss
422 .align
423 __v7_setup_stack:
424 .space 4 * 11 @ 11 registers