release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-tegra/clock.h

   1 /*
   2  * arch/arm/mach-tegra/include/mach/clock.h
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #ifndef __MACH_TEGRA_CLOCK_H
  21 #define __MACH_TEGRA_CLOCK_H
  22
  23 #include <linux/list.h>
  24 #include <asm/clkdev.h>
  25
  26 #define DIV_BUS                 (1 << 0)
  27 #define DIV_U71                 (1 << 1)
  28 #define DIV_U71_FIXED           (1 << 2)
  29 #define DIV_2                   (1 << 3)
  30 #define PLL_FIXED               (1 << 4)
  31 #define PLL_HAS_CPCON           (1 << 5)
  32 #define MUX                     (1 << 6)
  33 #define PLLD                    (1 << 7)
  34 #define PERIPH_NO_RESET         (1 << 8)
  35 #define PERIPH_NO_ENB           (1 << 9)
  36 #define PERIPH_EMC_ENB          (1 << 10)
  37 #define PERIPH_MANUAL_RESET     (1 << 11)
  38 #define PLL_ALT_MISC_REG        (1 << 12)
  39 #define ENABLE_ON_INIT          (1 << 28)
  40
  41 struct clk;
  42
  43 struct clk_mux_sel {
  44         struct clk      *input;
  45         u32             value;
  46 };
  47
  48 struct clk_pll_table {
  49         unsigned long   input_rate;
  50         unsigned long   output_rate;
  51         u16             n;
  52         u16             m;
  53         u8              p;
  54         u8              cpcon;
  55 };
  56
  57 struct clk_ops {
  58         void            (*init)(struct clk *);
  59         int             (*enable)(struct clk *);
  60         void            (*disable)(struct clk *);
  61         void            (*recalc)(struct clk *);
  62         int             (*set_parent)(struct clk *, struct clk *);
  63         int             (*set_rate)(struct clk *, unsigned long);
  64         unsigned long   (*get_rate)(struct clk *);
  65         long            (*round_rate)(struct clk *, unsigned long);
  66         unsigned long   (*recalculate_rate)(struct clk *);
  67 };
  68
  69 enum clk_state {
  70         UNINITIALIZED = 0,
  71         ON,
  72         OFF,
  73 };
  74
  75 struct clk {
  76         /* node for master clocks list */
  77         struct list_head                node;
  78         struct list_head                children;       /* list of children */
  79         struct list_head                sibling;        /* node for children */
  80 #ifdef CONFIG_DEBUG_FS
  81         struct dentry                   *dent;
  82         struct dentry                   *parent_dent;
  83 #endif
  84         struct clk_ops                  *ops;
  85         struct clk                      *parent;
  86         struct clk_lookup               lookup;
  87         unsigned long                   rate;
  88         u32                             flags;
  89         u32                             refcnt;
  90         const char                      *name;
  91         u32                             reg;
  92         u32                             reg_shift;
  93         unsigned int                    clk_num;
  94         enum clk_state                  state;
  95 #ifdef CONFIG_DEBUG_FS
  96         bool                            set;
  97 #endif
  98
  99         /* PLL */
 100         unsigned long                   input_min;
 101         unsigned long                   input_max;
 102         unsigned long                   cf_min;
 103         unsigned long                   cf_max;
 104         unsigned long                   vco_min;
 105         unsigned long                   vco_max;
 106         u32                             m;
 107         u32                             n;
 108         u32                             p;
 109         u32                             cpcon;
 110         const struct clk_pll_table      *pll_table;
 111
 112         /* DIV */
 113         u32                             div;
 114         u32                             mul;
 115
 116         /* MUX */
 117         const struct clk_mux_sel        *inputs;
 118         u32                             sel;
 119         u32                             reg_mask;
 120 };
 121
 122
 123 struct clk_duplicate {
 124         const char *name;
 125         struct clk_lookup lookup;
 126 };
 127
 128 struct tegra_clk_init_table {
 129         const char *name;
 130         const char *parent;
 131         unsigned long rate;
 132         bool enabled;
 133 };
 134
 135 void tegra2_init_clocks(void);
 136 void tegra2_periph_reset_deassert(struct clk *c);
 137 void tegra2_periph_reset_assert(struct clk *c);
 138 void clk_init(struct clk *clk);
 139 struct clk *tegra_get_clock_by_name(const char *name);
 140 unsigned long clk_measure_input_freq(void);
 141 void clk_disable_locked(struct clk *c);
 142 int clk_enable_locked(struct clk *c);
 143 int clk_set_parent_locked(struct clk *c, struct clk *parent);
 144 int clk_reparent(struct clk *c, struct clk *parent);
 145 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
 146
 147 #endif