release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv310/include/mach/regs-clock.h

   1 /* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV310 - Clock register definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_REGS_CLOCK_H
  14 #define __ASM_ARCH_REGS_CLOCK_H __FILE__
  15
  16 #include <mach/map.h>
  17
  18 #define S5P_CLKREG(x)                   (S5P_VA_CMU + (x))
  19
  20 #define S5P_INFORM0                     S5P_CLKREG(0x800)
  21
  22 #define S5P_EPLL_CON0                   S5P_CLKREG(0x0C110)
  23 #define S5P_EPLL_CON1                   S5P_CLKREG(0x0C114)
  24 #define S5P_VPLL_CON0                   S5P_CLKREG(0x0C120)
  25 #define S5P_VPLL_CON1                   S5P_CLKREG(0x0C124)
  26
  27 #define S5P_CLKSRC_TOP0                 S5P_CLKREG(0x0C210)
  28 #define S5P_CLKSRC_TOP1                 S5P_CLKREG(0x0C214)
  29
  30 #define S5P_CLKSRC_PERIL0               S5P_CLKREG(0x0C250)
  31
  32 #define S5P_CLKDIV_TOP                  S5P_CLKREG(0x0C510)
  33
  34 #define S5P_CLKDIV_PERIL0               S5P_CLKREG(0x0C550)
  35 #define S5P_CLKDIV_PERIL1               S5P_CLKREG(0x0C554)
  36 #define S5P_CLKDIV_PERIL2               S5P_CLKREG(0x0C558)
  37 #define S5P_CLKDIV_PERIL3               S5P_CLKREG(0x0C55C)
  38 #define S5P_CLKDIV_PERIL4               S5P_CLKREG(0x0C560)
  39 #define S5P_CLKDIV_PERIL5               S5P_CLKREG(0x0C564)
  40
  41 #define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
  42
  43 #define S5P_CLKGATE_IP_PERIL            S5P_CLKREG(0x0C950)
  44
  45 #define S5P_CLKSRC_CORE                 S5P_CLKREG(0x10200)
  46 #define S5P_CLKDIV_CORE0                S5P_CLKREG(0x10500)
  47
  48 #define S5P_APLL_LOCK                   S5P_CLKREG(0x14000)
  49 #define S5P_MPLL_LOCK                   S5P_CLKREG(0x14004)
  50 #define S5P_APLL_CON0                   S5P_CLKREG(0x14100)
  51 #define S5P_APLL_CON1                   S5P_CLKREG(0x14104)
  52 #define S5P_MPLL_CON0                   S5P_CLKREG(0x14108)
  53 #define S5P_MPLL_CON1                   S5P_CLKREG(0x1410C)
  54
  55 #define S5P_CLKSRC_CPU                  S5P_CLKREG(0x14200)
  56 #define S5P_CLKMUX_STATCPU              S5P_CLKREG(0x14400)
  57
  58 #define S5P_CLKDIV_CPU                  S5P_CLKREG(0x14500)
  59 #define S5P_CLKDIV_STATCPU              S5P_CLKREG(0x14600)
  60
  61 #define S5P_CLKGATE_SCLKCPU             S5P_CLKREG(0x14800)
  62
  63 #endif /* __ASM_ARCH_REGS_CLOCK_H */