1 /* linux/arch/arm/mach-s5pc100/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PC100 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
23 #include <plat/cpu-freq.h>
24 #include <mach/regs-clock.h>
25 #include <plat/clock.h>
28 #include <plat/s5p-clock.h>
29 #include <plat/clock-clksrc.h>
30 #include <plat/s5pc100.h>
32 static struct clk s5p_clk_otgphy
= {
37 static struct clk
*clk_src_mout_href_list
[] = {
42 static struct clksrc_sources clk_src_mout_href
= {
43 .sources
= clk_src_mout_href_list
,
44 .nr_sources
= ARRAY_SIZE(clk_src_mout_href_list
),
47 static struct clksrc_clk clk_mout_href
= {
52 .sources
= &clk_src_mout_href
,
53 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 20, .size
= 1 },
56 static struct clk
*clk_src_mout_48m_list
[] = {
58 [1] = &s5p_clk_otgphy
,
61 static struct clksrc_sources clk_src_mout_48m
= {
62 .sources
= clk_src_mout_48m_list
,
63 .nr_sources
= ARRAY_SIZE(clk_src_mout_48m_list
),
66 static struct clksrc_clk clk_mout_48m
= {
71 .sources
= &clk_src_mout_48m
,
72 .reg_src
= { .reg
= S5P_CLK_SRC1
, .shift
= 24, .size
= 1 },
75 static struct clksrc_clk clk_mout_mpll
= {
80 .sources
= &clk_src_mpll
,
81 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 4, .size
= 1 },
85 static struct clksrc_clk clk_mout_apll
= {
90 .sources
= &clk_src_apll
,
91 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 0, .size
= 1 },
94 static struct clksrc_clk clk_mout_epll
= {
99 .sources
= &clk_src_epll
,
100 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 8, .size
= 1 },
103 static struct clk
*clk_src_mout_hpll_list
[] = {
107 static struct clksrc_sources clk_src_mout_hpll
= {
108 .sources
= clk_src_mout_hpll_list
,
109 .nr_sources
= ARRAY_SIZE(clk_src_mout_hpll_list
),
112 static struct clksrc_clk clk_mout_hpll
= {
117 .sources
= &clk_src_mout_hpll
,
118 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 12, .size
= 1 },
121 static struct clksrc_clk clk_div_apll
= {
125 .parent
= &clk_mout_apll
.clk
,
127 .reg_div
= { .reg
= S5P_CLK_DIV0
, .shift
= 0, .size
= 1 },
130 static struct clksrc_clk clk_div_arm
= {
134 .parent
= &clk_div_apll
.clk
,
136 .reg_div
= { .reg
= S5P_CLK_DIV0
, .shift
= 4, .size
= 3 },
139 static struct clksrc_clk clk_div_d0_bus
= {
141 .name
= "div_d0_bus",
143 .parent
= &clk_div_arm
.clk
,
145 .reg_div
= { .reg
= S5P_CLK_DIV0
, .shift
= 8, .size
= 3 },
148 static struct clksrc_clk clk_div_pclkd0
= {
150 .name
= "div_pclkd0",
152 .parent
= &clk_div_d0_bus
.clk
,
154 .reg_div
= { .reg
= S5P_CLK_DIV0
, .shift
= 12, .size
= 3 },
157 static struct clksrc_clk clk_div_secss
= {
161 .parent
= &clk_div_d0_bus
.clk
,
163 .reg_div
= { .reg
= S5P_CLK_DIV0
, .shift
= 16, .size
= 3 },
166 static struct clksrc_clk clk_div_apll2
= {
170 .parent
= &clk_mout_apll
.clk
,
172 .reg_div
= { .reg
= S5P_CLK_DIV1
, .shift
= 0, .size
= 3 },
175 static struct clk
*clk_src_mout_am_list
[] = {
176 [0] = &clk_mout_mpll
.clk
,
177 [1] = &clk_div_apll2
.clk
,
180 struct clksrc_sources clk_src_mout_am
= {
181 .sources
= clk_src_mout_am_list
,
182 .nr_sources
= ARRAY_SIZE(clk_src_mout_am_list
),
185 static struct clksrc_clk clk_mout_am
= {
190 .sources
= &clk_src_mout_am
,
191 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 16, .size
= 1 },
194 static struct clksrc_clk clk_div_d1_bus
= {
196 .name
= "div_d1_bus",
198 .parent
= &clk_mout_am
.clk
,
200 .reg_div
= { .reg
= S5P_CLK_DIV1
, .shift
= 12, .size
= 3 },
203 static struct clksrc_clk clk_div_mpll2
= {
207 .parent
= &clk_mout_am
.clk
,
209 .reg_div
= { .reg
= S5P_CLK_DIV1
, .shift
= 8, .size
= 1 },
212 static struct clksrc_clk clk_div_mpll
= {
216 .parent
= &clk_mout_am
.clk
,
218 .reg_div
= { .reg
= S5P_CLK_DIV1
, .shift
= 4, .size
= 2 },
221 static struct clk
*clk_src_mout_onenand_list
[] = {
222 [0] = &clk_div_d0_bus
.clk
,
223 [1] = &clk_div_d1_bus
.clk
,
226 struct clksrc_sources clk_src_mout_onenand
= {
227 .sources
= clk_src_mout_onenand_list
,
228 .nr_sources
= ARRAY_SIZE(clk_src_mout_onenand_list
),
231 static struct clksrc_clk clk_mout_onenand
= {
233 .name
= "mout_onenand",
236 .sources
= &clk_src_mout_onenand
,
237 .reg_src
= { .reg
= S5P_CLK_SRC0
, .shift
= 24, .size
= 1 },
240 static struct clksrc_clk clk_div_onenand
= {
242 .name
= "div_onenand",
244 .parent
= &clk_mout_onenand
.clk
,
246 .reg_div
= { .reg
= S5P_CLK_DIV1
, .shift
= 20, .size
= 2 },
249 static struct clksrc_clk clk_div_pclkd1
= {
251 .name
= "div_pclkd1",
253 .parent
= &clk_div_d1_bus
.clk
,
255 .reg_div
= { .reg
= S5P_CLK_DIV1
, .shift
= 16, .size
= 3 },
258 static struct clksrc_clk clk_div_cam
= {
262 .parent
= &clk_div_mpll2
.clk
,
264 .reg_div
= { .reg
= S5P_CLK_DIV1
, .shift
= 24, .size
= 5 },
267 static struct clksrc_clk clk_div_hdmi
= {
271 .parent
= &clk_mout_hpll
.clk
,
273 .reg_div
= { .reg
= S5P_CLK_DIV3
, .shift
= 28, .size
= 4 },
276 static int s5pc100_epll_enable(struct clk
*clk
, int enable
)
278 unsigned int ctrlbit
= clk
->ctrlbit
;
279 unsigned int epll_con
= __raw_readl(S5P_EPLL_CON
) & ~ctrlbit
;
282 __raw_writel(epll_con
| ctrlbit
, S5P_EPLL_CON
);
284 __raw_writel(epll_con
, S5P_EPLL_CON
);
289 static unsigned long s5pc100_epll_get_rate(struct clk
*clk
)
294 static u32 epll_div
[][4] = {
295 { 32750000, 131, 3, 4 },
296 { 32768000, 131, 3, 4 },
297 { 36000000, 72, 3, 3 },
298 { 45000000, 90, 3, 3 },
299 { 45158000, 90, 3, 3 },
300 { 45158400, 90, 3, 3 },
301 { 48000000, 96, 3, 3 },
302 { 49125000, 131, 4, 3 },
303 { 49152000, 131, 4, 3 },
304 { 60000000, 120, 3, 3 },
305 { 67737600, 226, 5, 3 },
306 { 67738000, 226, 5, 3 },
307 { 73800000, 246, 5, 3 },
308 { 73728000, 246, 5, 3 },
309 { 72000000, 144, 3, 3 },
310 { 84000000, 168, 3, 3 },
311 { 96000000, 96, 3, 2 },
312 { 144000000, 144, 3, 2 },
313 { 192000000, 96, 3, 1 }
316 static int s5pc100_epll_set_rate(struct clk
*clk
, unsigned long rate
)
318 unsigned int epll_con
;
321 if (clk
->rate
== rate
) /* Return if nothing changed */
324 epll_con
= __raw_readl(S5P_EPLL_CON
);
326 epll_con
&= ~(PLL65XX_MDIV_MASK
| PLL65XX_PDIV_MASK
| PLL65XX_SDIV_MASK
);
328 for (i
= 0; i
< ARRAY_SIZE(epll_div
); i
++) {
329 if (epll_div
[i
][0] == rate
) {
330 epll_con
|= (epll_div
[i
][1] << PLL65XX_MDIV_SHIFT
) |
331 (epll_div
[i
][2] << PLL65XX_PDIV_SHIFT
) |
332 (epll_div
[i
][3] << PLL65XX_SDIV_SHIFT
);
337 if (i
== ARRAY_SIZE(epll_div
)) {
338 printk(KERN_ERR
"%s: Invalid Clock EPLL Frequency\n", __func__
);
342 __raw_writel(epll_con
, S5P_EPLL_CON
);
349 static struct clk_ops s5pc100_epll_ops
= {
350 .get_rate
= s5pc100_epll_get_rate
,
351 .set_rate
= s5pc100_epll_set_rate
,
354 static int s5pc100_d0_0_ctrl(struct clk
*clk
, int enable
)
356 return s5p_gatectrl(S5P_CLKGATE_D00
, clk
, enable
);
359 static int s5pc100_d0_1_ctrl(struct clk
*clk
, int enable
)
361 return s5p_gatectrl(S5P_CLKGATE_D01
, clk
, enable
);
364 static int s5pc100_d0_2_ctrl(struct clk
*clk
, int enable
)
366 return s5p_gatectrl(S5P_CLKGATE_D02
, clk
, enable
);
369 static int s5pc100_d1_0_ctrl(struct clk
*clk
, int enable
)
371 return s5p_gatectrl(S5P_CLKGATE_D10
, clk
, enable
);
374 static int s5pc100_d1_1_ctrl(struct clk
*clk
, int enable
)
376 return s5p_gatectrl(S5P_CLKGATE_D11
, clk
, enable
);
379 static int s5pc100_d1_2_ctrl(struct clk
*clk
, int enable
)
381 return s5p_gatectrl(S5P_CLKGATE_D12
, clk
, enable
);
384 static int s5pc100_d1_3_ctrl(struct clk
*clk
, int enable
)
386 return s5p_gatectrl(S5P_CLKGATE_D13
, clk
, enable
);
389 static int s5pc100_d1_4_ctrl(struct clk
*clk
, int enable
)
391 return s5p_gatectrl(S5P_CLKGATE_D14
, clk
, enable
);
394 static int s5pc100_d1_5_ctrl(struct clk
*clk
, int enable
)
396 return s5p_gatectrl(S5P_CLKGATE_D15
, clk
, enable
);
399 static int s5pc100_sclk0_ctrl(struct clk
*clk
, int enable
)
401 return s5p_gatectrl(S5P_CLKGATE_SCLK0
, clk
, enable
);
404 static int s5pc100_sclk1_ctrl(struct clk
*clk
, int enable
)
406 return s5p_gatectrl(S5P_CLKGATE_SCLK1
, clk
, enable
);
410 * The following clocks will be disabled during clock initialization. It is
411 * recommended to keep the following clocks disabled until the driver requests
412 * for enabling the clock.
414 static struct clk init_clocks_disable
[] = {
418 .parent
= &clk_div_d0_bus
.clk
,
419 .enable
= s5pc100_d0_0_ctrl
,
424 .parent
= &clk_div_d0_bus
.clk
,
425 .enable
= s5pc100_d0_0_ctrl
,
430 .parent
= &clk_div_d0_bus
.clk
,
431 .enable
= s5pc100_d0_0_ctrl
,
436 .parent
= &clk_div_d0_bus
.clk
,
437 .enable
= s5pc100_d0_0_ctrl
,
442 .parent
= &clk_div_d0_bus
.clk
,
443 .enable
= s5pc100_d0_0_ctrl
,
448 .parent
= &clk_div_d0_bus
.clk
,
449 .enable
= s5pc100_d0_1_ctrl
,
454 .parent
= &clk_div_d0_bus
.clk
,
455 .enable
= s5pc100_d0_1_ctrl
,
460 .parent
= &clk_div_d0_bus
.clk
,
461 .enable
= s5pc100_d0_2_ctrl
,
466 .parent
= &clk_div_d0_bus
.clk
,
467 .enable
= s5pc100_d0_2_ctrl
,
472 .parent
= &clk_div_d1_bus
.clk
,
473 .enable
= s5pc100_d1_0_ctrl
,
478 .parent
= &clk_div_d1_bus
.clk
,
479 .enable
= s5pc100_d1_0_ctrl
,
484 .parent
= &clk_div_d1_bus
.clk
,
485 .enable
= s5pc100_d1_0_ctrl
,
490 .parent
= &clk_div_d1_bus
.clk
,
491 .enable
= s5pc100_d1_0_ctrl
,
496 .parent
= &clk_div_d1_bus
.clk
,
497 .enable
= s5pc100_d1_0_ctrl
,
502 .parent
= &clk_div_d1_bus
.clk
,
503 .enable
= s5pc100_d1_0_ctrl
,
508 .parent
= &clk_div_d1_bus
.clk
,
509 .enable
= s5pc100_d1_0_ctrl
,
514 .parent
= &clk_div_d1_bus
.clk
,
515 .enable
= s5pc100_d1_0_ctrl
,
520 .parent
= &clk_div_d1_bus
.clk
,
521 .enable
= s5pc100_d1_1_ctrl
,
526 .parent
= &clk_div_d1_bus
.clk
,
527 .enable
= s5pc100_d1_1_ctrl
,
532 .parent
= &clk_div_d1_bus
.clk
,
533 .enable
= s5pc100_d1_1_ctrl
,
538 .parent
= &clk_div_d1_bus
.clk
,
539 .enable
= s5pc100_d1_1_ctrl
,
544 .parent
= &clk_div_d1_bus
.clk
,
545 .enable
= s5pc100_d1_1_ctrl
,
550 .parent
= &clk_div_d1_bus
.clk
,
551 .enable
= s5pc100_d1_1_ctrl
,
556 .parent
= &clk_div_d1_bus
.clk
,
557 .enable
= s5pc100_d1_1_ctrl
,
562 .parent
= &clk_div_d1_bus
.clk
,
563 .enable
= s5pc100_d1_1_ctrl
,
568 .parent
= &clk_div_d1_bus
.clk
,
569 .enable
= s5pc100_d1_0_ctrl
,
574 .parent
= &clk_div_d1_bus
.clk
,
575 .enable
= s5pc100_d1_2_ctrl
,
580 .parent
= &clk_div_d1_bus
.clk
,
581 .enable
= s5pc100_d1_2_ctrl
,
586 .parent
= &clk_div_d1_bus
.clk
,
587 .enable
= s5pc100_d1_2_ctrl
,
592 .parent
= &clk_div_d1_bus
.clk
,
593 .enable
= s5pc100_d1_2_ctrl
,
598 .parent
= &clk_div_d1_bus
.clk
,
599 .enable
= s5pc100_d1_2_ctrl
,
604 .parent
= &clk_div_d1_bus
.clk
,
605 .enable
= s5pc100_d1_3_ctrl
,
610 .parent
= &clk_div_d1_bus
.clk
,
611 .enable
= s5pc100_d1_3_ctrl
,
616 .parent
= &clk_div_d1_bus
.clk
,
617 .enable
= s5pc100_d1_3_ctrl
,
622 .parent
= &clk_div_d1_bus
.clk
,
623 .enable
= s5pc100_d1_3_ctrl
,
628 .parent
= &clk_div_d1_bus
.clk
,
629 .enable
= s5pc100_d1_3_ctrl
,
634 .parent
= &clk_div_d1_bus
.clk
,
635 .enable
= s5pc100_d1_4_ctrl
,
640 .parent
= &clk_div_d1_bus
.clk
,
641 .enable
= s5pc100_d1_4_ctrl
,
646 .parent
= &clk_div_d1_bus
.clk
,
647 .enable
= s5pc100_d1_4_ctrl
,
652 .parent
= &clk_div_d1_bus
.clk
,
653 .enable
= s5pc100_d1_4_ctrl
,
658 .parent
= &clk_div_d1_bus
.clk
,
659 .enable
= s5pc100_d1_4_ctrl
,
664 .parent
= &clk_div_d1_bus
.clk
,
665 .enable
= s5pc100_d1_4_ctrl
,
670 .parent
= &clk_div_d1_bus
.clk
,
671 .enable
= s5pc100_d1_4_ctrl
,
672 .ctrlbit
= (1 << 10),
676 .parent
= &clk_div_d1_bus
.clk
,
677 .enable
= s5pc100_d1_4_ctrl
,
678 .ctrlbit
= (1 << 11),
682 .parent
= &clk_div_d1_bus
.clk
,
683 .enable
= s5pc100_d1_4_ctrl
,
684 .ctrlbit
= (1 << 12),
688 .parent
= &clk_div_d1_bus
.clk
,
689 .enable
= s5pc100_d1_4_ctrl
,
690 .ctrlbit
= (1 << 13),
694 .parent
= &clk_div_d1_bus
.clk
,
695 .enable
= s5pc100_d1_5_ctrl
,
700 .parent
= &clk_div_d1_bus
.clk
,
701 .enable
= s5pc100_d1_5_ctrl
,
706 .parent
= &clk_div_d1_bus
.clk
,
707 .enable
= s5pc100_d1_5_ctrl
,
712 .parent
= &clk_div_d1_bus
.clk
,
713 .enable
= s5pc100_d1_5_ctrl
,
718 .parent
= &clk_div_d1_bus
.clk
,
719 .enable
= s5pc100_d1_5_ctrl
,
724 .parent
= &clk_div_d1_bus
.clk
,
725 .enable
= s5pc100_d1_5_ctrl
,
730 .parent
= &clk_div_d1_bus
.clk
,
731 .enable
= s5pc100_d1_5_ctrl
,
736 .parent
= &clk_div_d1_bus
.clk
,
737 .enable
= s5pc100_d1_5_ctrl
,
742 .parent
= &clk_div_d1_bus
.clk
,
743 .enable
= s5pc100_d1_5_ctrl
,
748 .parent
= &clk_mout_48m
.clk
,
749 .enable
= s5pc100_sclk0_ctrl
,
754 .parent
= &clk_mout_48m
.clk
,
755 .enable
= s5pc100_sclk0_ctrl
,
760 .parent
= &clk_mout_48m
.clk
,
761 .enable
= s5pc100_sclk0_ctrl
,
766 .parent
= &clk_mout_48m
.clk
,
767 .enable
= s5pc100_sclk0_ctrl
,
768 .ctrlbit
= (1 << 15),
772 .parent
= &clk_mout_48m
.clk
,
773 .enable
= s5pc100_sclk0_ctrl
,
774 .ctrlbit
= (1 << 16),
778 .parent
= &clk_mout_48m
.clk
,
779 .enable
= s5pc100_sclk0_ctrl
,
780 .ctrlbit
= (1 << 17),
784 static struct clk clk_vclk54m
= {
790 static struct clk clk_i2scdclk0
= {
791 .name
= "i2s_cdclk0",
795 static struct clk clk_i2scdclk1
= {
796 .name
= "i2s_cdclk1",
800 static struct clk clk_i2scdclk2
= {
801 .name
= "i2s_cdclk2",
805 static struct clk clk_pcmcdclk0
= {
806 .name
= "pcm_cdclk0",
810 static struct clk clk_pcmcdclk1
= {
811 .name
= "pcm_cdclk1",
815 static struct clk
*clk_src_group1_list
[] = {
816 [0] = &clk_mout_epll
.clk
,
817 [1] = &clk_div_mpll2
.clk
,
819 [3] = &clk_mout_hpll
.clk
,
822 struct clksrc_sources clk_src_group1
= {
823 .sources
= clk_src_group1_list
,
824 .nr_sources
= ARRAY_SIZE(clk_src_group1_list
),
827 static struct clk
*clk_src_group2_list
[] = {
828 [0] = &clk_mout_epll
.clk
,
829 [1] = &clk_div_mpll
.clk
,
832 struct clksrc_sources clk_src_group2
= {
833 .sources
= clk_src_group2_list
,
834 .nr_sources
= ARRAY_SIZE(clk_src_group2_list
),
837 static struct clk
*clk_src_group3_list
[] = {
838 [0] = &clk_mout_epll
.clk
,
839 [1] = &clk_div_mpll
.clk
,
841 [3] = &clk_i2scdclk0
,
842 [4] = &clk_pcmcdclk0
,
843 [5] = &clk_mout_hpll
.clk
,
846 struct clksrc_sources clk_src_group3
= {
847 .sources
= clk_src_group3_list
,
848 .nr_sources
= ARRAY_SIZE(clk_src_group3_list
),
851 static struct clk
*clk_src_group4_list
[] = {
852 [0] = &clk_mout_epll
.clk
,
853 [1] = &clk_div_mpll
.clk
,
855 [3] = &clk_i2scdclk1
,
856 [4] = &clk_pcmcdclk1
,
857 [5] = &clk_mout_hpll
.clk
,
860 struct clksrc_sources clk_src_group4
= {
861 .sources
= clk_src_group4_list
,
862 .nr_sources
= ARRAY_SIZE(clk_src_group4_list
),
865 static struct clk
*clk_src_group5_list
[] = {
866 [0] = &clk_mout_epll
.clk
,
867 [1] = &clk_div_mpll
.clk
,
869 [3] = &clk_i2scdclk2
,
870 [4] = &clk_mout_hpll
.clk
,
873 struct clksrc_sources clk_src_group5
= {
874 .sources
= clk_src_group5_list
,
875 .nr_sources
= ARRAY_SIZE(clk_src_group5_list
),
878 static struct clk
*clk_src_group6_list
[] = {
881 [2] = &clk_div_hdmi
.clk
,
884 struct clksrc_sources clk_src_group6
= {
885 .sources
= clk_src_group6_list
,
886 .nr_sources
= ARRAY_SIZE(clk_src_group6_list
),
889 static struct clk
*clk_src_group7_list
[] = {
890 [0] = &clk_mout_epll
.clk
,
891 [1] = &clk_div_mpll
.clk
,
892 [2] = &clk_mout_hpll
.clk
,
896 struct clksrc_sources clk_src_group7
= {
897 .sources
= clk_src_group7_list
,
898 .nr_sources
= ARRAY_SIZE(clk_src_group7_list
),
901 static struct clk
*clk_src_mmc0_list
[] = {
902 [0] = &clk_mout_epll
.clk
,
903 [1] = &clk_div_mpll
.clk
,
907 struct clksrc_sources clk_src_mmc0
= {
908 .sources
= clk_src_mmc0_list
,
909 .nr_sources
= ARRAY_SIZE(clk_src_mmc0_list
),
912 static struct clk
*clk_src_mmc12_list
[] = {
913 [0] = &clk_mout_epll
.clk
,
914 [1] = &clk_div_mpll
.clk
,
916 [3] = &clk_mout_hpll
.clk
,
919 struct clksrc_sources clk_src_mmc12
= {
920 .sources
= clk_src_mmc12_list
,
921 .nr_sources
= ARRAY_SIZE(clk_src_mmc12_list
),
924 static struct clk
*clk_src_irda_usb_list
[] = {
925 [0] = &clk_mout_epll
.clk
,
926 [1] = &clk_div_mpll
.clk
,
928 [3] = &clk_mout_hpll
.clk
,
931 struct clksrc_sources clk_src_irda_usb
= {
932 .sources
= clk_src_irda_usb_list
,
933 .nr_sources
= ARRAY_SIZE(clk_src_irda_usb_list
),
936 static struct clk
*clk_src_pwi_list
[] = {
938 [1] = &clk_mout_epll
.clk
,
939 [2] = &clk_div_mpll
.clk
,
942 struct clksrc_sources clk_src_pwi
= {
943 .sources
= clk_src_pwi_list
,
944 .nr_sources
= ARRAY_SIZE(clk_src_pwi_list
),
947 static struct clksrc_clk clksrcs
[] = {
953 .enable
= s5pc100_sclk0_ctrl
,
956 .sources
= &clk_src_group1
,
957 .reg_src
= { .reg
= S5P_CLK_SRC1
, .shift
= 4, .size
= 2 },
958 .reg_div
= { .reg
= S5P_CLK_DIV2
, .shift
= 4, .size
= 4 },
964 .enable
= s5pc100_sclk0_ctrl
,
967 .sources
= &clk_src_group1
,
968 .reg_src
= { .reg
= S5P_CLK_SRC1
, .shift
= 8, .size
= 2 },
969 .reg_div
= { .reg
= S5P_CLK_DIV2
, .shift
= 8, .size
= 4 },
975 .enable
= s5pc100_sclk0_ctrl
,
978 .sources
= &clk_src_group1
,
979 .reg_src
= { .reg
= S5P_CLK_SRC1
, .shift
= 12, .size
= 2 },
980 .reg_div
= { .reg
= S5P_CLK_DIV2
, .shift
= 12, .size
= 4 },
986 .enable
= s5pc100_sclk0_ctrl
,
989 .sources
= &clk_src_group2
,
990 .reg_src
= { .reg
= S5P_CLK_SRC1
, .shift
= 0, .size
= 1 },
991 .reg_div
= { .reg
= S5P_CLK_DIV2
, .shift
= 0, .size
= 4 },
994 .name
= "sclk_mixer",
997 .enable
= s5pc100_sclk0_ctrl
,
1000 .sources
= &clk_src_group6
,
1001 .reg_src
= { .reg
= S5P_CLK_SRC2
, .shift
= 28, .size
= 2 },
1004 .name
= "sclk_audio",
1006 .ctrlbit
= (1 << 8),
1007 .enable
= s5pc100_sclk1_ctrl
,
1010 .sources
= &clk_src_group3
,
1011 .reg_src
= { .reg
= S5P_CLK_SRC3
, .shift
= 12, .size
= 3 },
1012 .reg_div
= { .reg
= S5P_CLK_DIV4
, .shift
= 12, .size
= 4 },
1015 .name
= "sclk_audio",
1017 .ctrlbit
= (1 << 9),
1018 .enable
= s5pc100_sclk1_ctrl
,
1021 .sources
= &clk_src_group4
,
1022 .reg_src
= { .reg
= S5P_CLK_SRC3
, .shift
= 16, .size
= 3 },
1023 .reg_div
= { .reg
= S5P_CLK_DIV4
, .shift
= 16, .size
= 4 },
1026 .name
= "sclk_audio",
1028 .ctrlbit
= (1 << 10),
1029 .enable
= s5pc100_sclk1_ctrl
,
1032 .sources
= &clk_src_group5
,
1033 .reg_src
= { .reg
= S5P_CLK_SRC3
, .shift
= 20, .size
= 3 },
1034 .reg_div
= { .reg
= S5P_CLK_DIV4
, .shift
= 20, .size
= 4 },
1039 .ctrlbit
= (1 << 0),
1040 .enable
= s5pc100_sclk1_ctrl
,
1043 .sources
= &clk_src_group7
,
1044 .reg_src
= { .reg
= S5P_CLK_SRC2
, .shift
= 12, .size
= 2 },
1045 .reg_div
= { .reg
= S5P_CLK_DIV3
, .shift
= 12, .size
= 4 },
1048 .name
= "sclk_fimc",
1050 .ctrlbit
= (1 << 1),
1051 .enable
= s5pc100_sclk1_ctrl
,
1054 .sources
= &clk_src_group7
,
1055 .reg_src
= { .reg
= S5P_CLK_SRC2
, .shift
= 16, .size
= 2 },
1056 .reg_div
= { .reg
= S5P_CLK_DIV3
, .shift
= 16, .size
= 4 },
1059 .name
= "sclk_fimc",
1061 .ctrlbit
= (1 << 2),
1062 .enable
= s5pc100_sclk1_ctrl
,
1065 .sources
= &clk_src_group7
,
1066 .reg_src
= { .reg
= S5P_CLK_SRC2
, .shift
= 20, .size
= 2 },
1067 .reg_div
= { .reg
= S5P_CLK_DIV3
, .shift
= 20, .size
= 4 },
1070 .name
= "sclk_fimc",
1072 .ctrlbit
= (1 << 3),
1073 .enable
= s5pc100_sclk1_ctrl
,
1076 .sources
= &clk_src_group7
,
1077 .reg_src
= { .reg
= S5P_CLK_SRC2
, .shift
= 24, .size
= 2 },
1078 .reg_div
= { .reg
= S5P_CLK_DIV3
, .shift
= 24, .size
= 4 },
1083 .ctrlbit
= (1 << 12),
1084 .enable
= s5pc100_sclk1_ctrl
,
1087 .sources
= &clk_src_mmc0
,
1088 .reg_src
= { .reg
= S5P_CLK_SRC2
, .shift
= 0, .size
= 2 },
1089 .reg_div
= { .reg
= S5P_CLK_DIV3
, .shift
= 0, .size
= 4 },
1094 .ctrlbit
= (1 << 13),
1095 .enable
= s5pc100_sclk1_ctrl
,
1098 .sources
= &clk_src_mmc12
,
1099 .reg_src
= { .reg
= S5P_CLK_SRC2
, .shift
= 4, .size
= 2 },
1100 .reg_div
= { .reg
= S5P_CLK_DIV3
, .shift
= 4, .size
= 4 },
1105 .ctrlbit
= (1 << 14),
1106 .enable
= s5pc100_sclk1_ctrl
,
1109 .sources
= &clk_src_mmc12
,
1110 .reg_src
= { .reg
= S5P_CLK_SRC2
, .shift
= 8, .size
= 2 },
1111 .reg_div
= { .reg
= S5P_CLK_DIV3
, .shift
= 8, .size
= 4 },
1114 .name
= "sclk_irda",
1116 .ctrlbit
= (1 << 10),
1117 .enable
= s5pc100_sclk0_ctrl
,
1120 .sources
= &clk_src_irda_usb
,
1121 .reg_src
= { .reg
= S5P_CLK_SRC2
, .shift
= 8, .size
= 2 },
1122 .reg_div
= { .reg
= S5P_CLK_DIV3
, .shift
= 8, .size
= 4 },
1125 .name
= "sclk_irda",
1127 .ctrlbit
= (1 << 10),
1128 .enable
= s5pc100_sclk0_ctrl
,
1131 .sources
= &clk_src_mmc12
,
1132 .reg_src
= { .reg
= S5P_CLK_SRC1
, .shift
= 16, .size
= 2 },
1133 .reg_div
= { .reg
= S5P_CLK_DIV2
, .shift
= 16, .size
= 4 },
1138 .ctrlbit
= (1 << 1),
1139 .enable
= s5pc100_sclk0_ctrl
,
1142 .sources
= &clk_src_pwi
,
1143 .reg_src
= { .reg
= S5P_CLK_SRC3
, .shift
= 0, .size
= 2 },
1144 .reg_div
= { .reg
= S5P_CLK_DIV4
, .shift
= 0, .size
= 3 },
1147 .name
= "sclk_uhost",
1149 .ctrlbit
= (1 << 11),
1150 .enable
= s5pc100_sclk0_ctrl
,
1153 .sources
= &clk_src_irda_usb
,
1154 .reg_src
= { .reg
= S5P_CLK_SRC1
, .shift
= 20, .size
= 2 },
1155 .reg_div
= { .reg
= S5P_CLK_DIV2
, .shift
= 20, .size
= 4 },
1159 /* Clock initialisation code */
1160 static struct clksrc_clk
*sysclks
[] = {
1184 void __init_or_cpufreq
s5pc100_setup_clocks(void)
1188 unsigned long hclkd0
;
1189 unsigned long hclkd1
;
1190 unsigned long pclkd0
;
1191 unsigned long pclkd1
;
1198 /* Set S5PC100 functions for clk_fout_epll */
1199 clk_fout_epll
.enable
= s5pc100_epll_enable
;
1200 clk_fout_epll
.ops
= &s5pc100_epll_ops
;
1202 printk(KERN_DEBUG
"%s: registering clocks\n", __func__
);
1204 xtal
= clk_get_rate(&clk_xtal
);
1206 printk(KERN_DEBUG
"%s: xtal is %ld\n", __func__
, xtal
);
1208 apll
= s5p_get_pll65xx(xtal
, __raw_readl(S5P_APLL_CON
));
1209 mpll
= s5p_get_pll65xx(xtal
, __raw_readl(S5P_MPLL_CON
));
1210 epll
= s5p_get_pll65xx(xtal
, __raw_readl(S5P_EPLL_CON
));
1211 hpll
= s5p_get_pll65xx(xtal
, __raw_readl(S5P_HPLL_CON
));
1213 printk(KERN_INFO
"S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1214 print_mhz(apll
), print_mhz(mpll
), print_mhz(epll
), print_mhz(hpll
));
1216 clk_fout_apll
.rate
= apll
;
1217 clk_fout_mpll
.rate
= mpll
;
1218 clk_fout_epll
.rate
= epll
;
1219 clk_mout_hpll
.clk
.rate
= hpll
;
1221 for (ptr
= 0; ptr
< ARRAY_SIZE(clksrcs
); ptr
++)
1222 s3c_set_clksrc(&clksrcs
[ptr
], true);
1224 arm
= clk_get_rate(&clk_div_arm
.clk
);
1225 hclkd0
= clk_get_rate(&clk_div_d0_bus
.clk
);
1226 pclkd0
= clk_get_rate(&clk_div_pclkd0
.clk
);
1227 hclkd1
= clk_get_rate(&clk_div_d1_bus
.clk
);
1228 pclkd1
= clk_get_rate(&clk_div_pclkd1
.clk
);
1230 printk(KERN_INFO
"S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1231 print_mhz(hclkd0
), print_mhz(hclkd1
), print_mhz(pclkd0
), print_mhz(pclkd1
));
1234 clk_h
.rate
= hclkd1
;
1235 clk_p
.rate
= pclkd1
;
1239 * The following clocks will be enabled during clock initialization.
1241 static struct clk init_clocks
[] = {
1245 .parent
= &clk_div_d0_bus
.clk
,
1246 .enable
= s5pc100_d0_0_ctrl
,
1247 .ctrlbit
= (1 << 1),
1251 .parent
= &clk_div_d0_bus
.clk
,
1252 .enable
= s5pc100_d0_0_ctrl
,
1253 .ctrlbit
= (1 << 0),
1257 .parent
= &clk_div_d0_bus
.clk
,
1258 .enable
= s5pc100_d0_1_ctrl
,
1259 .ctrlbit
= (1 << 5),
1263 .parent
= &clk_div_d0_bus
.clk
,
1264 .enable
= s5pc100_d0_1_ctrl
,
1265 .ctrlbit
= (1 << 4),
1269 .parent
= &clk_div_d0_bus
.clk
,
1270 .enable
= s5pc100_d0_1_ctrl
,
1271 .ctrlbit
= (1 << 1),
1275 .parent
= &clk_div_d0_bus
.clk
,
1276 .enable
= s5pc100_d0_1_ctrl
,
1277 .ctrlbit
= (1 << 0),
1281 .parent
= &clk_div_d0_bus
.clk
,
1282 .enable
= s5pc100_d0_1_ctrl
,
1283 .ctrlbit
= (1 << 0),
1287 .parent
= &clk_div_d1_bus
.clk
,
1288 .enable
= s5pc100_d1_3_ctrl
,
1289 .ctrlbit
= (1 << 1),
1293 .parent
= &clk_div_d1_bus
.clk
,
1294 .enable
= s5pc100_d1_4_ctrl
,
1295 .ctrlbit
= (1 << 0),
1299 .parent
= &clk_div_d1_bus
.clk
,
1300 .enable
= s5pc100_d1_4_ctrl
,
1301 .ctrlbit
= (1 << 1),
1305 .parent
= &clk_div_d1_bus
.clk
,
1306 .enable
= s5pc100_d1_4_ctrl
,
1307 .ctrlbit
= (1 << 2),
1311 .parent
= &clk_div_d1_bus
.clk
,
1312 .enable
= s5pc100_d1_4_ctrl
,
1313 .ctrlbit
= (1 << 3),
1317 .parent
= &clk_div_d1_bus
.clk
,
1318 .enable
= s5pc100_d1_3_ctrl
,
1319 .ctrlbit
= (1 << 6),
1323 static struct clk
*clks
[] __initdata
= {
1332 void __init
s5pc100_register_clocks(void)
1338 s3c24xx_register_clocks(clks
, ARRAY_SIZE(clks
));
1340 for (ptr
= 0; ptr
< ARRAY_SIZE(sysclks
); ptr
++)
1341 s3c_register_clksrc(sysclks
[ptr
], 1);
1343 s3c_register_clksrc(clksrcs
, ARRAY_SIZE(clksrcs
));
1344 s3c_register_clocks(init_clocks
, ARRAY_SIZE(init_clocks
));
1346 clkp
= init_clocks_disable
;
1347 for (ptr
= 0; ptr
< ARRAY_SIZE(init_clocks_disable
); ptr
++, clkp
++) {
1349 ret
= s3c24xx_register_clock(clkp
);
1351 printk(KERN_ERR
"Failed to register clock %s (%d)\n",
1354 (clkp
->enable
)(clkp
, 0);