2 * OMAP3/4 - specific DPLL control functions
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
13 * Parts of this code are based on code written by
14 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
28 #include <linux/bitops.h>
31 #include <plat/clock.h>
32 #include <asm/clkdev.h>
36 #include "prm-regbits-34xx.h"
38 #include "cm-regbits-34xx.h"
40 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
41 #define DPLL_AUTOIDLE_DISABLE 0x0
42 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
44 #define MAX_DPLL_WAIT_TRIES 1000000
46 /* Private functions */
48 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
49 static void _omap3_dpll_write_clken(struct clk
*clk
, u8 clken_bits
)
51 const struct dpll_data
*dd
;
56 v
= __raw_readl(dd
->control_reg
);
57 v
&= ~dd
->enable_mask
;
58 v
|= clken_bits
<< __ffs(dd
->enable_mask
);
59 __raw_writel(v
, dd
->control_reg
);
62 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
63 static int _omap3_wait_dpll_status(struct clk
*clk
, u8 state
)
65 const struct dpll_data
*dd
;
71 state
<<= __ffs(dd
->idlest_mask
);
73 while (((__raw_readl(dd
->idlest_reg
) & dd
->idlest_mask
) != state
) &&
74 i
< MAX_DPLL_WAIT_TRIES
) {
79 if (i
== MAX_DPLL_WAIT_TRIES
) {
80 printk(KERN_ERR
"clock: %s failed transition to '%s'\n",
81 clk
->name
, (state
) ? "locked" : "bypassed");
83 pr_debug("clock: %s transition to '%s' in %d loops\n",
84 clk
->name
, (state
) ? "locked" : "bypassed", i
);
92 /* From 3430 TRM ES2 4.7.6.2 */
93 static u16
_omap3_dpll_compute_freqsel(struct clk
*clk
, u8 n
)
98 fint
= clk
->dpll_data
->clk_ref
->rate
/ n
;
100 pr_debug("clock: fint is %lu\n", fint
);
102 if (fint
>= 750000 && fint
<= 1000000)
104 else if (fint
> 1000000 && fint
<= 1250000)
106 else if (fint
> 1250000 && fint
<= 1500000)
108 else if (fint
> 1500000 && fint
<= 1750000)
110 else if (fint
> 1750000 && fint
<= 2100000)
112 else if (fint
> 7500000 && fint
<= 10000000)
114 else if (fint
> 10000000 && fint
<= 12500000)
116 else if (fint
> 12500000 && fint
<= 15000000)
118 else if (fint
> 15000000 && fint
<= 17500000)
120 else if (fint
> 17500000 && fint
<= 21000000)
123 pr_debug("clock: unknown freqsel setting for %d\n", n
);
129 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
130 * @clk: pointer to a DPLL struct clk
132 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
133 * readiness before returning. Will save and restore the DPLL's
134 * autoidle state across the enable, per the CDP code. If the DPLL
135 * locked successfully, return 0; if the DPLL did not lock in the time
136 * allotted, or DPLL3 was passed in, return -EINVAL.
138 static int _omap3_noncore_dpll_lock(struct clk
*clk
)
143 pr_debug("clock: locking DPLL %s\n", clk
->name
);
145 ai
= omap3_dpll_autoidle_read(clk
);
147 omap3_dpll_deny_idle(clk
);
149 _omap3_dpll_write_clken(clk
, DPLL_LOCKED
);
151 r
= _omap3_wait_dpll_status(clk
, 1);
154 omap3_dpll_allow_idle(clk
);
160 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
161 * @clk: pointer to a DPLL struct clk
163 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
164 * bypass mode, the DPLL's rate is set equal to its parent clock's
165 * rate. Waits for the DPLL to report readiness before returning.
166 * Will save and restore the DPLL's autoidle state across the enable,
167 * per the CDP code. If the DPLL entered bypass mode successfully,
168 * return 0; if the DPLL did not enter bypass in the time allotted, or
169 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
172 static int _omap3_noncore_dpll_bypass(struct clk
*clk
)
177 if (!(clk
->dpll_data
->modes
& (1 << DPLL_LOW_POWER_BYPASS
)))
180 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
183 ai
= omap3_dpll_autoidle_read(clk
);
185 _omap3_dpll_write_clken(clk
, DPLL_LOW_POWER_BYPASS
);
187 r
= _omap3_wait_dpll_status(clk
, 0);
190 omap3_dpll_allow_idle(clk
);
192 omap3_dpll_deny_idle(clk
);
198 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
199 * @clk: pointer to a DPLL struct clk
201 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
202 * restore the DPLL's autoidle state across the stop, per the CDP
203 * code. If DPLL3 was passed in, or the DPLL does not support
204 * low-power stop, return -EINVAL; otherwise, return 0.
206 static int _omap3_noncore_dpll_stop(struct clk
*clk
)
210 if (!(clk
->dpll_data
->modes
& (1 << DPLL_LOW_POWER_STOP
)))
213 pr_debug("clock: stopping DPLL %s\n", clk
->name
);
215 ai
= omap3_dpll_autoidle_read(clk
);
217 _omap3_dpll_write_clken(clk
, DPLL_LOW_POWER_STOP
);
220 omap3_dpll_allow_idle(clk
);
222 omap3_dpll_deny_idle(clk
);
227 static void lookup_dco_sddiv(struct clk
*clk
, u8
*dco
, u8
*sd_div
, u16 m
,
230 unsigned long fint
, clkinp
, sd
; /* watch out for overflow */
233 clkinp
= clk
->parent
->rate
;
234 fint
= (clkinp
/ n
) * m
;
236 if (fint
< 1000000000)
241 * target sigma-delta to near 250MHz
242 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
244 clkinp
/= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
245 mod1
= (clkinp
* m
) % (250 * n
);
246 sd
= (clkinp
* m
) / (250 * n
);
256 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
257 * @clk: struct clk * of DPLL to set
258 * @m: DPLL multiplier to set
259 * @n: DPLL divider to set
260 * @freqsel: FREQSEL value to set
262 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
263 * lock.. Returns -EINVAL upon error, or 0 upon success.
265 static int omap3_noncore_dpll_program(struct clk
*clk
, u16 m
, u8 n
, u16 freqsel
)
267 struct dpll_data
*dd
= clk
->dpll_data
;
270 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
271 _omap3_noncore_dpll_bypass(clk
);
274 * Set jitter correction. No jitter correction for OMAP4 and 3630
275 * since freqsel field is no longer present
277 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
278 v
= __raw_readl(dd
->control_reg
);
279 v
&= ~dd
->freqsel_mask
;
280 v
|= freqsel
<< __ffs(dd
->freqsel_mask
);
281 __raw_writel(v
, dd
->control_reg
);
284 /* Set DPLL multiplier, divider */
285 v
= __raw_readl(dd
->mult_div1_reg
);
286 v
&= ~(dd
->mult_mask
| dd
->div1_mask
);
287 v
|= m
<< __ffs(dd
->mult_mask
);
288 v
|= (n
- 1) << __ffs(dd
->div1_mask
);
290 if ((dd
->flags
& DPLL_J_TYPE
) && !(dd
->flags
& DPLL_NO_DCO_SEL
)) {
292 lookup_dco_sddiv(clk
, &dco
, &sd_div
, m
, n
);
293 v
&= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK
294 | OMAP3630_PERIPH_DPLL_SD_DIV_MASK
);
295 v
|= dco
<< __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK
);
296 v
|= sd_div
<< __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK
);
299 __raw_writel(v
, dd
->mult_div1_reg
);
301 /* We let the clock framework set the other output dividers later */
303 /* REVISIT: Set ramp-up delay? */
305 _omap3_noncore_dpll_lock(clk
);
310 /* Public functions */
313 * omap3_dpll_recalc - recalculate DPLL rate
314 * @clk: DPLL struct clk
316 * Recalculate and propagate the DPLL rate.
318 unsigned long omap3_dpll_recalc(struct clk
*clk
)
320 return omap2_get_dpll_rate(clk
);
323 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
326 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
327 * @clk: pointer to a DPLL struct clk
329 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
330 * The choice of modes depends on the DPLL's programmed rate: if it is
331 * the same as the DPLL's parent clock, it will enter bypass;
332 * otherwise, it will enter lock. This code will wait for the DPLL to
333 * indicate readiness before returning, unless the DPLL takes too long
334 * to enter the target state. Intended to be used as the struct clk's
335 * enable function. If DPLL3 was passed in, or the DPLL does not
336 * support low-power stop, or if the DPLL took too long to enter
337 * bypass or lock, return -EINVAL; otherwise, return 0.
339 int omap3_noncore_dpll_enable(struct clk
*clk
)
342 struct dpll_data
*dd
;
348 if (clk
->rate
== dd
->clk_bypass
->rate
) {
349 WARN_ON(clk
->parent
!= dd
->clk_bypass
);
350 r
= _omap3_noncore_dpll_bypass(clk
);
352 WARN_ON(clk
->parent
!= dd
->clk_ref
);
353 r
= _omap3_noncore_dpll_lock(clk
);
356 clk
->rate
= omap2_get_dpll_rate(clk
);
362 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
363 * @clk: pointer to a DPLL struct clk
365 * Instructs a non-CORE DPLL to enter low-power stop. This function is
366 * intended for use in struct clkops. No return value.
368 void omap3_noncore_dpll_disable(struct clk
*clk
)
370 _omap3_noncore_dpll_stop(clk
);
374 /* Non-CORE DPLL rate set code */
377 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
378 * @clk: struct clk * of DPLL to set
379 * @rate: rounded target rate
381 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
382 * low-power bypass, and the target rate is the bypass source clock
383 * rate, then configure the DPLL for bypass. Otherwise, round the
384 * target rate if it hasn't been done already, then program and lock
385 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
387 int omap3_noncore_dpll_set_rate(struct clk
*clk
, unsigned long rate
)
389 struct clk
*new_parent
= NULL
;
391 struct dpll_data
*dd
;
401 if (rate
== omap2_get_dpll_rate(clk
))
405 * Ensure both the bypass and ref clocks are enabled prior to
406 * doing anything; we need the bypass clock running to reprogram
409 omap2_clk_enable(dd
->clk_bypass
);
410 omap2_clk_enable(dd
->clk_ref
);
412 if (dd
->clk_bypass
->rate
== rate
&&
413 (clk
->dpll_data
->modes
& (1 << DPLL_LOW_POWER_BYPASS
))) {
414 pr_debug("clock: %s: set rate: entering bypass.\n", clk
->name
);
416 ret
= _omap3_noncore_dpll_bypass(clk
);
418 new_parent
= dd
->clk_bypass
;
420 if (dd
->last_rounded_rate
!= rate
)
421 omap2_dpll_round_rate(clk
, rate
);
423 if (dd
->last_rounded_rate
== 0)
426 /* No freqsel on OMAP4 and OMAP3630 */
427 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
428 freqsel
= _omap3_dpll_compute_freqsel(clk
,
434 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
437 ret
= omap3_noncore_dpll_program(clk
, dd
->last_rounded_m
,
438 dd
->last_rounded_n
, freqsel
);
440 new_parent
= dd
->clk_ref
;
444 * Switch the parent clock in the hierarchy, and make sure
445 * that the new parent's usecount is correct. Note: we
446 * enable the new parent before disabling the old to avoid
447 * any unnecessary hardware disable->enable transitions.
450 omap2_clk_enable(new_parent
);
451 omap2_clk_disable(clk
->parent
);
453 clk_reparent(clk
, new_parent
);
456 omap2_clk_disable(dd
->clk_ref
);
457 omap2_clk_disable(dd
->clk_bypass
);
462 /* DPLL autoidle read/set code */
465 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
466 * @clk: struct clk * of the DPLL to read
468 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
469 * -EINVAL if passed a null pointer or if the struct clk does not
470 * appear to refer to a DPLL.
472 u32
omap3_dpll_autoidle_read(struct clk
*clk
)
474 const struct dpll_data
*dd
;
477 if (!clk
|| !clk
->dpll_data
)
482 v
= __raw_readl(dd
->autoidle_reg
);
483 v
&= dd
->autoidle_mask
;
484 v
>>= __ffs(dd
->autoidle_mask
);
490 * omap3_dpll_allow_idle - enable DPLL autoidle bits
491 * @clk: struct clk * of the DPLL to operate on
493 * Enable DPLL automatic idle control. This automatic idle mode
494 * switching takes effect only when the DPLL is locked, at least on
495 * OMAP3430. The DPLL will enter low-power stop when its downstream
496 * clocks are gated. No return value.
498 void omap3_dpll_allow_idle(struct clk
*clk
)
500 const struct dpll_data
*dd
;
503 if (!clk
|| !clk
->dpll_data
)
509 * REVISIT: CORE DPLL can optionally enter low-power bypass
510 * by writing 0x5 instead of 0x1. Add some mechanism to
511 * optionally enter this mode.
513 v
= __raw_readl(dd
->autoidle_reg
);
514 v
&= ~dd
->autoidle_mask
;
515 v
|= DPLL_AUTOIDLE_LOW_POWER_STOP
<< __ffs(dd
->autoidle_mask
);
516 __raw_writel(v
, dd
->autoidle_reg
);
520 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
521 * @clk: struct clk * of the DPLL to operate on
523 * Disable DPLL automatic idle control. No return value.
525 void omap3_dpll_deny_idle(struct clk
*clk
)
527 const struct dpll_data
*dd
;
530 if (!clk
|| !clk
->dpll_data
)
535 v
= __raw_readl(dd
->autoidle_reg
);
536 v
&= ~dd
->autoidle_mask
;
537 v
|= DPLL_AUTOIDLE_DISABLE
<< __ffs(dd
->autoidle_mask
);
538 __raw_writel(v
, dd
->autoidle_reg
);
542 /* Clock control for DPLL outputs */
545 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
546 * @clk: DPLL output struct clk
548 * Using parent clock DPLL data, look up DPLL state. If locked, set our
549 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
551 unsigned long omap3_clkoutx2_recalc(struct clk
*clk
)
553 const struct dpll_data
*dd
;
558 /* Walk up the parents of clk, looking for a DPLL */
560 while (pclk
&& !pclk
->dpll_data
)
563 /* clk does not have a DPLL as a parent? */
566 dd
= pclk
->dpll_data
;
568 WARN_ON(!dd
->enable_mask
);
570 v
= __raw_readl(dd
->control_reg
) & dd
->enable_mask
;
571 v
>>= __ffs(dd
->enable_mask
);
572 if ((v
!= OMAP3XXX_EN_DPLL_LOCKED
) || (dd
->flags
& DPLL_J_TYPE
))
573 rate
= clk
->parent
->rate
;
575 rate
= clk
->parent
->rate
* 2;