[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / arm / mach-omap2 / control.c
| blob | a8d20eef2306e8ddb558f96b2cc0ceeb6a542b25 |
1 /*
2 * OMAP2/3 System Control Module register access
3 *
4 * Copyright (C) 2007 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #undef DEBUG
15 #include <linux/kernel.h>
16 #include <linux/io.h>
18 #include <plat/common.h>
19 #include <plat/control.h>
20 #include <plat/sdrc.h>
29 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
31 u32 boot_config_ptr;
32 u32 public_restore_ptr;
33 u32 secure_ram_restore_ptr;
34 u32 sdrc_module_semaphore;
35 u32 prcm_block_offset;
36 u32 sdrc_block_offset;
37 };
40 u32 prm_clksrc_ctrl;
41 u32 prm_clksel;
42 u32 cm_clksel_core;
43 u32 cm_clksel_wkup;
44 u32 cm_clken_pll;
45 u32 cm_autoidle_pll;
46 u32 cm_clksel1_pll;
47 u32 cm_clksel2_pll;
48 u32 cm_clksel3_pll;
49 u32 cm_clken_pll_mpu;
50 u32 cm_autoidle_pll_mpu;
51 u32 cm_clksel1_pll_mpu;
52 u32 cm_clksel2_pll_mpu;
53 u32 prcm_block_size;
54 };
57 u16 sysconfig;
58 u16 cs_cfg;
59 u16 sharing;
60 u16 err_type;
61 u32 dll_a_ctrl;
62 u32 dll_b_ctrl;
63 u32 power;
64 u32 cs_0;
65 u32 mcfg_0;
66 u16 mr_0;
67 u16 emr_1_0;
68 u16 emr_2_0;
69 u16 emr_3_0;
70 u32 actim_ctrla_0;
71 u32 actim_ctrlb_0;
72 u32 rfr_ctrl_0;
73 u32 cs_1;
74 u32 mcfg_1;
75 u16 mr_1;
76 u16 emr_1_1;
77 u16 emr_2_1;
78 u16 emr_3_1;
79 u32 actim_ctrla_1;
80 u32 actim_ctrlb_1;
81 u32 rfr_ctrl_1;
82 u16 dcdl_1_ctrl;
83 u16 dcdl_2_ctrl;
84 u32 flags;
85 u32 block_size;
86 };
90 /*
91 * This is used to store ARM registers in SDRAM before attempting
92 * an MPU OFF. The save and restore happens from the SRAM sleep code.
93 * The address is stored in scratchpad, so that it can be used
94 * during the restore path.
95 */
99 u32 sysconfig;
100 u32 devconf0;
101 u32 mem_dftrw0;
102 u32 mem_dftrw1;
103 u32 msuspendmux_0;
104 u32 msuspendmux_1;
105 u32 msuspendmux_2;
106 u32 msuspendmux_3;
107 u32 msuspendmux_4;
108 u32 msuspendmux_5;
109 u32 sec_ctrl;
110 u32 devconf1;
111 u32 csirxfe;
112 u32 iva2_bootaddr;
113 u32 iva2_bootmod;
114 u32 debobs_0;
115 u32 debobs_1;
116 u32 debobs_2;
117 u32 debobs_3;
118 u32 debobs_4;
119 u32 debobs_5;
120 u32 debobs_6;
121 u32 debobs_7;
122 u32 debobs_8;
123 u32 prog_io0;
124 u32 prog_io1;
125 u32 dss_dpll_spreading;
126 u32 core_dpll_spreading;
127 u32 per_dpll_spreading;
128 u32 usbhost_dpll_spreading;
129 u32 pbias_lite;
130 u32 temp_sensor;
131 u32 sramldo4;
132 u32 sramldo5;
133 u32 csi;
134 };
139 #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
142 {
143 /* Static mapping, never released */
147 }
148 }
151 {
153 }
156 {
158 }
161 {
163 }
166 {
168 }
171 {
173 }
176 {
178 }
181 {
183 }
185 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
186 /*
187 * Clears the scratchpad contents in case of cold boot-
188 * called during bootup
189 */
191 {
197 OMAP3430_GLOBAL_COLD_RST_MASK) {
201 OMAP3430_GR_MOD,
202 OMAP3_PRM_RSTST_OFFSET);
203 }
204 }
206 /* Populate the scratchpad structure with restore structure */
208 {
210 u32 arm_context_addr;
215 /* Populate the Scratchpad contents */
221 else
226 else
233 /* Populate the PRCM block contents */
235 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
237 OMAP3_PRM_CLKSEL_OFFSET);
262 /* Populate the SDRC block contents */
273 /*
274 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
275 * be programed to issue automatic self refresh on timeout
276 * of AUTO_CNT = 1 prior to any transition to OFF mode.
277 */
282 SDRC_POWER_CLKCTRL_MASK)) |
284 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
285 else
319 /* Copy all the contents to the scratchpad location */
323 /* Scratchpad contents being 32 bits, a divide by 4 done here */
330 /*
331 * Copies the address of the location in SDRAM where ARM
332 * registers get saved during a MPU OFF transition.
333 */
337 }
340 {
393 }
396 {
400 OMAP343X_CONTROL_MEM_DFTRW0);
402 OMAP343X_CONTROL_MEM_DFTRW1);
404 OMAP2_CONTROL_MSUSPENDMUX_0);
406 OMAP2_CONTROL_MSUSPENDMUX_1);
408 OMAP2_CONTROL_MSUSPENDMUX_2);
410 OMAP2_CONTROL_MSUSPENDMUX_3);
412 OMAP2_CONTROL_MSUSPENDMUX_4);
414 OMAP2_CONTROL_MSUSPENDMUX_5);
419 OMAP343X_CONTROL_IVA2_BOOTADDR);
421 OMAP343X_CONTROL_IVA2_BOOTMOD);
434 OMAP343X_CONTROL_DSS_DPLL_SPREADING);
436 OMAP343X_CONTROL_CORE_DPLL_SPREADING);
438 OMAP343X_CONTROL_PER_DPLL_SPREADING);
440 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
442 OMAP343X_CONTROL_PBIAS_LITE);
444 OMAP343X_CONTROL_TEMP_SENSOR);
449 }