4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #include <linux/kernel.h>
20 #include <linux/clk.h>
21 #include <linux/list.h>
23 #include <plat/control.h>
24 #include <plat/clkdev_omap.h>
27 #include "clock3xxx.h"
28 #include "clock34xx.h"
29 #include "clock36xx.h"
30 #include "clock3517.h"
33 #include "cm-regbits-34xx.h"
35 #include "prm-regbits-34xx.h"
41 #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
43 /* Maximum DPLL multiplier, divider values for OMAP3 */
44 #define OMAP3_MAX_DPLL_MULT 2047
45 #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
46 #define OMAP3_MAX_DPLL_DIV 128
49 * DPLL1 supplies clock to the MPU.
50 * DPLL2 supplies clock to the IVA2.
51 * DPLL3 supplies CORE domain clocks.
52 * DPLL4 supplies peripheral clocks.
53 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
56 /* Forward declarations for DPLL bypass clocks */
57 static struct clk dpll1_fck
;
58 static struct clk dpll2_fck
;
62 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
63 static struct clk omap_32k_fck
= {
64 .name
= "omap_32k_fck",
69 static struct clk secure_32k_fck
= {
70 .name
= "secure_32k_fck",
75 /* Virtual source clocks for osc_sys_ck */
76 static struct clk virt_12m_ck
= {
77 .name
= "virt_12m_ck",
82 static struct clk virt_13m_ck
= {
83 .name
= "virt_13m_ck",
88 static struct clk virt_16_8m_ck
= {
89 .name
= "virt_16_8m_ck",
94 static struct clk virt_19_2m_ck
= {
95 .name
= "virt_19_2m_ck",
100 static struct clk virt_26m_ck
= {
101 .name
= "virt_26m_ck",
106 static struct clk virt_38_4m_ck
= {
107 .name
= "virt_38_4m_ck",
112 static const struct clksel_rate osc_sys_12m_rates
[] = {
113 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
117 static const struct clksel_rate osc_sys_13m_rates
[] = {
118 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
122 static const struct clksel_rate osc_sys_16_8m_rates
[] = {
123 { .div
= 1, .val
= 5, .flags
= RATE_IN_3430ES2PLUS
},
127 static const struct clksel_rate osc_sys_19_2m_rates
[] = {
128 { .div
= 1, .val
= 2, .flags
= RATE_IN_3XXX
},
132 static const struct clksel_rate osc_sys_26m_rates
[] = {
133 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
137 static const struct clksel_rate osc_sys_38_4m_rates
[] = {
138 { .div
= 1, .val
= 4, .flags
= RATE_IN_3XXX
},
142 static const struct clksel osc_sys_clksel
[] = {
143 { .parent
= &virt_12m_ck
, .rates
= osc_sys_12m_rates
},
144 { .parent
= &virt_13m_ck
, .rates
= osc_sys_13m_rates
},
145 { .parent
= &virt_16_8m_ck
, .rates
= osc_sys_16_8m_rates
},
146 { .parent
= &virt_19_2m_ck
, .rates
= osc_sys_19_2m_rates
},
147 { .parent
= &virt_26m_ck
, .rates
= osc_sys_26m_rates
},
148 { .parent
= &virt_38_4m_ck
, .rates
= osc_sys_38_4m_rates
},
152 /* Oscillator clock */
153 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
154 static struct clk osc_sys_ck
= {
155 .name
= "osc_sys_ck",
157 .init
= &omap2_init_clksel_parent
,
158 .clksel_reg
= OMAP3430_PRM_CLKSEL
,
159 .clksel_mask
= OMAP3430_SYS_CLKIN_SEL_MASK
,
160 .clksel
= osc_sys_clksel
,
161 /* REVISIT: deal with autoextclkmode? */
162 .recalc
= &omap2_clksel_recalc
,
165 static const struct clksel_rate div2_rates
[] = {
166 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
167 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
171 static const struct clksel sys_clksel
[] = {
172 { .parent
= &osc_sys_ck
, .rates
= div2_rates
},
176 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
177 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
178 static struct clk sys_ck
= {
181 .parent
= &osc_sys_ck
,
182 .init
= &omap2_init_clksel_parent
,
183 .clksel_reg
= OMAP3430_PRM_CLKSRC_CTRL
,
184 .clksel_mask
= OMAP_SYSCLKDIV_MASK
,
185 .clksel
= sys_clksel
,
186 .recalc
= &omap2_clksel_recalc
,
189 static struct clk sys_altclk
= {
190 .name
= "sys_altclk",
194 /* Optional external clock input for some McBSPs */
195 static struct clk mcbsp_clks
= {
196 .name
= "mcbsp_clks",
200 /* PRM EXTERNAL CLOCK OUTPUT */
202 static struct clk sys_clkout1
= {
203 .name
= "sys_clkout1",
204 .ops
= &clkops_omap2_dflt
,
205 .parent
= &osc_sys_ck
,
206 .enable_reg
= OMAP3430_PRM_CLKOUT_CTRL
,
207 .enable_bit
= OMAP3430_CLKOUT_EN_SHIFT
,
208 .recalc
= &followparent_recalc
,
215 static const struct clksel_rate div16_dpll_rates
[] = {
216 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
217 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
218 { .div
= 3, .val
= 3, .flags
= RATE_IN_3XXX
},
219 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
220 { .div
= 5, .val
= 5, .flags
= RATE_IN_3XXX
},
221 { .div
= 6, .val
= 6, .flags
= RATE_IN_3XXX
},
222 { .div
= 7, .val
= 7, .flags
= RATE_IN_3XXX
},
223 { .div
= 8, .val
= 8, .flags
= RATE_IN_3XXX
},
224 { .div
= 9, .val
= 9, .flags
= RATE_IN_3XXX
},
225 { .div
= 10, .val
= 10, .flags
= RATE_IN_3XXX
},
226 { .div
= 11, .val
= 11, .flags
= RATE_IN_3XXX
},
227 { .div
= 12, .val
= 12, .flags
= RATE_IN_3XXX
},
228 { .div
= 13, .val
= 13, .flags
= RATE_IN_3XXX
},
229 { .div
= 14, .val
= 14, .flags
= RATE_IN_3XXX
},
230 { .div
= 15, .val
= 15, .flags
= RATE_IN_3XXX
},
231 { .div
= 16, .val
= 16, .flags
= RATE_IN_3XXX
},
235 static const struct clksel_rate dpll4_rates
[] = {
236 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
237 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
238 { .div
= 3, .val
= 3, .flags
= RATE_IN_3XXX
},
239 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
240 { .div
= 5, .val
= 5, .flags
= RATE_IN_3XXX
},
241 { .div
= 6, .val
= 6, .flags
= RATE_IN_3XXX
},
242 { .div
= 7, .val
= 7, .flags
= RATE_IN_3XXX
},
243 { .div
= 8, .val
= 8, .flags
= RATE_IN_3XXX
},
244 { .div
= 9, .val
= 9, .flags
= RATE_IN_3XXX
},
245 { .div
= 10, .val
= 10, .flags
= RATE_IN_3XXX
},
246 { .div
= 11, .val
= 11, .flags
= RATE_IN_3XXX
},
247 { .div
= 12, .val
= 12, .flags
= RATE_IN_3XXX
},
248 { .div
= 13, .val
= 13, .flags
= RATE_IN_3XXX
},
249 { .div
= 14, .val
= 14, .flags
= RATE_IN_3XXX
},
250 { .div
= 15, .val
= 15, .flags
= RATE_IN_3XXX
},
251 { .div
= 16, .val
= 16, .flags
= RATE_IN_3XXX
},
252 { .div
= 17, .val
= 17, .flags
= RATE_IN_36XX
},
253 { .div
= 18, .val
= 18, .flags
= RATE_IN_36XX
},
254 { .div
= 19, .val
= 19, .flags
= RATE_IN_36XX
},
255 { .div
= 20, .val
= 20, .flags
= RATE_IN_36XX
},
256 { .div
= 21, .val
= 21, .flags
= RATE_IN_36XX
},
257 { .div
= 22, .val
= 22, .flags
= RATE_IN_36XX
},
258 { .div
= 23, .val
= 23, .flags
= RATE_IN_36XX
},
259 { .div
= 24, .val
= 24, .flags
= RATE_IN_36XX
},
260 { .div
= 25, .val
= 25, .flags
= RATE_IN_36XX
},
261 { .div
= 26, .val
= 26, .flags
= RATE_IN_36XX
},
262 { .div
= 27, .val
= 27, .flags
= RATE_IN_36XX
},
263 { .div
= 28, .val
= 28, .flags
= RATE_IN_36XX
},
264 { .div
= 29, .val
= 29, .flags
= RATE_IN_36XX
},
265 { .div
= 30, .val
= 30, .flags
= RATE_IN_36XX
},
266 { .div
= 31, .val
= 31, .flags
= RATE_IN_36XX
},
267 { .div
= 32, .val
= 32, .flags
= RATE_IN_36XX
},
272 /* MPU clock source */
274 static struct dpll_data dpll1_dd
= {
275 .mult_div1_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
276 .mult_mask
= OMAP3430_MPU_DPLL_MULT_MASK
,
277 .div1_mask
= OMAP3430_MPU_DPLL_DIV_MASK
,
278 .clk_bypass
= &dpll1_fck
,
280 .freqsel_mask
= OMAP3430_MPU_DPLL_FREQSEL_MASK
,
281 .control_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKEN_PLL
),
282 .enable_mask
= OMAP3430_EN_MPU_DPLL_MASK
,
283 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
284 .auto_recal_bit
= OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT
,
285 .recal_en_bit
= OMAP3430_MPU_DPLL_RECAL_EN_SHIFT
,
286 .recal_st_bit
= OMAP3430_MPU_DPLL_ST_SHIFT
,
287 .autoidle_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_AUTOIDLE_PLL
),
288 .autoidle_mask
= OMAP3430_AUTO_MPU_DPLL_MASK
,
289 .idlest_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_IDLEST_PLL
),
290 .idlest_mask
= OMAP3430_ST_MPU_CLK_MASK
,
291 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
293 .max_divider
= OMAP3_MAX_DPLL_DIV
,
294 .rate_tolerance
= DEFAULT_DPLL_RATE_TOLERANCE
297 static struct clk dpll1_ck
= {
301 .dpll_data
= &dpll1_dd
,
302 .round_rate
= &omap2_dpll_round_rate
,
303 .set_rate
= &omap3_noncore_dpll_set_rate
,
304 .clkdm_name
= "dpll1_clkdm",
305 .recalc
= &omap3_dpll_recalc
,
309 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
310 * DPLL isn't bypassed.
312 static struct clk dpll1_x2_ck
= {
313 .name
= "dpll1_x2_ck",
316 .clkdm_name
= "dpll1_clkdm",
317 .recalc
= &omap3_clkoutx2_recalc
,
320 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
321 static const struct clksel div16_dpll1_x2m2_clksel
[] = {
322 { .parent
= &dpll1_x2_ck
, .rates
= div16_dpll_rates
},
327 * Does not exist in the TRM - needed to separate the M2 divider from
328 * bypass selection in mpu_ck
330 static struct clk dpll1_x2m2_ck
= {
331 .name
= "dpll1_x2m2_ck",
333 .parent
= &dpll1_x2_ck
,
334 .init
= &omap2_init_clksel_parent
,
335 .clksel_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL2_PLL
),
336 .clksel_mask
= OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK
,
337 .clksel
= div16_dpll1_x2m2_clksel
,
338 .clkdm_name
= "dpll1_clkdm",
339 .recalc
= &omap2_clksel_recalc
,
343 /* IVA2 clock source */
346 static struct dpll_data dpll2_dd
= {
347 .mult_div1_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
348 .mult_mask
= OMAP3430_IVA2_DPLL_MULT_MASK
,
349 .div1_mask
= OMAP3430_IVA2_DPLL_DIV_MASK
,
350 .clk_bypass
= &dpll2_fck
,
352 .freqsel_mask
= OMAP3430_IVA2_DPLL_FREQSEL_MASK
,
353 .control_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKEN_PLL
),
354 .enable_mask
= OMAP3430_EN_IVA2_DPLL_MASK
,
355 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
) |
356 (1 << DPLL_LOW_POWER_BYPASS
),
357 .auto_recal_bit
= OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT
,
358 .recal_en_bit
= OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT
,
359 .recal_st_bit
= OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT
,
360 .autoidle_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_AUTOIDLE_PLL
),
361 .autoidle_mask
= OMAP3430_AUTO_IVA2_DPLL_MASK
,
362 .idlest_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_IDLEST_PLL
),
363 .idlest_mask
= OMAP3430_ST_IVA2_CLK_MASK
,
364 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
366 .max_divider
= OMAP3_MAX_DPLL_DIV
,
367 .rate_tolerance
= DEFAULT_DPLL_RATE_TOLERANCE
370 static struct clk dpll2_ck
= {
372 .ops
= &clkops_omap3_noncore_dpll_ops
,
374 .dpll_data
= &dpll2_dd
,
375 .round_rate
= &omap2_dpll_round_rate
,
376 .set_rate
= &omap3_noncore_dpll_set_rate
,
377 .clkdm_name
= "dpll2_clkdm",
378 .recalc
= &omap3_dpll_recalc
,
381 static const struct clksel div16_dpll2_m2x2_clksel
[] = {
382 { .parent
= &dpll2_ck
, .rates
= div16_dpll_rates
},
387 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
388 * or CLKOUTX2. CLKOUT seems most plausible.
390 static struct clk dpll2_m2_ck
= {
391 .name
= "dpll2_m2_ck",
394 .init
= &omap2_init_clksel_parent
,
395 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
,
396 OMAP3430_CM_CLKSEL2_PLL
),
397 .clksel_mask
= OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK
,
398 .clksel
= div16_dpll2_m2x2_clksel
,
399 .clkdm_name
= "dpll2_clkdm",
400 .recalc
= &omap2_clksel_recalc
,
405 * Source clock for all interfaces and for some device fclks
406 * REVISIT: Also supports fast relock bypass - not included below
408 static struct dpll_data dpll3_dd
= {
409 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
410 .mult_mask
= OMAP3430_CORE_DPLL_MULT_MASK
,
411 .div1_mask
= OMAP3430_CORE_DPLL_DIV_MASK
,
412 .clk_bypass
= &sys_ck
,
414 .freqsel_mask
= OMAP3430_CORE_DPLL_FREQSEL_MASK
,
415 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
416 .enable_mask
= OMAP3430_EN_CORE_DPLL_MASK
,
417 .auto_recal_bit
= OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT
,
418 .recal_en_bit
= OMAP3430_CORE_DPLL_RECAL_EN_SHIFT
,
419 .recal_st_bit
= OMAP3430_CORE_DPLL_ST_SHIFT
,
420 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
421 .autoidle_mask
= OMAP3430_AUTO_CORE_DPLL_MASK
,
422 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
423 .idlest_mask
= OMAP3430_ST_CORE_CLK_MASK
,
424 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
426 .max_divider
= OMAP3_MAX_DPLL_DIV
,
427 .rate_tolerance
= DEFAULT_DPLL_RATE_TOLERANCE
430 static struct clk dpll3_ck
= {
434 .dpll_data
= &dpll3_dd
,
435 .round_rate
= &omap2_dpll_round_rate
,
436 .clkdm_name
= "dpll3_clkdm",
437 .recalc
= &omap3_dpll_recalc
,
441 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
442 * DPLL isn't bypassed
444 static struct clk dpll3_x2_ck
= {
445 .name
= "dpll3_x2_ck",
448 .clkdm_name
= "dpll3_clkdm",
449 .recalc
= &omap3_clkoutx2_recalc
,
452 static const struct clksel_rate div31_dpll3_rates
[] = {
453 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
454 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
455 { .div
= 3, .val
= 3, .flags
= RATE_IN_3430ES2PLUS
},
456 { .div
= 4, .val
= 4, .flags
= RATE_IN_3430ES2PLUS
},
457 { .div
= 5, .val
= 5, .flags
= RATE_IN_3430ES2PLUS
},
458 { .div
= 6, .val
= 6, .flags
= RATE_IN_3430ES2PLUS
},
459 { .div
= 7, .val
= 7, .flags
= RATE_IN_3430ES2PLUS
},
460 { .div
= 8, .val
= 8, .flags
= RATE_IN_3430ES2PLUS
},
461 { .div
= 9, .val
= 9, .flags
= RATE_IN_3430ES2PLUS
},
462 { .div
= 10, .val
= 10, .flags
= RATE_IN_3430ES2PLUS
},
463 { .div
= 11, .val
= 11, .flags
= RATE_IN_3430ES2PLUS
},
464 { .div
= 12, .val
= 12, .flags
= RATE_IN_3430ES2PLUS
},
465 { .div
= 13, .val
= 13, .flags
= RATE_IN_3430ES2PLUS
},
466 { .div
= 14, .val
= 14, .flags
= RATE_IN_3430ES2PLUS
},
467 { .div
= 15, .val
= 15, .flags
= RATE_IN_3430ES2PLUS
},
468 { .div
= 16, .val
= 16, .flags
= RATE_IN_3430ES2PLUS
},
469 { .div
= 17, .val
= 17, .flags
= RATE_IN_3430ES2PLUS
},
470 { .div
= 18, .val
= 18, .flags
= RATE_IN_3430ES2PLUS
},
471 { .div
= 19, .val
= 19, .flags
= RATE_IN_3430ES2PLUS
},
472 { .div
= 20, .val
= 20, .flags
= RATE_IN_3430ES2PLUS
},
473 { .div
= 21, .val
= 21, .flags
= RATE_IN_3430ES2PLUS
},
474 { .div
= 22, .val
= 22, .flags
= RATE_IN_3430ES2PLUS
},
475 { .div
= 23, .val
= 23, .flags
= RATE_IN_3430ES2PLUS
},
476 { .div
= 24, .val
= 24, .flags
= RATE_IN_3430ES2PLUS
},
477 { .div
= 25, .val
= 25, .flags
= RATE_IN_3430ES2PLUS
},
478 { .div
= 26, .val
= 26, .flags
= RATE_IN_3430ES2PLUS
},
479 { .div
= 27, .val
= 27, .flags
= RATE_IN_3430ES2PLUS
},
480 { .div
= 28, .val
= 28, .flags
= RATE_IN_3430ES2PLUS
},
481 { .div
= 29, .val
= 29, .flags
= RATE_IN_3430ES2PLUS
},
482 { .div
= 30, .val
= 30, .flags
= RATE_IN_3430ES2PLUS
},
483 { .div
= 31, .val
= 31, .flags
= RATE_IN_3430ES2PLUS
},
487 static const struct clksel div31_dpll3m2_clksel
[] = {
488 { .parent
= &dpll3_ck
, .rates
= div31_dpll3_rates
},
492 /* DPLL3 output M2 - primary control point for CORE speed */
493 static struct clk dpll3_m2_ck
= {
494 .name
= "dpll3_m2_ck",
497 .init
= &omap2_init_clksel_parent
,
498 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
499 .clksel_mask
= OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK
,
500 .clksel
= div31_dpll3m2_clksel
,
501 .clkdm_name
= "dpll3_clkdm",
502 .round_rate
= &omap2_clksel_round_rate
,
503 .set_rate
= &omap3_core_dpll_m2_set_rate
,
504 .recalc
= &omap2_clksel_recalc
,
507 static struct clk core_ck
= {
510 .parent
= &dpll3_m2_ck
,
511 .recalc
= &followparent_recalc
,
514 static struct clk dpll3_m2x2_ck
= {
515 .name
= "dpll3_m2x2_ck",
517 .parent
= &dpll3_m2_ck
,
518 .clkdm_name
= "dpll3_clkdm",
519 .recalc
= &omap3_clkoutx2_recalc
,
522 /* The PWRDN bit is apparently only available on 3430ES2 and above */
523 static const struct clksel div16_dpll3_clksel
[] = {
524 { .parent
= &dpll3_ck
, .rates
= div16_dpll_rates
},
528 /* This virtual clock is the source for dpll3_m3x2_ck */
529 static struct clk dpll3_m3_ck
= {
530 .name
= "dpll3_m3_ck",
533 .init
= &omap2_init_clksel_parent
,
534 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
535 .clksel_mask
= OMAP3430_DIV_DPLL3_MASK
,
536 .clksel
= div16_dpll3_clksel
,
537 .clkdm_name
= "dpll3_clkdm",
538 .recalc
= &omap2_clksel_recalc
,
541 /* The PWRDN bit is apparently only available on 3430ES2 and above */
542 static struct clk dpll3_m3x2_ck
= {
543 .name
= "dpll3_m3x2_ck",
544 .ops
= &clkops_omap2_dflt_wait
,
545 .parent
= &dpll3_m3_ck
,
546 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
547 .enable_bit
= OMAP3430_PWRDN_EMU_CORE_SHIFT
,
548 .flags
= INVERT_ENABLE
,
549 .clkdm_name
= "dpll3_clkdm",
550 .recalc
= &omap3_clkoutx2_recalc
,
553 static struct clk emu_core_alwon_ck
= {
554 .name
= "emu_core_alwon_ck",
556 .parent
= &dpll3_m3x2_ck
,
557 .clkdm_name
= "dpll3_clkdm",
558 .recalc
= &followparent_recalc
,
562 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
564 static struct dpll_data dpll4_dd
;
566 static struct dpll_data dpll4_dd_34xx __initdata
= {
567 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL2
),
568 .mult_mask
= OMAP3430_PERIPH_DPLL_MULT_MASK
,
569 .div1_mask
= OMAP3430_PERIPH_DPLL_DIV_MASK
,
570 .clk_bypass
= &sys_ck
,
572 .freqsel_mask
= OMAP3430_PERIPH_DPLL_FREQSEL_MASK
,
573 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
574 .enable_mask
= OMAP3430_EN_PERIPH_DPLL_MASK
,
575 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
576 .auto_recal_bit
= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT
,
577 .recal_en_bit
= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT
,
578 .recal_st_bit
= OMAP3430_PERIPH_DPLL_ST_SHIFT
,
579 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
580 .autoidle_mask
= OMAP3430_AUTO_PERIPH_DPLL_MASK
,
581 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
582 .idlest_mask
= OMAP3430_ST_PERIPH_CLK_MASK
,
583 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
585 .max_divider
= OMAP3_MAX_DPLL_DIV
,
586 .rate_tolerance
= DEFAULT_DPLL_RATE_TOLERANCE
589 static struct dpll_data dpll4_dd_3630 __initdata
= {
590 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL2
),
591 .mult_mask
= OMAP3630_PERIPH_DPLL_MULT_MASK
,
592 .div1_mask
= OMAP3430_PERIPH_DPLL_DIV_MASK
,
593 .clk_bypass
= &sys_ck
,
595 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
596 .enable_mask
= OMAP3430_EN_PERIPH_DPLL_MASK
,
597 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
598 .auto_recal_bit
= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT
,
599 .recal_en_bit
= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT
,
600 .recal_st_bit
= OMAP3430_PERIPH_DPLL_ST_SHIFT
,
601 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
602 .autoidle_mask
= OMAP3430_AUTO_PERIPH_DPLL_MASK
,
603 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
604 .idlest_mask
= OMAP3430_ST_PERIPH_CLK_MASK
,
605 .max_multiplier
= OMAP3630_MAX_JTYPE_DPLL_MULT
,
607 .max_divider
= OMAP3_MAX_DPLL_DIV
,
608 .rate_tolerance
= DEFAULT_DPLL_RATE_TOLERANCE
,
612 static struct clk dpll4_ck
= {
614 .ops
= &clkops_omap3_noncore_dpll_ops
,
616 .dpll_data
= &dpll4_dd
,
617 .round_rate
= &omap2_dpll_round_rate
,
618 .set_rate
= &omap3_dpll4_set_rate
,
619 .clkdm_name
= "dpll4_clkdm",
620 .recalc
= &omap3_dpll_recalc
,
623 static struct clk dpll4_x2_ck
= {
624 .name
= "dpll4_x2_ck",
627 .clkdm_name
= "dpll4_clkdm",
628 .recalc
= &omap3_clkoutx2_recalc
,
631 static const struct clksel dpll4_clksel
[] = {
632 { .parent
= &dpll4_ck
, .rates
= dpll4_rates
},
636 /* This virtual clock is the source for dpll4_m2x2_ck */
637 static struct clk dpll4_m2_ck
= {
638 .name
= "dpll4_m2_ck",
641 .init
= &omap2_init_clksel_parent
,
642 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430_CM_CLKSEL3
),
643 .clksel_mask
= OMAP3630_DIV_96M_MASK
,
644 .clksel
= dpll4_clksel
,
645 .clkdm_name
= "dpll4_clkdm",
646 .recalc
= &omap2_clksel_recalc
,
649 /* The PWRDN bit is apparently only available on 3430ES2 and above */
650 static struct clk dpll4_m2x2_ck
= {
651 .name
= "dpll4_m2x2_ck",
652 .ops
= &clkops_omap2_dflt_wait
,
653 .parent
= &dpll4_m2_ck
,
654 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
655 .enable_bit
= OMAP3430_PWRDN_96M_SHIFT
,
656 .flags
= INVERT_ENABLE
,
657 .clkdm_name
= "dpll4_clkdm",
658 .recalc
= &omap3_clkoutx2_recalc
,
662 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
663 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
664 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
668 /* Adding 192MHz Clock node needed by SGX */
669 static struct clk omap_192m_alwon_fck
= {
670 .name
= "omap_192m_alwon_fck",
672 .parent
= &dpll4_m2x2_ck
,
673 .recalc
= &followparent_recalc
,
676 static const struct clksel_rate omap_96m_alwon_fck_rates
[] = {
677 { .div
= 1, .val
= 1, .flags
= RATE_IN_36XX
},
678 { .div
= 2, .val
= 2, .flags
= RATE_IN_36XX
},
682 static const struct clksel omap_96m_alwon_fck_clksel
[] = {
683 { .parent
= &omap_192m_alwon_fck
, .rates
= omap_96m_alwon_fck_rates
},
687 static const struct clksel_rate omap_96m_dpll_rates
[] = {
688 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
692 static const struct clksel_rate omap_96m_sys_rates
[] = {
693 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
697 static struct clk omap_96m_alwon_fck
= {
698 .name
= "omap_96m_alwon_fck",
700 .parent
= &dpll4_m2x2_ck
,
701 .recalc
= &followparent_recalc
,
704 static struct clk omap_96m_alwon_fck_3630
= {
705 .name
= "omap_96m_alwon_fck",
706 .parent
= &omap_192m_alwon_fck
,
707 .init
= &omap2_init_clksel_parent
,
709 .recalc
= &omap2_clksel_recalc
,
710 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
711 .clksel_mask
= OMAP3630_CLKSEL_96M_MASK
,
712 .clksel
= omap_96m_alwon_fck_clksel
715 static struct clk cm_96m_fck
= {
716 .name
= "cm_96m_fck",
718 .parent
= &omap_96m_alwon_fck
,
719 .recalc
= &followparent_recalc
,
722 static const struct clksel omap_96m_fck_clksel
[] = {
723 { .parent
= &cm_96m_fck
, .rates
= omap_96m_dpll_rates
},
724 { .parent
= &sys_ck
, .rates
= omap_96m_sys_rates
},
728 static struct clk omap_96m_fck
= {
729 .name
= "omap_96m_fck",
732 .init
= &omap2_init_clksel_parent
,
733 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
734 .clksel_mask
= OMAP3430_SOURCE_96M_MASK
,
735 .clksel
= omap_96m_fck_clksel
,
736 .recalc
= &omap2_clksel_recalc
,
739 /* This virtual clock is the source for dpll4_m3x2_ck */
740 static struct clk dpll4_m3_ck
= {
741 .name
= "dpll4_m3_ck",
744 .init
= &omap2_init_clksel_parent
,
745 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_CLKSEL
),
746 .clksel_mask
= OMAP3430_CLKSEL_TV_MASK
,
747 .clksel
= dpll4_clksel
,
748 .clkdm_name
= "dpll4_clkdm",
749 .recalc
= &omap2_clksel_recalc
,
752 /* The PWRDN bit is apparently only available on 3430ES2 and above */
753 static struct clk dpll4_m3x2_ck
= {
754 .name
= "dpll4_m3x2_ck",
755 .ops
= &clkops_omap2_dflt_wait
,
756 .parent
= &dpll4_m3_ck
,
757 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
758 .enable_bit
= OMAP3430_PWRDN_TV_SHIFT
,
759 .flags
= INVERT_ENABLE
,
760 .clkdm_name
= "dpll4_clkdm",
761 .recalc
= &omap3_clkoutx2_recalc
,
764 static const struct clksel_rate omap_54m_d4m3x2_rates
[] = {
765 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
769 static const struct clksel_rate omap_54m_alt_rates
[] = {
770 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
774 static const struct clksel omap_54m_clksel
[] = {
775 { .parent
= &dpll4_m3x2_ck
, .rates
= omap_54m_d4m3x2_rates
},
776 { .parent
= &sys_altclk
, .rates
= omap_54m_alt_rates
},
780 static struct clk omap_54m_fck
= {
781 .name
= "omap_54m_fck",
783 .init
= &omap2_init_clksel_parent
,
784 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
785 .clksel_mask
= OMAP3430_SOURCE_54M_MASK
,
786 .clksel
= omap_54m_clksel
,
787 .recalc
= &omap2_clksel_recalc
,
790 static const struct clksel_rate omap_48m_cm96m_rates
[] = {
791 { .div
= 2, .val
= 0, .flags
= RATE_IN_3XXX
},
795 static const struct clksel_rate omap_48m_alt_rates
[] = {
796 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
800 static const struct clksel omap_48m_clksel
[] = {
801 { .parent
= &cm_96m_fck
, .rates
= omap_48m_cm96m_rates
},
802 { .parent
= &sys_altclk
, .rates
= omap_48m_alt_rates
},
806 static struct clk omap_48m_fck
= {
807 .name
= "omap_48m_fck",
809 .init
= &omap2_init_clksel_parent
,
810 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
811 .clksel_mask
= OMAP3430_SOURCE_48M_MASK
,
812 .clksel
= omap_48m_clksel
,
813 .recalc
= &omap2_clksel_recalc
,
816 static struct clk omap_12m_fck
= {
817 .name
= "omap_12m_fck",
819 .parent
= &omap_48m_fck
,
821 .recalc
= &omap_fixed_divisor_recalc
,
824 /* This virtual clock is the source for dpll4_m4x2_ck */
825 static struct clk dpll4_m4_ck
= {
826 .name
= "dpll4_m4_ck",
829 .init
= &omap2_init_clksel_parent
,
830 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_CLKSEL
),
831 .clksel_mask
= OMAP3430_CLKSEL_DSS1_MASK
,
832 .clksel
= dpll4_clksel
,
833 .clkdm_name
= "dpll4_clkdm",
834 .recalc
= &omap2_clksel_recalc
,
835 .set_rate
= &omap2_clksel_set_rate
,
836 .round_rate
= &omap2_clksel_round_rate
,
839 /* The PWRDN bit is apparently only available on 3430ES2 and above */
840 static struct clk dpll4_m4x2_ck
= {
841 .name
= "dpll4_m4x2_ck",
842 .ops
= &clkops_omap2_dflt_wait
,
843 .parent
= &dpll4_m4_ck
,
844 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
845 .enable_bit
= OMAP3430_PWRDN_DSS1_SHIFT
,
846 .flags
= INVERT_ENABLE
,
847 .clkdm_name
= "dpll4_clkdm",
848 .recalc
= &omap3_clkoutx2_recalc
,
851 /* This virtual clock is the source for dpll4_m5x2_ck */
852 static struct clk dpll4_m5_ck
= {
853 .name
= "dpll4_m5_ck",
856 .init
= &omap2_init_clksel_parent
,
857 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_CLKSEL
),
858 .clksel_mask
= OMAP3430_CLKSEL_CAM_MASK
,
859 .clksel
= dpll4_clksel
,
860 .clkdm_name
= "dpll4_clkdm",
861 .set_rate
= &omap2_clksel_set_rate
,
862 .round_rate
= &omap2_clksel_round_rate
,
863 .recalc
= &omap2_clksel_recalc
,
866 /* The PWRDN bit is apparently only available on 3430ES2 and above */
867 static struct clk dpll4_m5x2_ck
= {
868 .name
= "dpll4_m5x2_ck",
869 .ops
= &clkops_omap2_dflt_wait
,
870 .parent
= &dpll4_m5_ck
,
871 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
872 .enable_bit
= OMAP3430_PWRDN_CAM_SHIFT
,
873 .flags
= INVERT_ENABLE
,
874 .clkdm_name
= "dpll4_clkdm",
875 .recalc
= &omap3_clkoutx2_recalc
,
878 /* This virtual clock is the source for dpll4_m6x2_ck */
879 static struct clk dpll4_m6_ck
= {
880 .name
= "dpll4_m6_ck",
883 .init
= &omap2_init_clksel_parent
,
884 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
885 .clksel_mask
= OMAP3430_DIV_DPLL4_MASK
,
886 .clksel
= dpll4_clksel
,
887 .clkdm_name
= "dpll4_clkdm",
888 .recalc
= &omap2_clksel_recalc
,
891 /* The PWRDN bit is apparently only available on 3430ES2 and above */
892 static struct clk dpll4_m6x2_ck
= {
893 .name
= "dpll4_m6x2_ck",
894 .ops
= &clkops_omap2_dflt_wait
,
895 .parent
= &dpll4_m6_ck
,
896 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
897 .enable_bit
= OMAP3430_PWRDN_EMU_PERIPH_SHIFT
,
898 .flags
= INVERT_ENABLE
,
899 .clkdm_name
= "dpll4_clkdm",
900 .recalc
= &omap3_clkoutx2_recalc
,
903 static struct clk emu_per_alwon_ck
= {
904 .name
= "emu_per_alwon_ck",
906 .parent
= &dpll4_m6x2_ck
,
907 .clkdm_name
= "dpll4_clkdm",
908 .recalc
= &followparent_recalc
,
912 /* Supplies 120MHz clock, USIM source clock */
915 static struct dpll_data dpll5_dd
= {
916 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKSEL4
),
917 .mult_mask
= OMAP3430ES2_PERIPH2_DPLL_MULT_MASK
,
918 .div1_mask
= OMAP3430ES2_PERIPH2_DPLL_DIV_MASK
,
919 .clk_bypass
= &sys_ck
,
921 .freqsel_mask
= OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK
,
922 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKEN2
),
923 .enable_mask
= OMAP3430ES2_EN_PERIPH2_DPLL_MASK
,
924 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
925 .auto_recal_bit
= OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT
,
926 .recal_en_bit
= OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT
,
927 .recal_st_bit
= OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT
,
928 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_AUTOIDLE2_PLL
),
929 .autoidle_mask
= OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK
,
930 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST2
),
931 .idlest_mask
= OMAP3430ES2_ST_PERIPH2_CLK_MASK
,
932 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
934 .max_divider
= OMAP3_MAX_DPLL_DIV
,
935 .rate_tolerance
= DEFAULT_DPLL_RATE_TOLERANCE
938 static struct clk dpll5_ck
= {
940 .ops
= &clkops_omap3_noncore_dpll_ops
,
942 .dpll_data
= &dpll5_dd
,
943 .round_rate
= &omap2_dpll_round_rate
,
944 .set_rate
= &omap3_noncore_dpll_set_rate
,
945 .clkdm_name
= "dpll5_clkdm",
946 .recalc
= &omap3_dpll_recalc
,
949 static const struct clksel div16_dpll5_clksel
[] = {
950 { .parent
= &dpll5_ck
, .rates
= div16_dpll_rates
},
954 static struct clk dpll5_m2_ck
= {
955 .name
= "dpll5_m2_ck",
958 .init
= &omap2_init_clksel_parent
,
959 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKSEL5
),
960 .clksel_mask
= OMAP3430ES2_DIV_120M_MASK
,
961 .clksel
= div16_dpll5_clksel
,
962 .clkdm_name
= "dpll5_clkdm",
963 .recalc
= &omap2_clksel_recalc
,
966 /* CM EXTERNAL CLOCK OUTPUTS */
968 static const struct clksel_rate clkout2_src_core_rates
[] = {
969 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
973 static const struct clksel_rate clkout2_src_sys_rates
[] = {
974 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
978 static const struct clksel_rate clkout2_src_96m_rates
[] = {
979 { .div
= 1, .val
= 2, .flags
= RATE_IN_3XXX
},
983 static const struct clksel_rate clkout2_src_54m_rates
[] = {
984 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
988 static const struct clksel clkout2_src_clksel
[] = {
989 { .parent
= &core_ck
, .rates
= clkout2_src_core_rates
},
990 { .parent
= &sys_ck
, .rates
= clkout2_src_sys_rates
},
991 { .parent
= &cm_96m_fck
, .rates
= clkout2_src_96m_rates
},
992 { .parent
= &omap_54m_fck
, .rates
= clkout2_src_54m_rates
},
996 static struct clk clkout2_src_ck
= {
997 .name
= "clkout2_src_ck",
998 .ops
= &clkops_omap2_dflt
,
999 .init
= &omap2_init_clksel_parent
,
1000 .enable_reg
= OMAP3430_CM_CLKOUT_CTRL
,
1001 .enable_bit
= OMAP3430_CLKOUT2_EN_SHIFT
,
1002 .clksel_reg
= OMAP3430_CM_CLKOUT_CTRL
,
1003 .clksel_mask
= OMAP3430_CLKOUT2SOURCE_MASK
,
1004 .clksel
= clkout2_src_clksel
,
1005 .clkdm_name
= "core_clkdm",
1006 .recalc
= &omap2_clksel_recalc
,
1009 static const struct clksel_rate sys_clkout2_rates
[] = {
1010 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
1011 { .div
= 2, .val
= 1, .flags
= RATE_IN_3XXX
},
1012 { .div
= 4, .val
= 2, .flags
= RATE_IN_3XXX
},
1013 { .div
= 8, .val
= 3, .flags
= RATE_IN_3XXX
},
1014 { .div
= 16, .val
= 4, .flags
= RATE_IN_3XXX
},
1018 static const struct clksel sys_clkout2_clksel
[] = {
1019 { .parent
= &clkout2_src_ck
, .rates
= sys_clkout2_rates
},
1023 static struct clk sys_clkout2
= {
1024 .name
= "sys_clkout2",
1025 .ops
= &clkops_null
,
1026 .init
= &omap2_init_clksel_parent
,
1027 .clksel_reg
= OMAP3430_CM_CLKOUT_CTRL
,
1028 .clksel_mask
= OMAP3430_CLKOUT2_DIV_MASK
,
1029 .clksel
= sys_clkout2_clksel
,
1030 .recalc
= &omap2_clksel_recalc
,
1031 .round_rate
= &omap2_clksel_round_rate
,
1032 .set_rate
= &omap2_clksel_set_rate
1035 /* CM OUTPUT CLOCKS */
1037 static struct clk corex2_fck
= {
1038 .name
= "corex2_fck",
1039 .ops
= &clkops_null
,
1040 .parent
= &dpll3_m2x2_ck
,
1041 .recalc
= &followparent_recalc
,
1044 /* DPLL power domain clock controls */
1046 static const struct clksel_rate div4_rates
[] = {
1047 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
1048 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
1049 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
1053 static const struct clksel div4_core_clksel
[] = {
1054 { .parent
= &core_ck
, .rates
= div4_rates
},
1059 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1060 * may be inconsistent here?
1062 static struct clk dpll1_fck
= {
1063 .name
= "dpll1_fck",
1064 .ops
= &clkops_null
,
1066 .init
= &omap2_init_clksel_parent
,
1067 .clksel_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
1068 .clksel_mask
= OMAP3430_MPU_CLK_SRC_MASK
,
1069 .clksel
= div4_core_clksel
,
1070 .recalc
= &omap2_clksel_recalc
,
1073 static struct clk mpu_ck
= {
1075 .ops
= &clkops_null
,
1076 .parent
= &dpll1_x2m2_ck
,
1077 .clkdm_name
= "mpu_clkdm",
1078 .recalc
= &followparent_recalc
,
1081 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1082 static const struct clksel_rate arm_fck_rates
[] = {
1083 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
1084 { .div
= 2, .val
= 1, .flags
= RATE_IN_3XXX
},
1088 static const struct clksel arm_fck_clksel
[] = {
1089 { .parent
= &mpu_ck
, .rates
= arm_fck_rates
},
1093 static struct clk arm_fck
= {
1095 .ops
= &clkops_null
,
1097 .init
= &omap2_init_clksel_parent
,
1098 .clksel_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_IDLEST_PLL
),
1099 .clksel_mask
= OMAP3430_ST_MPU_CLK_MASK
,
1100 .clksel
= arm_fck_clksel
,
1101 .clkdm_name
= "mpu_clkdm",
1102 .recalc
= &omap2_clksel_recalc
,
1107 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1108 * although it is referenced - so this is a guess
1110 static struct clk emu_mpu_alwon_ck
= {
1111 .name
= "emu_mpu_alwon_ck",
1112 .ops
= &clkops_null
,
1114 .recalc
= &followparent_recalc
,
1117 static struct clk dpll2_fck
= {
1118 .name
= "dpll2_fck",
1119 .ops
= &clkops_null
,
1121 .init
= &omap2_init_clksel_parent
,
1122 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
1123 .clksel_mask
= OMAP3430_IVA2_CLK_SRC_MASK
,
1124 .clksel
= div4_core_clksel
,
1125 .recalc
= &omap2_clksel_recalc
,
1128 static struct clk iva2_ck
= {
1130 .ops
= &clkops_omap2_dflt_wait
,
1131 .parent
= &dpll2_m2_ck
,
1132 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, CM_FCLKEN
),
1133 .enable_bit
= OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT
,
1134 .clkdm_name
= "iva2_clkdm",
1135 .recalc
= &followparent_recalc
,
1138 /* Common interface clocks */
1140 static const struct clksel div2_core_clksel
[] = {
1141 { .parent
= &core_ck
, .rates
= div2_rates
},
1145 static struct clk l3_ick
= {
1147 .ops
= &clkops_null
,
1149 .init
= &omap2_init_clksel_parent
,
1150 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1151 .clksel_mask
= OMAP3430_CLKSEL_L3_MASK
,
1152 .clksel
= div2_core_clksel
,
1153 .clkdm_name
= "core_l3_clkdm",
1154 .recalc
= &omap2_clksel_recalc
,
1157 static const struct clksel div2_l3_clksel
[] = {
1158 { .parent
= &l3_ick
, .rates
= div2_rates
},
1162 static struct clk l4_ick
= {
1164 .ops
= &clkops_null
,
1166 .init
= &omap2_init_clksel_parent
,
1167 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1168 .clksel_mask
= OMAP3430_CLKSEL_L4_MASK
,
1169 .clksel
= div2_l3_clksel
,
1170 .clkdm_name
= "core_l4_clkdm",
1171 .recalc
= &omap2_clksel_recalc
,
1175 static const struct clksel div2_l4_clksel
[] = {
1176 { .parent
= &l4_ick
, .rates
= div2_rates
},
1180 static struct clk rm_ick
= {
1182 .ops
= &clkops_null
,
1184 .init
= &omap2_init_clksel_parent
,
1185 .clksel_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
1186 .clksel_mask
= OMAP3430_CLKSEL_RM_MASK
,
1187 .clksel
= div2_l4_clksel
,
1188 .recalc
= &omap2_clksel_recalc
,
1191 /* GFX power domain */
1193 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1195 static const struct clksel gfx_l3_clksel
[] = {
1196 { .parent
= &l3_ick
, .rates
= gfx_l3_rates
},
1200 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1201 static struct clk gfx_l3_ck
= {
1202 .name
= "gfx_l3_ck",
1203 .ops
= &clkops_omap2_dflt_wait
,
1205 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_ICLKEN
),
1206 .enable_bit
= OMAP_EN_GFX_SHIFT
,
1207 .recalc
= &followparent_recalc
,
1210 static struct clk gfx_l3_fck
= {
1211 .name
= "gfx_l3_fck",
1212 .ops
= &clkops_null
,
1213 .parent
= &gfx_l3_ck
,
1214 .init
= &omap2_init_clksel_parent
,
1215 .clksel_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_CLKSEL
),
1216 .clksel_mask
= OMAP_CLKSEL_GFX_MASK
,
1217 .clksel
= gfx_l3_clksel
,
1218 .clkdm_name
= "gfx_3430es1_clkdm",
1219 .recalc
= &omap2_clksel_recalc
,
1222 static struct clk gfx_l3_ick
= {
1223 .name
= "gfx_l3_ick",
1224 .ops
= &clkops_null
,
1225 .parent
= &gfx_l3_ck
,
1226 .clkdm_name
= "gfx_3430es1_clkdm",
1227 .recalc
= &followparent_recalc
,
1230 static struct clk gfx_cg1_ck
= {
1231 .name
= "gfx_cg1_ck",
1232 .ops
= &clkops_omap2_dflt_wait
,
1233 .parent
= &gfx_l3_fck
, /* REVISIT: correct? */
1234 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_FCLKEN
),
1235 .enable_bit
= OMAP3430ES1_EN_2D_SHIFT
,
1236 .clkdm_name
= "gfx_3430es1_clkdm",
1237 .recalc
= &followparent_recalc
,
1240 static struct clk gfx_cg2_ck
= {
1241 .name
= "gfx_cg2_ck",
1242 .ops
= &clkops_omap2_dflt_wait
,
1243 .parent
= &gfx_l3_fck
, /* REVISIT: correct? */
1244 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_FCLKEN
),
1245 .enable_bit
= OMAP3430ES1_EN_3D_SHIFT
,
1246 .clkdm_name
= "gfx_3430es1_clkdm",
1247 .recalc
= &followparent_recalc
,
1250 /* SGX power domain - 3430ES2 only */
1252 static const struct clksel_rate sgx_core_rates
[] = {
1253 { .div
= 2, .val
= 5, .flags
= RATE_IN_36XX
},
1254 { .div
= 3, .val
= 0, .flags
= RATE_IN_3XXX
},
1255 { .div
= 4, .val
= 1, .flags
= RATE_IN_3XXX
},
1256 { .div
= 6, .val
= 2, .flags
= RATE_IN_3XXX
},
1260 static const struct clksel_rate sgx_192m_rates
[] = {
1261 { .div
= 1, .val
= 4, .flags
= RATE_IN_36XX
},
1265 static const struct clksel_rate sgx_corex2_rates
[] = {
1266 { .div
= 3, .val
= 6, .flags
= RATE_IN_36XX
},
1267 { .div
= 5, .val
= 7, .flags
= RATE_IN_36XX
},
1271 static const struct clksel_rate sgx_96m_rates
[] = {
1272 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
1276 static const struct clksel sgx_clksel
[] = {
1277 { .parent
= &core_ck
, .rates
= sgx_core_rates
},
1278 { .parent
= &cm_96m_fck
, .rates
= sgx_96m_rates
},
1279 { .parent
= &omap_192m_alwon_fck
, .rates
= sgx_192m_rates
},
1280 { .parent
= &corex2_fck
, .rates
= sgx_corex2_rates
},
1284 static struct clk sgx_fck
= {
1286 .ops
= &clkops_omap2_dflt_wait
,
1287 .init
= &omap2_init_clksel_parent
,
1288 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_FCLKEN
),
1289 .enable_bit
= OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT
,
1290 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_CLKSEL
),
1291 .clksel_mask
= OMAP3430ES2_CLKSEL_SGX_MASK
,
1292 .clksel
= sgx_clksel
,
1293 .clkdm_name
= "sgx_clkdm",
1294 .recalc
= &omap2_clksel_recalc
,
1295 .set_rate
= &omap2_clksel_set_rate
,
1296 .round_rate
= &omap2_clksel_round_rate
1299 static struct clk sgx_ick
= {
1301 .ops
= &clkops_omap2_dflt_wait
,
1303 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_ICLKEN
),
1304 .enable_bit
= OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT
,
1305 .clkdm_name
= "sgx_clkdm",
1306 .recalc
= &followparent_recalc
,
1309 /* CORE power domain */
1311 static struct clk d2d_26m_fck
= {
1312 .name
= "d2d_26m_fck",
1313 .ops
= &clkops_omap2_dflt_wait
,
1315 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1316 .enable_bit
= OMAP3430ES1_EN_D2D_SHIFT
,
1317 .clkdm_name
= "d2d_clkdm",
1318 .recalc
= &followparent_recalc
,
1321 static struct clk modem_fck
= {
1322 .name
= "modem_fck",
1323 .ops
= &clkops_omap2_dflt_wait
,
1325 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1326 .enable_bit
= OMAP3430_EN_MODEM_SHIFT
,
1327 .clkdm_name
= "d2d_clkdm",
1328 .recalc
= &followparent_recalc
,
1331 static struct clk sad2d_ick
= {
1332 .name
= "sad2d_ick",
1333 .ops
= &clkops_omap2_dflt_wait
,
1335 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1336 .enable_bit
= OMAP3430_EN_SAD2D_SHIFT
,
1337 .clkdm_name
= "d2d_clkdm",
1338 .recalc
= &followparent_recalc
,
1341 static struct clk mad2d_ick
= {
1342 .name
= "mad2d_ick",
1343 .ops
= &clkops_omap2_dflt_wait
,
1345 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN3
),
1346 .enable_bit
= OMAP3430_EN_MAD2D_SHIFT
,
1347 .clkdm_name
= "d2d_clkdm",
1348 .recalc
= &followparent_recalc
,
1351 static const struct clksel omap343x_gpt_clksel
[] = {
1352 { .parent
= &omap_32k_fck
, .rates
= gpt_32k_rates
},
1353 { .parent
= &sys_ck
, .rates
= gpt_sys_rates
},
1357 static struct clk gpt10_fck
= {
1358 .name
= "gpt10_fck",
1359 .ops
= &clkops_omap2_dflt_wait
,
1361 .init
= &omap2_init_clksel_parent
,
1362 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1363 .enable_bit
= OMAP3430_EN_GPT10_SHIFT
,
1364 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1365 .clksel_mask
= OMAP3430_CLKSEL_GPT10_MASK
,
1366 .clksel
= omap343x_gpt_clksel
,
1367 .clkdm_name
= "core_l4_clkdm",
1368 .recalc
= &omap2_clksel_recalc
,
1371 static struct clk gpt11_fck
= {
1372 .name
= "gpt11_fck",
1373 .ops
= &clkops_omap2_dflt_wait
,
1375 .init
= &omap2_init_clksel_parent
,
1376 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1377 .enable_bit
= OMAP3430_EN_GPT11_SHIFT
,
1378 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1379 .clksel_mask
= OMAP3430_CLKSEL_GPT11_MASK
,
1380 .clksel
= omap343x_gpt_clksel
,
1381 .clkdm_name
= "core_l4_clkdm",
1382 .recalc
= &omap2_clksel_recalc
,
1385 static struct clk cpefuse_fck
= {
1386 .name
= "cpefuse_fck",
1387 .ops
= &clkops_omap2_dflt
,
1389 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
1390 .enable_bit
= OMAP3430ES2_EN_CPEFUSE_SHIFT
,
1391 .recalc
= &followparent_recalc
,
1394 static struct clk ts_fck
= {
1396 .ops
= &clkops_omap2_dflt
,
1397 .parent
= &omap_32k_fck
,
1398 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
1399 .enable_bit
= OMAP3430ES2_EN_TS_SHIFT
,
1400 .recalc
= &followparent_recalc
,
1403 static struct clk usbtll_fck
= {
1404 .name
= "usbtll_fck",
1405 .ops
= &clkops_omap2_dflt_wait
,
1406 .parent
= &dpll5_m2_ck
,
1407 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
1408 .enable_bit
= OMAP3430ES2_EN_USBTLL_SHIFT
,
1409 .recalc
= &followparent_recalc
,
1412 /* CORE 96M FCLK-derived clocks */
1414 static struct clk core_96m_fck
= {
1415 .name
= "core_96m_fck",
1416 .ops
= &clkops_null
,
1417 .parent
= &omap_96m_fck
,
1418 .clkdm_name
= "core_l4_clkdm",
1419 .recalc
= &followparent_recalc
,
1422 static struct clk mmchs3_fck
= {
1423 .name
= "mmchs3_fck",
1424 .ops
= &clkops_omap2_dflt_wait
,
1425 .parent
= &core_96m_fck
,
1426 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1427 .enable_bit
= OMAP3430ES2_EN_MMC3_SHIFT
,
1428 .clkdm_name
= "core_l4_clkdm",
1429 .recalc
= &followparent_recalc
,
1432 static struct clk mmchs2_fck
= {
1433 .name
= "mmchs2_fck",
1434 .ops
= &clkops_omap2_dflt_wait
,
1435 .parent
= &core_96m_fck
,
1436 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1437 .enable_bit
= OMAP3430_EN_MMC2_SHIFT
,
1438 .clkdm_name
= "core_l4_clkdm",
1439 .recalc
= &followparent_recalc
,
1442 static struct clk mspro_fck
= {
1443 .name
= "mspro_fck",
1444 .ops
= &clkops_omap2_dflt_wait
,
1445 .parent
= &core_96m_fck
,
1446 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1447 .enable_bit
= OMAP3430_EN_MSPRO_SHIFT
,
1448 .clkdm_name
= "core_l4_clkdm",
1449 .recalc
= &followparent_recalc
,
1452 static struct clk mmchs1_fck
= {
1453 .name
= "mmchs1_fck",
1454 .ops
= &clkops_omap2_dflt_wait
,
1455 .parent
= &core_96m_fck
,
1456 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1457 .enable_bit
= OMAP3430_EN_MMC1_SHIFT
,
1458 .clkdm_name
= "core_l4_clkdm",
1459 .recalc
= &followparent_recalc
,
1462 static struct clk i2c3_fck
= {
1464 .ops
= &clkops_omap2_dflt_wait
,
1465 .parent
= &core_96m_fck
,
1466 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1467 .enable_bit
= OMAP3430_EN_I2C3_SHIFT
,
1468 .clkdm_name
= "core_l4_clkdm",
1469 .recalc
= &followparent_recalc
,
1472 static struct clk i2c2_fck
= {
1474 .ops
= &clkops_omap2_dflt_wait
,
1475 .parent
= &core_96m_fck
,
1476 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1477 .enable_bit
= OMAP3430_EN_I2C2_SHIFT
,
1478 .clkdm_name
= "core_l4_clkdm",
1479 .recalc
= &followparent_recalc
,
1482 static struct clk i2c1_fck
= {
1484 .ops
= &clkops_omap2_dflt_wait
,
1485 .parent
= &core_96m_fck
,
1486 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1487 .enable_bit
= OMAP3430_EN_I2C1_SHIFT
,
1488 .clkdm_name
= "core_l4_clkdm",
1489 .recalc
= &followparent_recalc
,
1493 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1494 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1496 static const struct clksel_rate common_mcbsp_96m_rates
[] = {
1497 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
1501 static const struct clksel_rate common_mcbsp_mcbsp_rates
[] = {
1502 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
1506 static const struct clksel mcbsp_15_clksel
[] = {
1507 { .parent
= &core_96m_fck
, .rates
= common_mcbsp_96m_rates
},
1508 { .parent
= &mcbsp_clks
, .rates
= common_mcbsp_mcbsp_rates
},
1512 static struct clk mcbsp5_fck
= {
1513 .name
= "mcbsp5_fck",
1514 .ops
= &clkops_omap2_dflt_wait
,
1515 .init
= &omap2_init_clksel_parent
,
1516 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1517 .enable_bit
= OMAP3430_EN_MCBSP5_SHIFT
,
1518 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
1519 .clksel_mask
= OMAP2_MCBSP5_CLKS_MASK
,
1520 .clksel
= mcbsp_15_clksel
,
1521 .clkdm_name
= "core_l4_clkdm",
1522 .recalc
= &omap2_clksel_recalc
,
1525 static struct clk mcbsp1_fck
= {
1526 .name
= "mcbsp1_fck",
1527 .ops
= &clkops_omap2_dflt_wait
,
1528 .init
= &omap2_init_clksel_parent
,
1529 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1530 .enable_bit
= OMAP3430_EN_MCBSP1_SHIFT
,
1531 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0
),
1532 .clksel_mask
= OMAP2_MCBSP1_CLKS_MASK
,
1533 .clksel
= mcbsp_15_clksel
,
1534 .clkdm_name
= "core_l4_clkdm",
1535 .recalc
= &omap2_clksel_recalc
,
1538 /* CORE_48M_FCK-derived clocks */
1540 static struct clk core_48m_fck
= {
1541 .name
= "core_48m_fck",
1542 .ops
= &clkops_null
,
1543 .parent
= &omap_48m_fck
,
1544 .clkdm_name
= "core_l4_clkdm",
1545 .recalc
= &followparent_recalc
,
1548 static struct clk mcspi4_fck
= {
1549 .name
= "mcspi4_fck",
1550 .ops
= &clkops_omap2_dflt_wait
,
1551 .parent
= &core_48m_fck
,
1552 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1553 .enable_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
1554 .recalc
= &followparent_recalc
,
1557 static struct clk mcspi3_fck
= {
1558 .name
= "mcspi3_fck",
1559 .ops
= &clkops_omap2_dflt_wait
,
1560 .parent
= &core_48m_fck
,
1561 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1562 .enable_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
1563 .recalc
= &followparent_recalc
,
1566 static struct clk mcspi2_fck
= {
1567 .name
= "mcspi2_fck",
1568 .ops
= &clkops_omap2_dflt_wait
,
1569 .parent
= &core_48m_fck
,
1570 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1571 .enable_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
1572 .recalc
= &followparent_recalc
,
1575 static struct clk mcspi1_fck
= {
1576 .name
= "mcspi1_fck",
1577 .ops
= &clkops_omap2_dflt_wait
,
1578 .parent
= &core_48m_fck
,
1579 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1580 .enable_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
1581 .recalc
= &followparent_recalc
,
1584 static struct clk uart2_fck
= {
1585 .name
= "uart2_fck",
1586 .ops
= &clkops_omap2_dflt_wait
,
1587 .parent
= &core_48m_fck
,
1588 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1589 .enable_bit
= OMAP3430_EN_UART2_SHIFT
,
1590 .clkdm_name
= "core_l4_clkdm",
1591 .recalc
= &followparent_recalc
,
1594 static struct clk uart1_fck
= {
1595 .name
= "uart1_fck",
1596 .ops
= &clkops_omap2_dflt_wait
,
1597 .parent
= &core_48m_fck
,
1598 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1599 .enable_bit
= OMAP3430_EN_UART1_SHIFT
,
1600 .clkdm_name
= "core_l4_clkdm",
1601 .recalc
= &followparent_recalc
,
1604 static struct clk fshostusb_fck
= {
1605 .name
= "fshostusb_fck",
1606 .ops
= &clkops_omap2_dflt_wait
,
1607 .parent
= &core_48m_fck
,
1608 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1609 .enable_bit
= OMAP3430ES1_EN_FSHOSTUSB_SHIFT
,
1610 .recalc
= &followparent_recalc
,
1613 /* CORE_12M_FCK based clocks */
1615 static struct clk core_12m_fck
= {
1616 .name
= "core_12m_fck",
1617 .ops
= &clkops_null
,
1618 .parent
= &omap_12m_fck
,
1619 .clkdm_name
= "core_l4_clkdm",
1620 .recalc
= &followparent_recalc
,
1623 static struct clk hdq_fck
= {
1625 .ops
= &clkops_omap2_dflt_wait
,
1626 .parent
= &core_12m_fck
,
1627 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1628 .enable_bit
= OMAP3430_EN_HDQ_SHIFT
,
1629 .recalc
= &followparent_recalc
,
1632 /* DPLL3-derived clock */
1634 static const struct clksel_rate ssi_ssr_corex2_rates
[] = {
1635 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
1636 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
1637 { .div
= 3, .val
= 3, .flags
= RATE_IN_3XXX
},
1638 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
1639 { .div
= 6, .val
= 6, .flags
= RATE_IN_3XXX
},
1640 { .div
= 8, .val
= 8, .flags
= RATE_IN_3XXX
},
1644 static const struct clksel ssi_ssr_clksel
[] = {
1645 { .parent
= &corex2_fck
, .rates
= ssi_ssr_corex2_rates
},
1649 static struct clk ssi_ssr_fck_3430es1
= {
1650 .name
= "ssi_ssr_fck",
1651 .ops
= &clkops_omap2_dflt
,
1652 .init
= &omap2_init_clksel_parent
,
1653 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1654 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
1655 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1656 .clksel_mask
= OMAP3430_CLKSEL_SSI_MASK
,
1657 .clksel
= ssi_ssr_clksel
,
1658 .clkdm_name
= "core_l4_clkdm",
1659 .recalc
= &omap2_clksel_recalc
,
1662 static struct clk ssi_ssr_fck_3430es2
= {
1663 .name
= "ssi_ssr_fck",
1664 .ops
= &clkops_omap3430es2_ssi_wait
,
1665 .init
= &omap2_init_clksel_parent
,
1666 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1667 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
1668 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1669 .clksel_mask
= OMAP3430_CLKSEL_SSI_MASK
,
1670 .clksel
= ssi_ssr_clksel
,
1671 .clkdm_name
= "core_l4_clkdm",
1672 .recalc
= &omap2_clksel_recalc
,
1675 static struct clk ssi_sst_fck_3430es1
= {
1676 .name
= "ssi_sst_fck",
1677 .ops
= &clkops_null
,
1678 .parent
= &ssi_ssr_fck_3430es1
,
1680 .recalc
= &omap_fixed_divisor_recalc
,
1683 static struct clk ssi_sst_fck_3430es2
= {
1684 .name
= "ssi_sst_fck",
1685 .ops
= &clkops_null
,
1686 .parent
= &ssi_ssr_fck_3430es2
,
1688 .recalc
= &omap_fixed_divisor_recalc
,
1693 /* CORE_L3_ICK based clocks */
1695 static struct clk core_l3_ick
= {
1696 .name
= "core_l3_ick",
1697 .ops
= &clkops_null
,
1699 .clkdm_name
= "core_l3_clkdm",
1700 .recalc
= &followparent_recalc
,
1703 static struct clk hsotgusb_ick_3430es1
= {
1704 .name
= "hsotgusb_ick",
1705 .ops
= &clkops_omap2_dflt
,
1706 .parent
= &core_l3_ick
,
1707 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1708 .enable_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
1709 .clkdm_name
= "core_l3_clkdm",
1710 .recalc
= &followparent_recalc
,
1713 static struct clk hsotgusb_ick_3430es2
= {
1714 .name
= "hsotgusb_ick",
1715 .ops
= &clkops_omap3430es2_hsotgusb_wait
,
1716 .parent
= &core_l3_ick
,
1717 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1718 .enable_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
1719 .clkdm_name
= "core_l3_clkdm",
1720 .recalc
= &followparent_recalc
,
1723 static struct clk sdrc_ick
= {
1725 .ops
= &clkops_omap2_dflt_wait
,
1726 .parent
= &core_l3_ick
,
1727 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1728 .enable_bit
= OMAP3430_EN_SDRC_SHIFT
,
1729 .flags
= ENABLE_ON_INIT
,
1730 .clkdm_name
= "core_l3_clkdm",
1731 .recalc
= &followparent_recalc
,
1734 static struct clk gpmc_fck
= {
1736 .ops
= &clkops_null
,
1737 .parent
= &core_l3_ick
,
1738 .flags
= ENABLE_ON_INIT
, /* huh? */
1739 .clkdm_name
= "core_l3_clkdm",
1740 .recalc
= &followparent_recalc
,
1743 /* SECURITY_L3_ICK based clocks */
1745 static struct clk security_l3_ick
= {
1746 .name
= "security_l3_ick",
1747 .ops
= &clkops_null
,
1749 .recalc
= &followparent_recalc
,
1752 static struct clk pka_ick
= {
1754 .ops
= &clkops_omap2_dflt_wait
,
1755 .parent
= &security_l3_ick
,
1756 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1757 .enable_bit
= OMAP3430_EN_PKA_SHIFT
,
1758 .recalc
= &followparent_recalc
,
1761 /* CORE_L4_ICK based clocks */
1763 static struct clk core_l4_ick
= {
1764 .name
= "core_l4_ick",
1765 .ops
= &clkops_null
,
1767 .clkdm_name
= "core_l4_clkdm",
1768 .recalc
= &followparent_recalc
,
1771 static struct clk usbtll_ick
= {
1772 .name
= "usbtll_ick",
1773 .ops
= &clkops_omap2_dflt_wait
,
1774 .parent
= &core_l4_ick
,
1775 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN3
),
1776 .enable_bit
= OMAP3430ES2_EN_USBTLL_SHIFT
,
1777 .clkdm_name
= "core_l4_clkdm",
1778 .recalc
= &followparent_recalc
,
1781 static struct clk mmchs3_ick
= {
1782 .name
= "mmchs3_ick",
1783 .ops
= &clkops_omap2_dflt_wait
,
1784 .parent
= &core_l4_ick
,
1785 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1786 .enable_bit
= OMAP3430ES2_EN_MMC3_SHIFT
,
1787 .clkdm_name
= "core_l4_clkdm",
1788 .recalc
= &followparent_recalc
,
1791 /* Intersystem Communication Registers - chassis mode only */
1792 static struct clk icr_ick
= {
1794 .ops
= &clkops_omap2_dflt_wait
,
1795 .parent
= &core_l4_ick
,
1796 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1797 .enable_bit
= OMAP3430_EN_ICR_SHIFT
,
1798 .clkdm_name
= "core_l4_clkdm",
1799 .recalc
= &followparent_recalc
,
1802 static struct clk aes2_ick
= {
1804 .ops
= &clkops_omap2_dflt_wait
,
1805 .parent
= &core_l4_ick
,
1806 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1807 .enable_bit
= OMAP3430_EN_AES2_SHIFT
,
1808 .clkdm_name
= "core_l4_clkdm",
1809 .recalc
= &followparent_recalc
,
1812 static struct clk sha12_ick
= {
1813 .name
= "sha12_ick",
1814 .ops
= &clkops_omap2_dflt_wait
,
1815 .parent
= &core_l4_ick
,
1816 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1817 .enable_bit
= OMAP3430_EN_SHA12_SHIFT
,
1818 .clkdm_name
= "core_l4_clkdm",
1819 .recalc
= &followparent_recalc
,
1822 static struct clk des2_ick
= {
1824 .ops
= &clkops_omap2_dflt_wait
,
1825 .parent
= &core_l4_ick
,
1826 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1827 .enable_bit
= OMAP3430_EN_DES2_SHIFT
,
1828 .clkdm_name
= "core_l4_clkdm",
1829 .recalc
= &followparent_recalc
,
1832 static struct clk mmchs2_ick
= {
1833 .name
= "mmchs2_ick",
1834 .ops
= &clkops_omap2_dflt_wait
,
1835 .parent
= &core_l4_ick
,
1836 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1837 .enable_bit
= OMAP3430_EN_MMC2_SHIFT
,
1838 .clkdm_name
= "core_l4_clkdm",
1839 .recalc
= &followparent_recalc
,
1842 static struct clk mmchs1_ick
= {
1843 .name
= "mmchs1_ick",
1844 .ops
= &clkops_omap2_dflt_wait
,
1845 .parent
= &core_l4_ick
,
1846 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1847 .enable_bit
= OMAP3430_EN_MMC1_SHIFT
,
1848 .clkdm_name
= "core_l4_clkdm",
1849 .recalc
= &followparent_recalc
,
1852 static struct clk mspro_ick
= {
1853 .name
= "mspro_ick",
1854 .ops
= &clkops_omap2_dflt_wait
,
1855 .parent
= &core_l4_ick
,
1856 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1857 .enable_bit
= OMAP3430_EN_MSPRO_SHIFT
,
1858 .clkdm_name
= "core_l4_clkdm",
1859 .recalc
= &followparent_recalc
,
1862 static struct clk hdq_ick
= {
1864 .ops
= &clkops_omap2_dflt_wait
,
1865 .parent
= &core_l4_ick
,
1866 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1867 .enable_bit
= OMAP3430_EN_HDQ_SHIFT
,
1868 .clkdm_name
= "core_l4_clkdm",
1869 .recalc
= &followparent_recalc
,
1872 static struct clk mcspi4_ick
= {
1873 .name
= "mcspi4_ick",
1874 .ops
= &clkops_omap2_dflt_wait
,
1875 .parent
= &core_l4_ick
,
1876 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1877 .enable_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
1878 .clkdm_name
= "core_l4_clkdm",
1879 .recalc
= &followparent_recalc
,
1882 static struct clk mcspi3_ick
= {
1883 .name
= "mcspi3_ick",
1884 .ops
= &clkops_omap2_dflt_wait
,
1885 .parent
= &core_l4_ick
,
1886 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1887 .enable_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
1888 .clkdm_name
= "core_l4_clkdm",
1889 .recalc
= &followparent_recalc
,
1892 static struct clk mcspi2_ick
= {
1893 .name
= "mcspi2_ick",
1894 .ops
= &clkops_omap2_dflt_wait
,
1895 .parent
= &core_l4_ick
,
1896 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1897 .enable_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
1898 .clkdm_name
= "core_l4_clkdm",
1899 .recalc
= &followparent_recalc
,
1902 static struct clk mcspi1_ick
= {
1903 .name
= "mcspi1_ick",
1904 .ops
= &clkops_omap2_dflt_wait
,
1905 .parent
= &core_l4_ick
,
1906 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1907 .enable_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
1908 .clkdm_name
= "core_l4_clkdm",
1909 .recalc
= &followparent_recalc
,
1912 static struct clk i2c3_ick
= {
1914 .ops
= &clkops_omap2_dflt_wait
,
1915 .parent
= &core_l4_ick
,
1916 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1917 .enable_bit
= OMAP3430_EN_I2C3_SHIFT
,
1918 .clkdm_name
= "core_l4_clkdm",
1919 .recalc
= &followparent_recalc
,
1922 static struct clk i2c2_ick
= {
1924 .ops
= &clkops_omap2_dflt_wait
,
1925 .parent
= &core_l4_ick
,
1926 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1927 .enable_bit
= OMAP3430_EN_I2C2_SHIFT
,
1928 .clkdm_name
= "core_l4_clkdm",
1929 .recalc
= &followparent_recalc
,
1932 static struct clk i2c1_ick
= {
1934 .ops
= &clkops_omap2_dflt_wait
,
1935 .parent
= &core_l4_ick
,
1936 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1937 .enable_bit
= OMAP3430_EN_I2C1_SHIFT
,
1938 .clkdm_name
= "core_l4_clkdm",
1939 .recalc
= &followparent_recalc
,
1942 static struct clk uart2_ick
= {
1943 .name
= "uart2_ick",
1944 .ops
= &clkops_omap2_dflt_wait
,
1945 .parent
= &core_l4_ick
,
1946 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1947 .enable_bit
= OMAP3430_EN_UART2_SHIFT
,
1948 .clkdm_name
= "core_l4_clkdm",
1949 .recalc
= &followparent_recalc
,
1952 static struct clk uart1_ick
= {
1953 .name
= "uart1_ick",
1954 .ops
= &clkops_omap2_dflt_wait
,
1955 .parent
= &core_l4_ick
,
1956 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1957 .enable_bit
= OMAP3430_EN_UART1_SHIFT
,
1958 .clkdm_name
= "core_l4_clkdm",
1959 .recalc
= &followparent_recalc
,
1962 static struct clk gpt11_ick
= {
1963 .name
= "gpt11_ick",
1964 .ops
= &clkops_omap2_dflt_wait
,
1965 .parent
= &core_l4_ick
,
1966 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1967 .enable_bit
= OMAP3430_EN_GPT11_SHIFT
,
1968 .clkdm_name
= "core_l4_clkdm",
1969 .recalc
= &followparent_recalc
,
1972 static struct clk gpt10_ick
= {
1973 .name
= "gpt10_ick",
1974 .ops
= &clkops_omap2_dflt_wait
,
1975 .parent
= &core_l4_ick
,
1976 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1977 .enable_bit
= OMAP3430_EN_GPT10_SHIFT
,
1978 .clkdm_name
= "core_l4_clkdm",
1979 .recalc
= &followparent_recalc
,
1982 static struct clk mcbsp5_ick
= {
1983 .name
= "mcbsp5_ick",
1984 .ops
= &clkops_omap2_dflt_wait
,
1985 .parent
= &core_l4_ick
,
1986 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1987 .enable_bit
= OMAP3430_EN_MCBSP5_SHIFT
,
1988 .clkdm_name
= "core_l4_clkdm",
1989 .recalc
= &followparent_recalc
,
1992 static struct clk mcbsp1_ick
= {
1993 .name
= "mcbsp1_ick",
1994 .ops
= &clkops_omap2_dflt_wait
,
1995 .parent
= &core_l4_ick
,
1996 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1997 .enable_bit
= OMAP3430_EN_MCBSP1_SHIFT
,
1998 .clkdm_name
= "core_l4_clkdm",
1999 .recalc
= &followparent_recalc
,
2002 static struct clk fac_ick
= {
2004 .ops
= &clkops_omap2_dflt_wait
,
2005 .parent
= &core_l4_ick
,
2006 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2007 .enable_bit
= OMAP3430ES1_EN_FAC_SHIFT
,
2008 .clkdm_name
= "core_l4_clkdm",
2009 .recalc
= &followparent_recalc
,
2012 static struct clk mailboxes_ick
= {
2013 .name
= "mailboxes_ick",
2014 .ops
= &clkops_omap2_dflt_wait
,
2015 .parent
= &core_l4_ick
,
2016 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2017 .enable_bit
= OMAP3430_EN_MAILBOXES_SHIFT
,
2018 .clkdm_name
= "core_l4_clkdm",
2019 .recalc
= &followparent_recalc
,
2022 static struct clk omapctrl_ick
= {
2023 .name
= "omapctrl_ick",
2024 .ops
= &clkops_omap2_dflt_wait
,
2025 .parent
= &core_l4_ick
,
2026 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2027 .enable_bit
= OMAP3430_EN_OMAPCTRL_SHIFT
,
2028 .flags
= ENABLE_ON_INIT
,
2029 .recalc
= &followparent_recalc
,
2032 /* SSI_L4_ICK based clocks */
2034 static struct clk ssi_l4_ick
= {
2035 .name
= "ssi_l4_ick",
2036 .ops
= &clkops_null
,
2038 .clkdm_name
= "core_l4_clkdm",
2039 .recalc
= &followparent_recalc
,
2042 static struct clk ssi_ick_3430es1
= {
2044 .ops
= &clkops_omap2_dflt
,
2045 .parent
= &ssi_l4_ick
,
2046 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2047 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
2048 .clkdm_name
= "core_l4_clkdm",
2049 .recalc
= &followparent_recalc
,
2052 static struct clk ssi_ick_3430es2
= {
2054 .ops
= &clkops_omap3430es2_ssi_wait
,
2055 .parent
= &ssi_l4_ick
,
2056 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2057 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
2058 .clkdm_name
= "core_l4_clkdm",
2059 .recalc
= &followparent_recalc
,
2062 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2063 * but l4_ick makes more sense to me */
2065 static const struct clksel usb_l4_clksel
[] = {
2066 { .parent
= &l4_ick
, .rates
= div2_rates
},
2070 static struct clk usb_l4_ick
= {
2071 .name
= "usb_l4_ick",
2072 .ops
= &clkops_omap2_dflt_wait
,
2074 .init
= &omap2_init_clksel_parent
,
2075 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2076 .enable_bit
= OMAP3430ES1_EN_FSHOSTUSB_SHIFT
,
2077 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
2078 .clksel_mask
= OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK
,
2079 .clksel
= usb_l4_clksel
,
2080 .recalc
= &omap2_clksel_recalc
,
2083 /* SECURITY_L4_ICK2 based clocks */
2085 static struct clk security_l4_ick2
= {
2086 .name
= "security_l4_ick2",
2087 .ops
= &clkops_null
,
2089 .recalc
= &followparent_recalc
,
2092 static struct clk aes1_ick
= {
2094 .ops
= &clkops_omap2_dflt_wait
,
2095 .parent
= &security_l4_ick2
,
2096 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2097 .enable_bit
= OMAP3430_EN_AES1_SHIFT
,
2098 .recalc
= &followparent_recalc
,
2101 static struct clk rng_ick
= {
2103 .ops
= &clkops_omap2_dflt_wait
,
2104 .parent
= &security_l4_ick2
,
2105 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2106 .enable_bit
= OMAP3430_EN_RNG_SHIFT
,
2107 .recalc
= &followparent_recalc
,
2110 static struct clk sha11_ick
= {
2111 .name
= "sha11_ick",
2112 .ops
= &clkops_omap2_dflt_wait
,
2113 .parent
= &security_l4_ick2
,
2114 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2115 .enable_bit
= OMAP3430_EN_SHA11_SHIFT
,
2116 .recalc
= &followparent_recalc
,
2119 static struct clk des1_ick
= {
2121 .ops
= &clkops_omap2_dflt_wait
,
2122 .parent
= &security_l4_ick2
,
2123 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2124 .enable_bit
= OMAP3430_EN_DES1_SHIFT
,
2125 .recalc
= &followparent_recalc
,
2129 static struct clk dss1_alwon_fck_3430es1
= {
2130 .name
= "dss1_alwon_fck",
2131 .ops
= &clkops_omap2_dflt
,
2132 .parent
= &dpll4_m4x2_ck
,
2133 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2134 .enable_bit
= OMAP3430_EN_DSS1_SHIFT
,
2135 .clkdm_name
= "dss_clkdm",
2136 .recalc
= &followparent_recalc
,
2139 static struct clk dss1_alwon_fck_3430es2
= {
2140 .name
= "dss1_alwon_fck",
2141 .ops
= &clkops_omap3430es2_dss_usbhost_wait
,
2142 .parent
= &dpll4_m4x2_ck
,
2143 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2144 .enable_bit
= OMAP3430_EN_DSS1_SHIFT
,
2145 .clkdm_name
= "dss_clkdm",
2146 .recalc
= &followparent_recalc
,
2149 static struct clk dss_tv_fck
= {
2150 .name
= "dss_tv_fck",
2151 .ops
= &clkops_omap2_dflt
,
2152 .parent
= &omap_54m_fck
,
2153 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2154 .enable_bit
= OMAP3430_EN_TV_SHIFT
,
2155 .clkdm_name
= "dss_clkdm",
2156 .recalc
= &followparent_recalc
,
2159 static struct clk dss_96m_fck
= {
2160 .name
= "dss_96m_fck",
2161 .ops
= &clkops_omap2_dflt
,
2162 .parent
= &omap_96m_fck
,
2163 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2164 .enable_bit
= OMAP3430_EN_TV_SHIFT
,
2165 .clkdm_name
= "dss_clkdm",
2166 .recalc
= &followparent_recalc
,
2169 static struct clk dss2_alwon_fck
= {
2170 .name
= "dss2_alwon_fck",
2171 .ops
= &clkops_omap2_dflt
,
2173 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2174 .enable_bit
= OMAP3430_EN_DSS2_SHIFT
,
2175 .clkdm_name
= "dss_clkdm",
2176 .recalc
= &followparent_recalc
,
2179 static struct clk dss_ick_3430es1
= {
2180 /* Handles both L3 and L4 clocks */
2182 .ops
= &clkops_omap2_dflt
,
2184 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_ICLKEN
),
2185 .enable_bit
= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT
,
2186 .clkdm_name
= "dss_clkdm",
2187 .recalc
= &followparent_recalc
,
2190 static struct clk dss_ick_3430es2
= {
2191 /* Handles both L3 and L4 clocks */
2193 .ops
= &clkops_omap3430es2_dss_usbhost_wait
,
2195 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_ICLKEN
),
2196 .enable_bit
= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT
,
2197 .clkdm_name
= "dss_clkdm",
2198 .recalc
= &followparent_recalc
,
2203 static struct clk cam_mclk
= {
2205 .ops
= &clkops_omap2_dflt
,
2206 .parent
= &dpll4_m5x2_ck
,
2207 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_FCLKEN
),
2208 .enable_bit
= OMAP3430_EN_CAM_SHIFT
,
2209 .clkdm_name
= "cam_clkdm",
2210 .recalc
= &followparent_recalc
,
2213 static struct clk cam_ick
= {
2214 /* Handles both L3 and L4 clocks */
2216 .ops
= &clkops_omap2_dflt
,
2218 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_ICLKEN
),
2219 .enable_bit
= OMAP3430_EN_CAM_SHIFT
,
2220 .clkdm_name
= "cam_clkdm",
2221 .recalc
= &followparent_recalc
,
2224 static struct clk csi2_96m_fck
= {
2225 .name
= "csi2_96m_fck",
2226 .ops
= &clkops_omap2_dflt
,
2227 .parent
= &core_96m_fck
,
2228 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_FCLKEN
),
2229 .enable_bit
= OMAP3430_EN_CSI2_SHIFT
,
2230 .clkdm_name
= "cam_clkdm",
2231 .recalc
= &followparent_recalc
,
2234 /* USBHOST - 3430ES2 only */
2236 static struct clk usbhost_120m_fck
= {
2237 .name
= "usbhost_120m_fck",
2238 .ops
= &clkops_omap2_dflt
,
2239 .parent
= &dpll5_m2_ck
,
2240 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_FCLKEN
),
2241 .enable_bit
= OMAP3430ES2_EN_USBHOST2_SHIFT
,
2242 .clkdm_name
= "usbhost_clkdm",
2243 .recalc
= &followparent_recalc
,
2246 static struct clk usbhost_48m_fck
= {
2247 .name
= "usbhost_48m_fck",
2248 .ops
= &clkops_omap3430es2_dss_usbhost_wait
,
2249 .parent
= &omap_48m_fck
,
2250 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_FCLKEN
),
2251 .enable_bit
= OMAP3430ES2_EN_USBHOST1_SHIFT
,
2252 .clkdm_name
= "usbhost_clkdm",
2253 .recalc
= &followparent_recalc
,
2256 static struct clk usbhost_ick
= {
2257 /* Handles both L3 and L4 clocks */
2258 .name
= "usbhost_ick",
2259 .ops
= &clkops_omap3430es2_dss_usbhost_wait
,
2261 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_ICLKEN
),
2262 .enable_bit
= OMAP3430ES2_EN_USBHOST_SHIFT
,
2263 .clkdm_name
= "usbhost_clkdm",
2264 .recalc
= &followparent_recalc
,
2269 static const struct clksel_rate usim_96m_rates
[] = {
2270 { .div
= 2, .val
= 3, .flags
= RATE_IN_3XXX
},
2271 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
2272 { .div
= 8, .val
= 5, .flags
= RATE_IN_3XXX
},
2273 { .div
= 10, .val
= 6, .flags
= RATE_IN_3XXX
},
2277 static const struct clksel_rate usim_120m_rates
[] = {
2278 { .div
= 4, .val
= 7, .flags
= RATE_IN_3XXX
},
2279 { .div
= 8, .val
= 8, .flags
= RATE_IN_3XXX
},
2280 { .div
= 16, .val
= 9, .flags
= RATE_IN_3XXX
},
2281 { .div
= 20, .val
= 10, .flags
= RATE_IN_3XXX
},
2285 static const struct clksel usim_clksel
[] = {
2286 { .parent
= &omap_96m_fck
, .rates
= usim_96m_rates
},
2287 { .parent
= &dpll5_m2_ck
, .rates
= usim_120m_rates
},
2288 { .parent
= &sys_ck
, .rates
= div2_rates
},
2293 static struct clk usim_fck
= {
2295 .ops
= &clkops_omap2_dflt_wait
,
2296 .init
= &omap2_init_clksel_parent
,
2297 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2298 .enable_bit
= OMAP3430ES2_EN_USIMOCP_SHIFT
,
2299 .clksel_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
2300 .clksel_mask
= OMAP3430ES2_CLKSEL_USIMOCP_MASK
,
2301 .clksel
= usim_clksel
,
2302 .recalc
= &omap2_clksel_recalc
,
2305 static struct clk gpt1_fck
= {
2307 .ops
= &clkops_omap2_dflt_wait
,
2308 .init
= &omap2_init_clksel_parent
,
2309 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2310 .enable_bit
= OMAP3430_EN_GPT1_SHIFT
,
2311 .clksel_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
2312 .clksel_mask
= OMAP3430_CLKSEL_GPT1_MASK
,
2313 .clksel
= omap343x_gpt_clksel
,
2314 .clkdm_name
= "wkup_clkdm",
2315 .recalc
= &omap2_clksel_recalc
,
2318 static struct clk wkup_32k_fck
= {
2319 .name
= "wkup_32k_fck",
2320 .ops
= &clkops_null
,
2321 .parent
= &omap_32k_fck
,
2322 .clkdm_name
= "wkup_clkdm",
2323 .recalc
= &followparent_recalc
,
2326 static struct clk gpio1_dbck
= {
2327 .name
= "gpio1_dbck",
2328 .ops
= &clkops_omap2_dflt
,
2329 .parent
= &wkup_32k_fck
,
2330 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2331 .enable_bit
= OMAP3430_EN_GPIO1_SHIFT
,
2332 .clkdm_name
= "wkup_clkdm",
2333 .recalc
= &followparent_recalc
,
2336 static struct clk wdt2_fck
= {
2338 .ops
= &clkops_omap2_dflt_wait
,
2339 .parent
= &wkup_32k_fck
,
2340 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2341 .enable_bit
= OMAP3430_EN_WDT2_SHIFT
,
2342 .clkdm_name
= "wkup_clkdm",
2343 .recalc
= &followparent_recalc
,
2346 static struct clk wkup_l4_ick
= {
2347 .name
= "wkup_l4_ick",
2348 .ops
= &clkops_null
,
2350 .clkdm_name
= "wkup_clkdm",
2351 .recalc
= &followparent_recalc
,
2355 /* Never specifically named in the TRM, so we have to infer a likely name */
2356 static struct clk usim_ick
= {
2358 .ops
= &clkops_omap2_dflt_wait
,
2359 .parent
= &wkup_l4_ick
,
2360 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2361 .enable_bit
= OMAP3430ES2_EN_USIMOCP_SHIFT
,
2362 .clkdm_name
= "wkup_clkdm",
2363 .recalc
= &followparent_recalc
,
2366 static struct clk wdt2_ick
= {
2368 .ops
= &clkops_omap2_dflt_wait
,
2369 .parent
= &wkup_l4_ick
,
2370 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2371 .enable_bit
= OMAP3430_EN_WDT2_SHIFT
,
2372 .clkdm_name
= "wkup_clkdm",
2373 .recalc
= &followparent_recalc
,
2376 static struct clk wdt1_ick
= {
2378 .ops
= &clkops_omap2_dflt_wait
,
2379 .parent
= &wkup_l4_ick
,
2380 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2381 .enable_bit
= OMAP3430_EN_WDT1_SHIFT
,
2382 .clkdm_name
= "wkup_clkdm",
2383 .recalc
= &followparent_recalc
,
2386 static struct clk gpio1_ick
= {
2387 .name
= "gpio1_ick",
2388 .ops
= &clkops_omap2_dflt_wait
,
2389 .parent
= &wkup_l4_ick
,
2390 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2391 .enable_bit
= OMAP3430_EN_GPIO1_SHIFT
,
2392 .clkdm_name
= "wkup_clkdm",
2393 .recalc
= &followparent_recalc
,
2396 static struct clk omap_32ksync_ick
= {
2397 .name
= "omap_32ksync_ick",
2398 .ops
= &clkops_omap2_dflt_wait
,
2399 .parent
= &wkup_l4_ick
,
2400 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2401 .enable_bit
= OMAP3430_EN_32KSYNC_SHIFT
,
2402 .clkdm_name
= "wkup_clkdm",
2403 .recalc
= &followparent_recalc
,
2406 static struct clk gpt12_ick
= {
2407 .name
= "gpt12_ick",
2408 .ops
= &clkops_omap2_dflt_wait
,
2409 .parent
= &wkup_l4_ick
,
2410 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2411 .enable_bit
= OMAP3430_EN_GPT12_SHIFT
,
2412 .clkdm_name
= "wkup_clkdm",
2413 .recalc
= &followparent_recalc
,
2416 static struct clk gpt1_ick
= {
2418 .ops
= &clkops_omap2_dflt_wait
,
2419 .parent
= &wkup_l4_ick
,
2420 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2421 .enable_bit
= OMAP3430_EN_GPT1_SHIFT
,
2422 .clkdm_name
= "wkup_clkdm",
2423 .recalc
= &followparent_recalc
,
2428 /* PER clock domain */
2430 static struct clk per_96m_fck
= {
2431 .name
= "per_96m_fck",
2432 .ops
= &clkops_null
,
2433 .parent
= &omap_96m_alwon_fck
,
2434 .clkdm_name
= "per_clkdm",
2435 .recalc
= &followparent_recalc
,
2438 static struct clk per_48m_fck
= {
2439 .name
= "per_48m_fck",
2440 .ops
= &clkops_null
,
2441 .parent
= &omap_48m_fck
,
2442 .clkdm_name
= "per_clkdm",
2443 .recalc
= &followparent_recalc
,
2446 static struct clk uart3_fck
= {
2447 .name
= "uart3_fck",
2448 .ops
= &clkops_omap2_dflt_wait
,
2449 .parent
= &per_48m_fck
,
2450 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2451 .enable_bit
= OMAP3430_EN_UART3_SHIFT
,
2452 .clkdm_name
= "per_clkdm",
2453 .recalc
= &followparent_recalc
,
2456 static struct clk gpt2_fck
= {
2458 .ops
= &clkops_omap2_dflt_wait
,
2459 .init
= &omap2_init_clksel_parent
,
2460 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2461 .enable_bit
= OMAP3430_EN_GPT2_SHIFT
,
2462 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2463 .clksel_mask
= OMAP3430_CLKSEL_GPT2_MASK
,
2464 .clksel
= omap343x_gpt_clksel
,
2465 .clkdm_name
= "per_clkdm",
2466 .recalc
= &omap2_clksel_recalc
,
2469 static struct clk gpt3_fck
= {
2471 .ops
= &clkops_omap2_dflt_wait
,
2472 .init
= &omap2_init_clksel_parent
,
2473 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2474 .enable_bit
= OMAP3430_EN_GPT3_SHIFT
,
2475 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2476 .clksel_mask
= OMAP3430_CLKSEL_GPT3_MASK
,
2477 .clksel
= omap343x_gpt_clksel
,
2478 .clkdm_name
= "per_clkdm",
2479 .recalc
= &omap2_clksel_recalc
,
2482 static struct clk gpt4_fck
= {
2484 .ops
= &clkops_omap2_dflt_wait
,
2485 .init
= &omap2_init_clksel_parent
,
2486 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2487 .enable_bit
= OMAP3430_EN_GPT4_SHIFT
,
2488 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2489 .clksel_mask
= OMAP3430_CLKSEL_GPT4_MASK
,
2490 .clksel
= omap343x_gpt_clksel
,
2491 .clkdm_name
= "per_clkdm",
2492 .recalc
= &omap2_clksel_recalc
,
2495 static struct clk gpt5_fck
= {
2497 .ops
= &clkops_omap2_dflt_wait
,
2498 .init
= &omap2_init_clksel_parent
,
2499 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2500 .enable_bit
= OMAP3430_EN_GPT5_SHIFT
,
2501 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2502 .clksel_mask
= OMAP3430_CLKSEL_GPT5_MASK
,
2503 .clksel
= omap343x_gpt_clksel
,
2504 .clkdm_name
= "per_clkdm",
2505 .recalc
= &omap2_clksel_recalc
,
2508 static struct clk gpt6_fck
= {
2510 .ops
= &clkops_omap2_dflt_wait
,
2511 .init
= &omap2_init_clksel_parent
,
2512 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2513 .enable_bit
= OMAP3430_EN_GPT6_SHIFT
,
2514 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2515 .clksel_mask
= OMAP3430_CLKSEL_GPT6_MASK
,
2516 .clksel
= omap343x_gpt_clksel
,
2517 .clkdm_name
= "per_clkdm",
2518 .recalc
= &omap2_clksel_recalc
,
2521 static struct clk gpt7_fck
= {
2523 .ops
= &clkops_omap2_dflt_wait
,
2524 .init
= &omap2_init_clksel_parent
,
2525 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2526 .enable_bit
= OMAP3430_EN_GPT7_SHIFT
,
2527 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2528 .clksel_mask
= OMAP3430_CLKSEL_GPT7_MASK
,
2529 .clksel
= omap343x_gpt_clksel
,
2530 .clkdm_name
= "per_clkdm",
2531 .recalc
= &omap2_clksel_recalc
,
2534 static struct clk gpt8_fck
= {
2536 .ops
= &clkops_omap2_dflt_wait
,
2537 .init
= &omap2_init_clksel_parent
,
2538 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2539 .enable_bit
= OMAP3430_EN_GPT8_SHIFT
,
2540 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2541 .clksel_mask
= OMAP3430_CLKSEL_GPT8_MASK
,
2542 .clksel
= omap343x_gpt_clksel
,
2543 .clkdm_name
= "per_clkdm",
2544 .recalc
= &omap2_clksel_recalc
,
2547 static struct clk gpt9_fck
= {
2549 .ops
= &clkops_omap2_dflt_wait
,
2550 .init
= &omap2_init_clksel_parent
,
2551 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2552 .enable_bit
= OMAP3430_EN_GPT9_SHIFT
,
2553 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2554 .clksel_mask
= OMAP3430_CLKSEL_GPT9_MASK
,
2555 .clksel
= omap343x_gpt_clksel
,
2556 .clkdm_name
= "per_clkdm",
2557 .recalc
= &omap2_clksel_recalc
,
2560 static struct clk per_32k_alwon_fck
= {
2561 .name
= "per_32k_alwon_fck",
2562 .ops
= &clkops_null
,
2563 .parent
= &omap_32k_fck
,
2564 .clkdm_name
= "per_clkdm",
2565 .recalc
= &followparent_recalc
,
2568 static struct clk gpio6_dbck
= {
2569 .name
= "gpio6_dbck",
2570 .ops
= &clkops_omap2_dflt
,
2571 .parent
= &per_32k_alwon_fck
,
2572 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2573 .enable_bit
= OMAP3430_EN_GPIO6_SHIFT
,
2574 .clkdm_name
= "per_clkdm",
2575 .recalc
= &followparent_recalc
,
2578 static struct clk gpio5_dbck
= {
2579 .name
= "gpio5_dbck",
2580 .ops
= &clkops_omap2_dflt
,
2581 .parent
= &per_32k_alwon_fck
,
2582 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2583 .enable_bit
= OMAP3430_EN_GPIO5_SHIFT
,
2584 .clkdm_name
= "per_clkdm",
2585 .recalc
= &followparent_recalc
,
2588 static struct clk gpio4_dbck
= {
2589 .name
= "gpio4_dbck",
2590 .ops
= &clkops_omap2_dflt
,
2591 .parent
= &per_32k_alwon_fck
,
2592 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2593 .enable_bit
= OMAP3430_EN_GPIO4_SHIFT
,
2594 .clkdm_name
= "per_clkdm",
2595 .recalc
= &followparent_recalc
,
2598 static struct clk gpio3_dbck
= {
2599 .name
= "gpio3_dbck",
2600 .ops
= &clkops_omap2_dflt
,
2601 .parent
= &per_32k_alwon_fck
,
2602 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2603 .enable_bit
= OMAP3430_EN_GPIO3_SHIFT
,
2604 .clkdm_name
= "per_clkdm",
2605 .recalc
= &followparent_recalc
,
2608 static struct clk gpio2_dbck
= {
2609 .name
= "gpio2_dbck",
2610 .ops
= &clkops_omap2_dflt
,
2611 .parent
= &per_32k_alwon_fck
,
2612 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2613 .enable_bit
= OMAP3430_EN_GPIO2_SHIFT
,
2614 .clkdm_name
= "per_clkdm",
2615 .recalc
= &followparent_recalc
,
2618 static struct clk wdt3_fck
= {
2620 .ops
= &clkops_omap2_dflt_wait
,
2621 .parent
= &per_32k_alwon_fck
,
2622 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2623 .enable_bit
= OMAP3430_EN_WDT3_SHIFT
,
2624 .clkdm_name
= "per_clkdm",
2625 .recalc
= &followparent_recalc
,
2628 static struct clk per_l4_ick
= {
2629 .name
= "per_l4_ick",
2630 .ops
= &clkops_null
,
2632 .clkdm_name
= "per_clkdm",
2633 .recalc
= &followparent_recalc
,
2636 static struct clk gpio6_ick
= {
2637 .name
= "gpio6_ick",
2638 .ops
= &clkops_omap2_dflt_wait
,
2639 .parent
= &per_l4_ick
,
2640 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2641 .enable_bit
= OMAP3430_EN_GPIO6_SHIFT
,
2642 .clkdm_name
= "per_clkdm",
2643 .recalc
= &followparent_recalc
,
2646 static struct clk gpio5_ick
= {
2647 .name
= "gpio5_ick",
2648 .ops
= &clkops_omap2_dflt_wait
,
2649 .parent
= &per_l4_ick
,
2650 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2651 .enable_bit
= OMAP3430_EN_GPIO5_SHIFT
,
2652 .clkdm_name
= "per_clkdm",
2653 .recalc
= &followparent_recalc
,
2656 static struct clk gpio4_ick
= {
2657 .name
= "gpio4_ick",
2658 .ops
= &clkops_omap2_dflt_wait
,
2659 .parent
= &per_l4_ick
,
2660 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2661 .enable_bit
= OMAP3430_EN_GPIO4_SHIFT
,
2662 .clkdm_name
= "per_clkdm",
2663 .recalc
= &followparent_recalc
,
2666 static struct clk gpio3_ick
= {
2667 .name
= "gpio3_ick",
2668 .ops
= &clkops_omap2_dflt_wait
,
2669 .parent
= &per_l4_ick
,
2670 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2671 .enable_bit
= OMAP3430_EN_GPIO3_SHIFT
,
2672 .clkdm_name
= "per_clkdm",
2673 .recalc
= &followparent_recalc
,
2676 static struct clk gpio2_ick
= {
2677 .name
= "gpio2_ick",
2678 .ops
= &clkops_omap2_dflt_wait
,
2679 .parent
= &per_l4_ick
,
2680 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2681 .enable_bit
= OMAP3430_EN_GPIO2_SHIFT
,
2682 .clkdm_name
= "per_clkdm",
2683 .recalc
= &followparent_recalc
,
2686 static struct clk wdt3_ick
= {
2688 .ops
= &clkops_omap2_dflt_wait
,
2689 .parent
= &per_l4_ick
,
2690 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2691 .enable_bit
= OMAP3430_EN_WDT3_SHIFT
,
2692 .clkdm_name
= "per_clkdm",
2693 .recalc
= &followparent_recalc
,
2696 static struct clk uart3_ick
= {
2697 .name
= "uart3_ick",
2698 .ops
= &clkops_omap2_dflt_wait
,
2699 .parent
= &per_l4_ick
,
2700 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2701 .enable_bit
= OMAP3430_EN_UART3_SHIFT
,
2702 .clkdm_name
= "per_clkdm",
2703 .recalc
= &followparent_recalc
,
2706 static struct clk gpt9_ick
= {
2708 .ops
= &clkops_omap2_dflt_wait
,
2709 .parent
= &per_l4_ick
,
2710 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2711 .enable_bit
= OMAP3430_EN_GPT9_SHIFT
,
2712 .clkdm_name
= "per_clkdm",
2713 .recalc
= &followparent_recalc
,
2716 static struct clk gpt8_ick
= {
2718 .ops
= &clkops_omap2_dflt_wait
,
2719 .parent
= &per_l4_ick
,
2720 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2721 .enable_bit
= OMAP3430_EN_GPT8_SHIFT
,
2722 .clkdm_name
= "per_clkdm",
2723 .recalc
= &followparent_recalc
,
2726 static struct clk gpt7_ick
= {
2728 .ops
= &clkops_omap2_dflt_wait
,
2729 .parent
= &per_l4_ick
,
2730 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2731 .enable_bit
= OMAP3430_EN_GPT7_SHIFT
,
2732 .clkdm_name
= "per_clkdm",
2733 .recalc
= &followparent_recalc
,
2736 static struct clk gpt6_ick
= {
2738 .ops
= &clkops_omap2_dflt_wait
,
2739 .parent
= &per_l4_ick
,
2740 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2741 .enable_bit
= OMAP3430_EN_GPT6_SHIFT
,
2742 .clkdm_name
= "per_clkdm",
2743 .recalc
= &followparent_recalc
,
2746 static struct clk gpt5_ick
= {
2748 .ops
= &clkops_omap2_dflt_wait
,
2749 .parent
= &per_l4_ick
,
2750 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2751 .enable_bit
= OMAP3430_EN_GPT5_SHIFT
,
2752 .clkdm_name
= "per_clkdm",
2753 .recalc
= &followparent_recalc
,
2756 static struct clk gpt4_ick
= {
2758 .ops
= &clkops_omap2_dflt_wait
,
2759 .parent
= &per_l4_ick
,
2760 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2761 .enable_bit
= OMAP3430_EN_GPT4_SHIFT
,
2762 .clkdm_name
= "per_clkdm",
2763 .recalc
= &followparent_recalc
,
2766 static struct clk gpt3_ick
= {
2768 .ops
= &clkops_omap2_dflt_wait
,
2769 .parent
= &per_l4_ick
,
2770 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2771 .enable_bit
= OMAP3430_EN_GPT3_SHIFT
,
2772 .clkdm_name
= "per_clkdm",
2773 .recalc
= &followparent_recalc
,
2776 static struct clk gpt2_ick
= {
2778 .ops
= &clkops_omap2_dflt_wait
,
2779 .parent
= &per_l4_ick
,
2780 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2781 .enable_bit
= OMAP3430_EN_GPT2_SHIFT
,
2782 .clkdm_name
= "per_clkdm",
2783 .recalc
= &followparent_recalc
,
2786 static struct clk mcbsp2_ick
= {
2787 .name
= "mcbsp2_ick",
2788 .ops
= &clkops_omap2_dflt_wait
,
2789 .parent
= &per_l4_ick
,
2790 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2791 .enable_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
2792 .clkdm_name
= "per_clkdm",
2793 .recalc
= &followparent_recalc
,
2796 static struct clk mcbsp3_ick
= {
2797 .name
= "mcbsp3_ick",
2798 .ops
= &clkops_omap2_dflt_wait
,
2799 .parent
= &per_l4_ick
,
2800 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2801 .enable_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
2802 .clkdm_name
= "per_clkdm",
2803 .recalc
= &followparent_recalc
,
2806 static struct clk mcbsp4_ick
= {
2807 .name
= "mcbsp4_ick",
2808 .ops
= &clkops_omap2_dflt_wait
,
2809 .parent
= &per_l4_ick
,
2810 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2811 .enable_bit
= OMAP3430_EN_MCBSP4_SHIFT
,
2812 .clkdm_name
= "per_clkdm",
2813 .recalc
= &followparent_recalc
,
2816 static const struct clksel mcbsp_234_clksel
[] = {
2817 { .parent
= &per_96m_fck
, .rates
= common_mcbsp_96m_rates
},
2818 { .parent
= &mcbsp_clks
, .rates
= common_mcbsp_mcbsp_rates
},
2822 static struct clk mcbsp2_fck
= {
2823 .name
= "mcbsp2_fck",
2824 .ops
= &clkops_omap2_dflt_wait
,
2825 .init
= &omap2_init_clksel_parent
,
2826 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2827 .enable_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
2828 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0
),
2829 .clksel_mask
= OMAP2_MCBSP2_CLKS_MASK
,
2830 .clksel
= mcbsp_234_clksel
,
2831 .clkdm_name
= "per_clkdm",
2832 .recalc
= &omap2_clksel_recalc
,
2835 static struct clk mcbsp3_fck
= {
2836 .name
= "mcbsp3_fck",
2837 .ops
= &clkops_omap2_dflt_wait
,
2838 .init
= &omap2_init_clksel_parent
,
2839 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2840 .enable_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
2841 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
2842 .clksel_mask
= OMAP2_MCBSP3_CLKS_MASK
,
2843 .clksel
= mcbsp_234_clksel
,
2844 .clkdm_name
= "per_clkdm",
2845 .recalc
= &omap2_clksel_recalc
,
2848 static struct clk mcbsp4_fck
= {
2849 .name
= "mcbsp4_fck",
2850 .ops
= &clkops_omap2_dflt_wait
,
2851 .init
= &omap2_init_clksel_parent
,
2852 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2853 .enable_bit
= OMAP3430_EN_MCBSP4_SHIFT
,
2854 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
2855 .clksel_mask
= OMAP2_MCBSP4_CLKS_MASK
,
2856 .clksel
= mcbsp_234_clksel
,
2857 .clkdm_name
= "per_clkdm",
2858 .recalc
= &omap2_clksel_recalc
,
2863 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2865 static const struct clksel_rate emu_src_sys_rates
[] = {
2866 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
2870 static const struct clksel_rate emu_src_core_rates
[] = {
2871 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
2875 static const struct clksel_rate emu_src_per_rates
[] = {
2876 { .div
= 1, .val
= 2, .flags
= RATE_IN_3XXX
},
2880 static const struct clksel_rate emu_src_mpu_rates
[] = {
2881 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
2885 static const struct clksel emu_src_clksel
[] = {
2886 { .parent
= &sys_ck
, .rates
= emu_src_sys_rates
},
2887 { .parent
= &emu_core_alwon_ck
, .rates
= emu_src_core_rates
},
2888 { .parent
= &emu_per_alwon_ck
, .rates
= emu_src_per_rates
},
2889 { .parent
= &emu_mpu_alwon_ck
, .rates
= emu_src_mpu_rates
},
2893 static struct clk emu_src_ck
= {
2894 .name
= "emu_src_ck",
2895 .ops
= &clkops_null
,
2896 .init
= &omap2_init_clksel_parent
,
2897 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2898 .clksel_mask
= OMAP3430_MUX_CTRL_MASK
,
2899 .clksel
= emu_src_clksel
,
2900 .clkdm_name
= "emu_clkdm",
2901 .recalc
= &omap2_clksel_recalc
,
2904 static const struct clksel_rate pclk_emu_rates
[] = {
2905 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
2906 { .div
= 3, .val
= 3, .flags
= RATE_IN_3XXX
},
2907 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
2908 { .div
= 6, .val
= 6, .flags
= RATE_IN_3XXX
},
2912 static const struct clksel pclk_emu_clksel
[] = {
2913 { .parent
= &emu_src_ck
, .rates
= pclk_emu_rates
},
2917 static struct clk pclk_fck
= {
2919 .ops
= &clkops_null
,
2920 .init
= &omap2_init_clksel_parent
,
2921 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2922 .clksel_mask
= OMAP3430_CLKSEL_PCLK_MASK
,
2923 .clksel
= pclk_emu_clksel
,
2924 .clkdm_name
= "emu_clkdm",
2925 .recalc
= &omap2_clksel_recalc
,
2928 static const struct clksel_rate pclkx2_emu_rates
[] = {
2929 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
2930 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
2931 { .div
= 3, .val
= 3, .flags
= RATE_IN_3XXX
},
2935 static const struct clksel pclkx2_emu_clksel
[] = {
2936 { .parent
= &emu_src_ck
, .rates
= pclkx2_emu_rates
},
2940 static struct clk pclkx2_fck
= {
2941 .name
= "pclkx2_fck",
2942 .ops
= &clkops_null
,
2943 .init
= &omap2_init_clksel_parent
,
2944 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2945 .clksel_mask
= OMAP3430_CLKSEL_PCLKX2_MASK
,
2946 .clksel
= pclkx2_emu_clksel
,
2947 .clkdm_name
= "emu_clkdm",
2948 .recalc
= &omap2_clksel_recalc
,
2951 static const struct clksel atclk_emu_clksel
[] = {
2952 { .parent
= &emu_src_ck
, .rates
= div2_rates
},
2956 static struct clk atclk_fck
= {
2957 .name
= "atclk_fck",
2958 .ops
= &clkops_null
,
2959 .init
= &omap2_init_clksel_parent
,
2960 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2961 .clksel_mask
= OMAP3430_CLKSEL_ATCLK_MASK
,
2962 .clksel
= atclk_emu_clksel
,
2963 .clkdm_name
= "emu_clkdm",
2964 .recalc
= &omap2_clksel_recalc
,
2967 static struct clk traceclk_src_fck
= {
2968 .name
= "traceclk_src_fck",
2969 .ops
= &clkops_null
,
2970 .init
= &omap2_init_clksel_parent
,
2971 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2972 .clksel_mask
= OMAP3430_TRACE_MUX_CTRL_MASK
,
2973 .clksel
= emu_src_clksel
,
2974 .clkdm_name
= "emu_clkdm",
2975 .recalc
= &omap2_clksel_recalc
,
2978 static const struct clksel_rate traceclk_rates
[] = {
2979 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
2980 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
2981 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
2985 static const struct clksel traceclk_clksel
[] = {
2986 { .parent
= &traceclk_src_fck
, .rates
= traceclk_rates
},
2990 static struct clk traceclk_fck
= {
2991 .name
= "traceclk_fck",
2992 .ops
= &clkops_null
,
2993 .init
= &omap2_init_clksel_parent
,
2994 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2995 .clksel_mask
= OMAP3430_CLKSEL_TRACECLK_MASK
,
2996 .clksel
= traceclk_clksel
,
2997 .clkdm_name
= "emu_clkdm",
2998 .recalc
= &omap2_clksel_recalc
,
3003 /* SmartReflex fclk (VDD1) */
3004 static struct clk sr1_fck
= {
3006 .ops
= &clkops_omap2_dflt_wait
,
3008 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
3009 .enable_bit
= OMAP3430_EN_SR1_SHIFT
,
3010 .recalc
= &followparent_recalc
,
3013 /* SmartReflex fclk (VDD2) */
3014 static struct clk sr2_fck
= {
3016 .ops
= &clkops_omap2_dflt_wait
,
3018 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
3019 .enable_bit
= OMAP3430_EN_SR2_SHIFT
,
3020 .recalc
= &followparent_recalc
,
3023 static struct clk sr_l4_ick
= {
3024 .name
= "sr_l4_ick",
3025 .ops
= &clkops_null
, /* RMK: missing? */
3027 .clkdm_name
= "core_l4_clkdm",
3028 .recalc
= &followparent_recalc
,
3031 /* SECURE_32K_FCK clocks */
3033 static struct clk gpt12_fck
= {
3034 .name
= "gpt12_fck",
3035 .ops
= &clkops_null
,
3036 .parent
= &secure_32k_fck
,
3037 .recalc
= &followparent_recalc
,
3040 static struct clk wdt1_fck
= {
3042 .ops
= &clkops_null
,
3043 .parent
= &secure_32k_fck
,
3044 .recalc
= &followparent_recalc
,
3047 /* Clocks for AM35XX */
3048 static struct clk ipss_ick
= {
3050 .ops
= &clkops_am35xx_ipss_wait
,
3051 .parent
= &core_l3_ick
,
3052 .clkdm_name
= "core_l3_clkdm",
3053 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
3054 .enable_bit
= AM35XX_EN_IPSS_SHIFT
,
3055 .recalc
= &followparent_recalc
,
3058 static struct clk emac_ick
= {
3060 .ops
= &clkops_am35xx_ipss_module_wait
,
3061 .parent
= &ipss_ick
,
3062 .clkdm_name
= "core_l3_clkdm",
3063 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3064 .enable_bit
= AM35XX_CPGMAC_VBUSP_CLK_SHIFT
,
3065 .recalc
= &followparent_recalc
,
3068 static struct clk rmii_ck
= {
3070 .ops
= &clkops_null
,
3074 static struct clk emac_fck
= {
3076 .ops
= &clkops_omap2_dflt
,
3078 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3079 .enable_bit
= AM35XX_CPGMAC_FCLK_SHIFT
,
3080 .recalc
= &followparent_recalc
,
3083 static struct clk hsotgusb_ick_am35xx
= {
3084 .name
= "hsotgusb_ick",
3085 .ops
= &clkops_am35xx_ipss_module_wait
,
3086 .parent
= &ipss_ick
,
3087 .clkdm_name
= "core_l3_clkdm",
3088 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3089 .enable_bit
= AM35XX_USBOTG_VBUSP_CLK_SHIFT
,
3090 .recalc
= &followparent_recalc
,
3093 static struct clk hsotgusb_fck_am35xx
= {
3094 .name
= "hsotgusb_fck",
3095 .ops
= &clkops_omap2_dflt
,
3097 .clkdm_name
= "core_l3_clkdm",
3098 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3099 .enable_bit
= AM35XX_USBOTG_FCLK_SHIFT
,
3100 .recalc
= &followparent_recalc
,
3103 static struct clk hecc_ck
= {
3105 .ops
= &clkops_am35xx_ipss_module_wait
,
3107 .clkdm_name
= "core_l3_clkdm",
3108 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3109 .enable_bit
= AM35XX_HECC_VBUSP_CLK_SHIFT
,
3110 .recalc
= &followparent_recalc
,
3113 static struct clk vpfe_ick
= {
3115 .ops
= &clkops_am35xx_ipss_module_wait
,
3116 .parent
= &ipss_ick
,
3117 .clkdm_name
= "core_l3_clkdm",
3118 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3119 .enable_bit
= AM35XX_VPFE_VBUSP_CLK_SHIFT
,
3120 .recalc
= &followparent_recalc
,
3123 static struct clk pclk_ck
= {
3125 .ops
= &clkops_null
,
3129 static struct clk vpfe_fck
= {
3131 .ops
= &clkops_omap2_dflt
,
3133 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3134 .enable_bit
= AM35XX_VPFE_FCLK_SHIFT
,
3135 .recalc
= &followparent_recalc
,
3139 * The UART1/2 functional clock acts as the functional
3140 * clock for UART4. No separate fclk control available.
3142 static struct clk uart4_ick_am35xx
= {
3143 .name
= "uart4_ick",
3144 .ops
= &clkops_omap2_dflt_wait
,
3145 .parent
= &core_l4_ick
,
3146 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
3147 .enable_bit
= AM35XX_EN_UART4_SHIFT
,
3148 .clkdm_name
= "core_l4_clkdm",
3149 .recalc
= &followparent_recalc
,
3152 static struct clk dummy_apb_pclk
= {
3154 .ops
= &clkops_null
,
3161 static struct omap_clk omap3xxx_clks
[] = {
3162 CLK(NULL
, "apb_pclk", &dummy_apb_pclk
, CK_3XXX
),
3163 CLK(NULL
, "omap_32k_fck", &omap_32k_fck
, CK_3XXX
),
3164 CLK(NULL
, "virt_12m_ck", &virt_12m_ck
, CK_3XXX
),
3165 CLK(NULL
, "virt_13m_ck", &virt_13m_ck
, CK_3XXX
),
3166 CLK(NULL
, "virt_16_8m_ck", &virt_16_8m_ck
, CK_3430ES2
| CK_AM35XX
),
3167 CLK(NULL
, "virt_19_2m_ck", &virt_19_2m_ck
, CK_3XXX
),
3168 CLK(NULL
, "virt_26m_ck", &virt_26m_ck
, CK_3XXX
),
3169 CLK(NULL
, "virt_38_4m_ck", &virt_38_4m_ck
, CK_3XXX
),
3170 CLK(NULL
, "osc_sys_ck", &osc_sys_ck
, CK_3XXX
),
3171 CLK(NULL
, "sys_ck", &sys_ck
, CK_3XXX
),
3172 CLK(NULL
, "sys_altclk", &sys_altclk
, CK_3XXX
),
3173 CLK(NULL
, "mcbsp_clks", &mcbsp_clks
, CK_3XXX
),
3174 CLK(NULL
, "sys_clkout1", &sys_clkout1
, CK_3XXX
),
3175 CLK(NULL
, "dpll1_ck", &dpll1_ck
, CK_3XXX
),
3176 CLK(NULL
, "dpll1_x2_ck", &dpll1_x2_ck
, CK_3XXX
),
3177 CLK(NULL
, "dpll1_x2m2_ck", &dpll1_x2m2_ck
, CK_3XXX
),
3178 CLK(NULL
, "dpll2_ck", &dpll2_ck
, CK_343X
),
3179 CLK(NULL
, "dpll2_m2_ck", &dpll2_m2_ck
, CK_343X
),
3180 CLK(NULL
, "dpll3_ck", &dpll3_ck
, CK_3XXX
),
3181 CLK(NULL
, "core_ck", &core_ck
, CK_3XXX
),
3182 CLK(NULL
, "dpll3_x2_ck", &dpll3_x2_ck
, CK_3XXX
),
3183 CLK(NULL
, "dpll3_m2_ck", &dpll3_m2_ck
, CK_3XXX
),
3184 CLK(NULL
, "dpll3_m2x2_ck", &dpll3_m2x2_ck
, CK_3XXX
),
3185 CLK(NULL
, "dpll3_m3_ck", &dpll3_m3_ck
, CK_3XXX
),
3186 CLK(NULL
, "dpll3_m3x2_ck", &dpll3_m3x2_ck
, CK_3XXX
),
3187 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck
, CK_3XXX
),
3188 CLK(NULL
, "dpll4_ck", &dpll4_ck
, CK_3XXX
),
3189 CLK(NULL
, "dpll4_x2_ck", &dpll4_x2_ck
, CK_3XXX
),
3190 CLK(NULL
, "omap_192m_alwon_fck", &omap_192m_alwon_fck
, CK_36XX
),
3191 CLK(NULL
, "omap_96m_alwon_fck", &omap_96m_alwon_fck
, CK_3XXX
),
3192 CLK(NULL
, "omap_96m_fck", &omap_96m_fck
, CK_3XXX
),
3193 CLK(NULL
, "cm_96m_fck", &cm_96m_fck
, CK_3XXX
),
3194 CLK(NULL
, "omap_54m_fck", &omap_54m_fck
, CK_3XXX
),
3195 CLK(NULL
, "omap_48m_fck", &omap_48m_fck
, CK_3XXX
),
3196 CLK(NULL
, "omap_12m_fck", &omap_12m_fck
, CK_3XXX
),
3197 CLK(NULL
, "dpll4_m2_ck", &dpll4_m2_ck
, CK_3XXX
),
3198 CLK(NULL
, "dpll4_m2x2_ck", &dpll4_m2x2_ck
, CK_3XXX
),
3199 CLK(NULL
, "dpll4_m3_ck", &dpll4_m3_ck
, CK_3XXX
),
3200 CLK(NULL
, "dpll4_m3x2_ck", &dpll4_m3x2_ck
, CK_3XXX
),
3201 CLK(NULL
, "dpll4_m4_ck", &dpll4_m4_ck
, CK_3XXX
),
3202 CLK(NULL
, "dpll4_m4x2_ck", &dpll4_m4x2_ck
, CK_3XXX
),
3203 CLK(NULL
, "dpll4_m5_ck", &dpll4_m5_ck
, CK_3XXX
),
3204 CLK(NULL
, "dpll4_m5x2_ck", &dpll4_m5x2_ck
, CK_3XXX
),
3205 CLK(NULL
, "dpll4_m6_ck", &dpll4_m6_ck
, CK_3XXX
),
3206 CLK(NULL
, "dpll4_m6x2_ck", &dpll4_m6x2_ck
, CK_3XXX
),
3207 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck
, CK_3XXX
),
3208 CLK(NULL
, "dpll5_ck", &dpll5_ck
, CK_3430ES2
| CK_AM35XX
),
3209 CLK(NULL
, "dpll5_m2_ck", &dpll5_m2_ck
, CK_3430ES2
| CK_AM35XX
),
3210 CLK(NULL
, "clkout2_src_ck", &clkout2_src_ck
, CK_3XXX
),
3211 CLK(NULL
, "sys_clkout2", &sys_clkout2
, CK_3XXX
),
3212 CLK(NULL
, "corex2_fck", &corex2_fck
, CK_3XXX
),
3213 CLK(NULL
, "dpll1_fck", &dpll1_fck
, CK_3XXX
),
3214 CLK(NULL
, "mpu_ck", &mpu_ck
, CK_3XXX
),
3215 CLK(NULL
, "arm_fck", &arm_fck
, CK_3XXX
),
3216 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck
, CK_3XXX
),
3217 CLK(NULL
, "dpll2_fck", &dpll2_fck
, CK_343X
),
3218 CLK(NULL
, "iva2_ck", &iva2_ck
, CK_343X
),
3219 CLK(NULL
, "l3_ick", &l3_ick
, CK_3XXX
),
3220 CLK(NULL
, "l4_ick", &l4_ick
, CK_3XXX
),
3221 CLK(NULL
, "rm_ick", &rm_ick
, CK_3XXX
),
3222 CLK(NULL
, "gfx_l3_ck", &gfx_l3_ck
, CK_3430ES1
),
3223 CLK(NULL
, "gfx_l3_fck", &gfx_l3_fck
, CK_3430ES1
),
3224 CLK(NULL
, "gfx_l3_ick", &gfx_l3_ick
, CK_3430ES1
),
3225 CLK(NULL
, "gfx_cg1_ck", &gfx_cg1_ck
, CK_3430ES1
),
3226 CLK(NULL
, "gfx_cg2_ck", &gfx_cg2_ck
, CK_3430ES1
),
3227 CLK(NULL
, "sgx_fck", &sgx_fck
, CK_3430ES2
| CK_3517
),
3228 CLK(NULL
, "sgx_ick", &sgx_ick
, CK_3430ES2
| CK_3517
),
3229 CLK(NULL
, "d2d_26m_fck", &d2d_26m_fck
, CK_3430ES1
),
3230 CLK(NULL
, "modem_fck", &modem_fck
, CK_343X
),
3231 CLK(NULL
, "sad2d_ick", &sad2d_ick
, CK_343X
),
3232 CLK(NULL
, "mad2d_ick", &mad2d_ick
, CK_343X
),
3233 CLK(NULL
, "gpt10_fck", &gpt10_fck
, CK_3XXX
),
3234 CLK(NULL
, "gpt11_fck", &gpt11_fck
, CK_3XXX
),
3235 CLK(NULL
, "cpefuse_fck", &cpefuse_fck
, CK_3430ES2
| CK_AM35XX
),
3236 CLK(NULL
, "ts_fck", &ts_fck
, CK_3430ES2
| CK_AM35XX
),
3237 CLK(NULL
, "usbtll_fck", &usbtll_fck
, CK_3430ES2
| CK_AM35XX
),
3238 CLK(NULL
, "core_96m_fck", &core_96m_fck
, CK_3XXX
),
3239 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck
, CK_3430ES2
| CK_AM35XX
),
3240 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck
, CK_3XXX
),
3241 CLK(NULL
, "mspro_fck", &mspro_fck
, CK_343X
),
3242 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck
, CK_3XXX
),
3243 CLK("i2c_omap.3", "fck", &i2c3_fck
, CK_3XXX
),
3244 CLK("i2c_omap.2", "fck", &i2c2_fck
, CK_3XXX
),
3245 CLK("i2c_omap.1", "fck", &i2c1_fck
, CK_3XXX
),
3246 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck
, CK_3XXX
),
3247 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck
, CK_3XXX
),
3248 CLK(NULL
, "core_48m_fck", &core_48m_fck
, CK_3XXX
),
3249 CLK("omap2_mcspi.4", "fck", &mcspi4_fck
, CK_3XXX
),
3250 CLK("omap2_mcspi.3", "fck", &mcspi3_fck
, CK_3XXX
),
3251 CLK("omap2_mcspi.2", "fck", &mcspi2_fck
, CK_3XXX
),
3252 CLK("omap2_mcspi.1", "fck", &mcspi1_fck
, CK_3XXX
),
3253 CLK(NULL
, "uart2_fck", &uart2_fck
, CK_3XXX
),
3254 CLK(NULL
, "uart1_fck", &uart1_fck
, CK_3XXX
),
3255 CLK(NULL
, "fshostusb_fck", &fshostusb_fck
, CK_3430ES1
),
3256 CLK(NULL
, "core_12m_fck", &core_12m_fck
, CK_3XXX
),
3257 CLK("omap_hdq.0", "fck", &hdq_fck
, CK_3XXX
),
3258 CLK(NULL
, "ssi_ssr_fck", &ssi_ssr_fck_3430es1
, CK_3430ES1
),
3259 CLK(NULL
, "ssi_ssr_fck", &ssi_ssr_fck_3430es2
, CK_3430ES2
),
3260 CLK(NULL
, "ssi_sst_fck", &ssi_sst_fck_3430es1
, CK_3430ES1
),
3261 CLK(NULL
, "ssi_sst_fck", &ssi_sst_fck_3430es2
, CK_3430ES2
),
3262 CLK(NULL
, "core_l3_ick", &core_l3_ick
, CK_3XXX
),
3263 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1
, CK_3430ES1
),
3264 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2
, CK_3430ES2
),
3265 CLK(NULL
, "sdrc_ick", &sdrc_ick
, CK_3XXX
),
3266 CLK(NULL
, "gpmc_fck", &gpmc_fck
, CK_3XXX
),
3267 CLK(NULL
, "security_l3_ick", &security_l3_ick
, CK_343X
),
3268 CLK(NULL
, "pka_ick", &pka_ick
, CK_343X
),
3269 CLK(NULL
, "core_l4_ick", &core_l4_ick
, CK_3XXX
),
3270 CLK(NULL
, "usbtll_ick", &usbtll_ick
, CK_3430ES2
| CK_AM35XX
),
3271 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick
, CK_3430ES2
| CK_AM35XX
),
3272 CLK(NULL
, "icr_ick", &icr_ick
, CK_343X
),
3273 CLK(NULL
, "aes2_ick", &aes2_ick
, CK_343X
),
3274 CLK("omap-sham", "ick", &sha12_ick
, CK_343X
),
3275 CLK(NULL
, "des2_ick", &des2_ick
, CK_343X
),
3276 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick
, CK_3XXX
),
3277 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick
, CK_3XXX
),
3278 CLK(NULL
, "mspro_ick", &mspro_ick
, CK_343X
),
3279 CLK("omap_hdq.0", "ick", &hdq_ick
, CK_3XXX
),
3280 CLK("omap2_mcspi.4", "ick", &mcspi4_ick
, CK_3XXX
),
3281 CLK("omap2_mcspi.3", "ick", &mcspi3_ick
, CK_3XXX
),
3282 CLK("omap2_mcspi.2", "ick", &mcspi2_ick
, CK_3XXX
),
3283 CLK("omap2_mcspi.1", "ick", &mcspi1_ick
, CK_3XXX
),
3284 CLK("i2c_omap.3", "ick", &i2c3_ick
, CK_3XXX
),
3285 CLK("i2c_omap.2", "ick", &i2c2_ick
, CK_3XXX
),
3286 CLK("i2c_omap.1", "ick", &i2c1_ick
, CK_3XXX
),
3287 CLK(NULL
, "uart2_ick", &uart2_ick
, CK_3XXX
),
3288 CLK(NULL
, "uart1_ick", &uart1_ick
, CK_3XXX
),
3289 CLK(NULL
, "gpt11_ick", &gpt11_ick
, CK_3XXX
),
3290 CLK(NULL
, "gpt10_ick", &gpt10_ick
, CK_3XXX
),
3291 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick
, CK_3XXX
),
3292 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick
, CK_3XXX
),
3293 CLK(NULL
, "fac_ick", &fac_ick
, CK_3430ES1
),
3294 CLK(NULL
, "mailboxes_ick", &mailboxes_ick
, CK_343X
),
3295 CLK(NULL
, "omapctrl_ick", &omapctrl_ick
, CK_3XXX
),
3296 CLK(NULL
, "ssi_l4_ick", &ssi_l4_ick
, CK_343X
),
3297 CLK(NULL
, "ssi_ick", &ssi_ick_3430es1
, CK_3430ES1
),
3298 CLK(NULL
, "ssi_ick", &ssi_ick_3430es2
, CK_3430ES2
),
3299 CLK(NULL
, "usb_l4_ick", &usb_l4_ick
, CK_3430ES1
),
3300 CLK(NULL
, "security_l4_ick2", &security_l4_ick2
, CK_343X
),
3301 CLK(NULL
, "aes1_ick", &aes1_ick
, CK_343X
),
3302 CLK("omap_rng", "ick", &rng_ick
, CK_343X
),
3303 CLK(NULL
, "sha11_ick", &sha11_ick
, CK_343X
),
3304 CLK(NULL
, "des1_ick", &des1_ick
, CK_343X
),
3305 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1
, CK_3430ES1
),
3306 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2
, CK_3430ES2
| CK_AM35XX
),
3307 CLK("omapdss", "tv_fck", &dss_tv_fck
, CK_3XXX
),
3308 CLK("omapdss", "video_fck", &dss_96m_fck
, CK_3XXX
),
3309 CLK("omapdss", "dss2_fck", &dss2_alwon_fck
, CK_3XXX
),
3310 CLK("omapdss", "ick", &dss_ick_3430es1
, CK_3430ES1
),
3311 CLK("omapdss", "ick", &dss_ick_3430es2
, CK_3430ES2
| CK_AM35XX
),
3312 CLK(NULL
, "cam_mclk", &cam_mclk
, CK_343X
),
3313 CLK(NULL
, "cam_ick", &cam_ick
, CK_343X
),
3314 CLK(NULL
, "csi2_96m_fck", &csi2_96m_fck
, CK_343X
),
3315 CLK(NULL
, "usbhost_120m_fck", &usbhost_120m_fck
, CK_3430ES2
| CK_AM35XX
),
3316 CLK(NULL
, "usbhost_48m_fck", &usbhost_48m_fck
, CK_3430ES2
| CK_AM35XX
),
3317 CLK(NULL
, "usbhost_ick", &usbhost_ick
, CK_3430ES2
| CK_AM35XX
),
3318 CLK(NULL
, "usim_fck", &usim_fck
, CK_3430ES2
),
3319 CLK(NULL
, "gpt1_fck", &gpt1_fck
, CK_3XXX
),
3320 CLK(NULL
, "wkup_32k_fck", &wkup_32k_fck
, CK_3XXX
),
3321 CLK(NULL
, "gpio1_dbck", &gpio1_dbck
, CK_3XXX
),
3322 CLK("omap_wdt", "fck", &wdt2_fck
, CK_3XXX
),
3323 CLK(NULL
, "wkup_l4_ick", &wkup_l4_ick
, CK_343X
),
3324 CLK(NULL
, "usim_ick", &usim_ick
, CK_3430ES2
),
3325 CLK("omap_wdt", "ick", &wdt2_ick
, CK_3XXX
),
3326 CLK(NULL
, "wdt1_ick", &wdt1_ick
, CK_3XXX
),
3327 CLK(NULL
, "gpio1_ick", &gpio1_ick
, CK_3XXX
),
3328 CLK(NULL
, "omap_32ksync_ick", &omap_32ksync_ick
, CK_3XXX
),
3329 CLK(NULL
, "gpt12_ick", &gpt12_ick
, CK_3XXX
),
3330 CLK(NULL
, "gpt1_ick", &gpt1_ick
, CK_3XXX
),
3331 CLK(NULL
, "per_96m_fck", &per_96m_fck
, CK_3XXX
),
3332 CLK(NULL
, "per_48m_fck", &per_48m_fck
, CK_3XXX
),
3333 CLK(NULL
, "uart3_fck", &uart3_fck
, CK_3XXX
),
3334 CLK(NULL
, "gpt2_fck", &gpt2_fck
, CK_3XXX
),
3335 CLK(NULL
, "gpt3_fck", &gpt3_fck
, CK_3XXX
),
3336 CLK(NULL
, "gpt4_fck", &gpt4_fck
, CK_3XXX
),
3337 CLK(NULL
, "gpt5_fck", &gpt5_fck
, CK_3XXX
),
3338 CLK(NULL
, "gpt6_fck", &gpt6_fck
, CK_3XXX
),
3339 CLK(NULL
, "gpt7_fck", &gpt7_fck
, CK_3XXX
),
3340 CLK(NULL
, "gpt8_fck", &gpt8_fck
, CK_3XXX
),
3341 CLK(NULL
, "gpt9_fck", &gpt9_fck
, CK_3XXX
),
3342 CLK(NULL
, "per_32k_alwon_fck", &per_32k_alwon_fck
, CK_3XXX
),
3343 CLK(NULL
, "gpio6_dbck", &gpio6_dbck
, CK_3XXX
),
3344 CLK(NULL
, "gpio5_dbck", &gpio5_dbck
, CK_3XXX
),
3345 CLK(NULL
, "gpio4_dbck", &gpio4_dbck
, CK_3XXX
),
3346 CLK(NULL
, "gpio3_dbck", &gpio3_dbck
, CK_3XXX
),
3347 CLK(NULL
, "gpio2_dbck", &gpio2_dbck
, CK_3XXX
),
3348 CLK(NULL
, "wdt3_fck", &wdt3_fck
, CK_3XXX
),
3349 CLK(NULL
, "per_l4_ick", &per_l4_ick
, CK_3XXX
),
3350 CLK(NULL
, "gpio6_ick", &gpio6_ick
, CK_3XXX
),
3351 CLK(NULL
, "gpio5_ick", &gpio5_ick
, CK_3XXX
),
3352 CLK(NULL
, "gpio4_ick", &gpio4_ick
, CK_3XXX
),
3353 CLK(NULL
, "gpio3_ick", &gpio3_ick
, CK_3XXX
),
3354 CLK(NULL
, "gpio2_ick", &gpio2_ick
, CK_3XXX
),
3355 CLK(NULL
, "wdt3_ick", &wdt3_ick
, CK_3XXX
),
3356 CLK(NULL
, "uart3_ick", &uart3_ick
, CK_3XXX
),
3357 CLK(NULL
, "gpt9_ick", &gpt9_ick
, CK_3XXX
),
3358 CLK(NULL
, "gpt8_ick", &gpt8_ick
, CK_3XXX
),
3359 CLK(NULL
, "gpt7_ick", &gpt7_ick
, CK_3XXX
),
3360 CLK(NULL
, "gpt6_ick", &gpt6_ick
, CK_3XXX
),
3361 CLK(NULL
, "gpt5_ick", &gpt5_ick
, CK_3XXX
),
3362 CLK(NULL
, "gpt4_ick", &gpt4_ick
, CK_3XXX
),
3363 CLK(NULL
, "gpt3_ick", &gpt3_ick
, CK_3XXX
),
3364 CLK(NULL
, "gpt2_ick", &gpt2_ick
, CK_3XXX
),
3365 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick
, CK_3XXX
),
3366 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick
, CK_3XXX
),
3367 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick
, CK_3XXX
),
3368 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck
, CK_3XXX
),
3369 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck
, CK_3XXX
),
3370 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck
, CK_3XXX
),
3371 CLK("etb", "emu_src_ck", &emu_src_ck
, CK_3XXX
),
3372 CLK(NULL
, "pclk_fck", &pclk_fck
, CK_3XXX
),
3373 CLK(NULL
, "pclkx2_fck", &pclkx2_fck
, CK_3XXX
),
3374 CLK(NULL
, "atclk_fck", &atclk_fck
, CK_3XXX
),
3375 CLK(NULL
, "traceclk_src_fck", &traceclk_src_fck
, CK_3XXX
),
3376 CLK(NULL
, "traceclk_fck", &traceclk_fck
, CK_3XXX
),
3377 CLK(NULL
, "sr1_fck", &sr1_fck
, CK_343X
),
3378 CLK(NULL
, "sr2_fck", &sr2_fck
, CK_343X
),
3379 CLK(NULL
, "sr_l4_ick", &sr_l4_ick
, CK_343X
),
3380 CLK(NULL
, "secure_32k_fck", &secure_32k_fck
, CK_3XXX
),
3381 CLK(NULL
, "gpt12_fck", &gpt12_fck
, CK_3XXX
),
3382 CLK(NULL
, "wdt1_fck", &wdt1_fck
, CK_3XXX
),
3383 CLK(NULL
, "ipss_ick", &ipss_ick
, CK_AM35XX
),
3384 CLK(NULL
, "rmii_ck", &rmii_ck
, CK_AM35XX
),
3385 CLK(NULL
, "pclk_ck", &pclk_ck
, CK_AM35XX
),
3386 CLK("davinci_emac", "emac_clk", &emac_ick
, CK_AM35XX
),
3387 CLK("davinci_emac", "phy_clk", &emac_fck
, CK_AM35XX
),
3388 CLK("vpfe-capture", "master", &vpfe_ick
, CK_AM35XX
),
3389 CLK("vpfe-capture", "slave", &vpfe_fck
, CK_AM35XX
),
3390 CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx
, CK_AM35XX
),
3391 CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx
, CK_AM35XX
),
3392 CLK(NULL
, "hecc_ck", &hecc_ck
, CK_AM35XX
),
3393 CLK(NULL
, "uart4_ick", &uart4_ick_am35xx
, CK_AM35XX
),
3397 int __init
omap3xxx_clk_init(void)
3400 u32 cpu_clkflg
= CK_3XXX
;
3402 if (cpu_is_omap3517()) {
3403 cpu_mask
= RATE_IN_3XXX
| RATE_IN_3430ES2PLUS
;
3404 cpu_clkflg
|= CK_3517
;
3405 } else if (cpu_is_omap3505()) {
3406 cpu_mask
= RATE_IN_3XXX
| RATE_IN_3430ES2PLUS
;
3407 cpu_clkflg
|= CK_3505
;
3408 } else if (cpu_is_omap34xx()) {
3409 cpu_mask
= RATE_IN_3XXX
;
3410 cpu_clkflg
|= CK_343X
;
3413 * Update this if there are further clock changes between ES2
3414 * and production parts
3416 if (omap_rev() == OMAP3430_REV_ES1_0
) {
3417 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3418 cpu_clkflg
|= CK_3430ES1
;
3420 cpu_mask
|= RATE_IN_3430ES2PLUS
;
3421 cpu_clkflg
|= CK_3430ES2
;
3425 if (omap3_has_192mhz_clk())
3426 omap_96m_alwon_fck
= omap_96m_alwon_fck_3630
;
3428 if (cpu_is_omap3630()) {
3429 cpu_mask
|= RATE_IN_36XX
;
3430 cpu_clkflg
|= CK_36XX
;
3433 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore
;
3435 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore
;
3437 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore
;
3439 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore
;
3441 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore
;
3443 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore
;
3446 if (cpu_is_omap3630())
3447 dpll4_dd
= dpll4_dd_3630
;
3449 dpll4_dd
= dpll4_dd_34xx
;
3451 clk_init(&omap2_clk_functions
);
3453 for (c
= omap3xxx_clks
; c
< omap3xxx_clks
+ ARRAY_SIZE(omap3xxx_clks
);
3455 clk_preinit(c
->lk
.clk
);
3457 for (c
= omap3xxx_clks
; c
< omap3xxx_clks
+ ARRAY_SIZE(omap3xxx_clks
);
3459 if (c
->cpu
& cpu_clkflg
) {
3461 clk_register(c
->lk
.clk
);
3462 omap2_init_clk_clkdm(c
->lk
.clk
);
3465 recalculate_root_clocks();
3467 printk(KERN_INFO
"Clocking rate (Crystal/Core/MPU): "
3468 "%ld.%01ld/%ld/%ld MHz\n",
3469 (osc_sys_ck
.rate
/ 1000000), (osc_sys_ck
.rate
/ 100000) % 10,
3470 (core_ck
.rate
/ 1000000), (arm_fck
.rate
/ 1000000));
3473 * Only enable those clocks we will need, let the drivers
3474 * enable other clocks as necessary
3476 clk_enable_init_clocks();
3479 * Lock DPLL5 and put it in autoidle.
3481 if (omap_rev() >= OMAP3430_REV_ES2_0
)
3482 omap3_clk_lock_dpll5();
3484 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3485 sdrc_ick_p
= clk_get(NULL
, "sdrc_ick");
3486 arm_fck_p
= clk_get(NULL
, "arm_fck");