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[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / arm / mach-omap1 / mcbsp.c
blobb4da5f1fda9b3a93cb6d8b162962c6ff8bd705d6
1 /*
2 * linux/arch/arm/mach-omap1/mcbsp.c
4 * Copyright (C) 2008 Instituto Nokia de Tecnologia
5 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Multichannel mode not supported.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
21 #include <mach/irqs.h>
22 #include <plat/dma.h>
23 #include <plat/mux.h>
24 #include <plat/cpu.h>
25 #include <plat/mcbsp.h>
27 #define DPS_RSTCT2_PER_EN (1 << 0)
28 #define DSP_RSTCT2_WD_PER_EN (1 << 1)
30 static int dsp_use;
31 static struct clk *api_clk;
32 static struct clk *dsp_clk;
34 static void omap1_mcbsp_request(unsigned int id)
37 * On 1510, 1610 and 1710, McBSP1 and McBSP3
38 * are DSP public peripherals.
40 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
41 if (dsp_use++ == 0) {
42 api_clk = clk_get(NULL, "api_ck");
43 dsp_clk = clk_get(NULL, "dsp_ck");
44 if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {
45 clk_enable(api_clk);
46 clk_enable(dsp_clk);
48 __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
49 DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
55 static void omap1_mcbsp_free(unsigned int id)
57 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
58 if (--dsp_use == 0) {
59 if (!IS_ERR(api_clk)) {
60 clk_disable(api_clk);
61 clk_put(api_clk);
63 if (!IS_ERR(dsp_clk)) {
64 clk_disable(dsp_clk);
65 clk_put(dsp_clk);
71 static struct omap_mcbsp_ops omap1_mcbsp_ops = {
72 .request = omap1_mcbsp_request,
73 .free = omap1_mcbsp_free,
76 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
77 static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
79 .phys_base = OMAP7XX_MCBSP1_BASE,
80 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
81 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
82 .rx_irq = INT_7XX_McBSP1RX,
83 .tx_irq = INT_7XX_McBSP1TX,
84 .ops = &omap1_mcbsp_ops,
87 .phys_base = OMAP7XX_MCBSP2_BASE,
88 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
89 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
90 .rx_irq = INT_7XX_McBSP2RX,
91 .tx_irq = INT_7XX_McBSP2TX,
92 .ops = &omap1_mcbsp_ops,
95 #define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata)
96 #define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
97 #else
98 #define omap7xx_mcbsp_pdata NULL
99 #define OMAP7XX_MCBSP_PDATA_SZ 0
100 #define OMAP7XX_MCBSP_REG_NUM 0
101 #endif
103 #ifdef CONFIG_ARCH_OMAP15XX
104 static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
106 .phys_base = OMAP1510_MCBSP1_BASE,
107 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
108 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
109 .rx_irq = INT_McBSP1RX,
110 .tx_irq = INT_McBSP1TX,
111 .ops = &omap1_mcbsp_ops,
114 .phys_base = OMAP1510_MCBSP2_BASE,
115 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
116 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
117 .rx_irq = INT_1510_SPI_RX,
118 .tx_irq = INT_1510_SPI_TX,
119 .ops = &omap1_mcbsp_ops,
122 .phys_base = OMAP1510_MCBSP3_BASE,
123 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
124 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
125 .rx_irq = INT_McBSP3RX,
126 .tx_irq = INT_McBSP3TX,
127 .ops = &omap1_mcbsp_ops,
130 #define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata)
131 #define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
132 #else
133 #define omap15xx_mcbsp_pdata NULL
134 #define OMAP15XX_MCBSP_PDATA_SZ 0
135 #define OMAP15XX_MCBSP_REG_NUM 0
136 #endif
138 #ifdef CONFIG_ARCH_OMAP16XX
139 static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
141 .phys_base = OMAP1610_MCBSP1_BASE,
142 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
143 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
144 .rx_irq = INT_McBSP1RX,
145 .tx_irq = INT_McBSP1TX,
146 .ops = &omap1_mcbsp_ops,
149 .phys_base = OMAP1610_MCBSP2_BASE,
150 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
151 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
152 .rx_irq = INT_1610_McBSP2_RX,
153 .tx_irq = INT_1610_McBSP2_TX,
154 .ops = &omap1_mcbsp_ops,
157 .phys_base = OMAP1610_MCBSP3_BASE,
158 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
159 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
160 .rx_irq = INT_McBSP3RX,
161 .tx_irq = INT_McBSP3TX,
162 .ops = &omap1_mcbsp_ops,
165 #define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata)
166 #define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
167 #else
168 #define omap16xx_mcbsp_pdata NULL
169 #define OMAP16XX_MCBSP_PDATA_SZ 0
170 #define OMAP16XX_MCBSP_REG_NUM 0
171 #endif
173 int __init omap1_mcbsp_init(void)
175 if (cpu_is_omap7xx()) {
176 omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
177 omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16);
178 } else if (cpu_is_omap15xx()) {
179 omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
180 omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16);
181 } else if (cpu_is_omap16xx()) {
182 omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
183 omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16);
186 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
187 GFP_KERNEL);
188 if (!mcbsp_ptr)
189 return -ENOMEM;
191 if (cpu_is_omap7xx())
192 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata,
193 OMAP7XX_MCBSP_PDATA_SZ);
195 if (cpu_is_omap15xx())
196 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
197 OMAP15XX_MCBSP_PDATA_SZ);
199 if (cpu_is_omap16xx())
200 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
201 OMAP16XX_MCBSP_PDATA_SZ);
203 return omap_mcbsp_init();
206 arch_initcall(omap1_mcbsp_init);