release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-mx5/board-cpuimx51.c

   1 /*
   2  *
   3  * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
   4  *
   5  * based on board-mx51_babbage.c which is
   6  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
   7  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/i2c.h>
  21 #include <linux/gpio.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/fsl_devices.h>
  27
  28 #include <mach/eukrea-baseboards.h>
  29 #include <mach/common.h>
  30 #include <mach/hardware.h>
  31 #include <mach/imx-uart.h>
  32 #include <mach/iomux-mx51.h>
  33 #include <mach/i2c.h>
  34 #include <mach/mxc_ehci.h>
  35
  36 #include <asm/irq.h>
  37 #include <asm/setup.h>
  38 #include <asm/mach-types.h>
  39 #include <asm/mach/arch.h>
  40 #include <asm/mach/time.h>
  41
  42 #include "devices.h"
  43
  44 #define CPUIMX51_USBH1_STP      (0*32 + 27)
  45 #define CPUIMX51_QUARTA_GPIO    (2*32 + 28)
  46 #define CPUIMX51_QUARTB_GPIO    (2*32 + 25)
  47 #define CPUIMX51_QUARTC_GPIO    (2*32 + 26)
  48 #define CPUIMX51_QUARTD_GPIO    (2*32 + 27)
  49 #define CPUIMX51_QUARTA_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
  50 #define CPUIMX51_QUARTB_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
  51 #define CPUIMX51_QUARTC_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
  52 #define CPUIMX51_QUARTD_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO)
  53 #define CPUIMX51_QUART_XTAL     14745600
  54 #define CPUIMX51_QUART_REGSHIFT 17
  55
  56 /* USB_CTRL_1 */
  57 #define MX51_USB_CTRL_1_OFFSET          0x10
  58 #define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
  59
  60 #define MX51_USB_PLLDIV_12_MHZ          0x00
  61 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  62 #define MX51_USB_PLL_DIV_24_MHZ         0x02
  63
  64 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
  65 static struct plat_serial8250_port serial_platform_data[] = {
  66         {
  67                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
  68                 .irq = CPUIMX51_QUARTA_IRQ,
  69                 .irqflags = IRQF_TRIGGER_HIGH,
  70                 .uartclk = CPUIMX51_QUART_XTAL,
  71                 .regshift = CPUIMX51_QUART_REGSHIFT,
  72                 .iotype = UPIO_MEM,
  73                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  74         }, {
  75                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
  76                 .irq = CPUIMX51_QUARTB_IRQ,
  77                 .irqflags = IRQF_TRIGGER_HIGH,
  78                 .uartclk = CPUIMX51_QUART_XTAL,
  79                 .regshift = CPUIMX51_QUART_REGSHIFT,
  80                 .iotype = UPIO_MEM,
  81                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  82         }, {
  83                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
  84                 .irq = CPUIMX51_QUARTC_IRQ,
  85                 .irqflags = IRQF_TRIGGER_HIGH,
  86                 .uartclk = CPUIMX51_QUART_XTAL,
  87                 .regshift = CPUIMX51_QUART_REGSHIFT,
  88                 .iotype = UPIO_MEM,
  89                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  90         }, {
  91                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
  92                 .irq = CPUIMX51_QUARTD_IRQ,
  93                 .irqflags = IRQF_TRIGGER_HIGH,
  94                 .uartclk = CPUIMX51_QUART_XTAL,
  95                 .regshift = CPUIMX51_QUART_REGSHIFT,
  96                 .iotype = UPIO_MEM,
  97                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  98         }, {
  99         }
 100 };
 101
 102 static struct platform_device serial_device = {
 103         .name = "serial8250",
 104         .id = 0,
 105         .dev = {
 106                 .platform_data = serial_platform_data,
 107         },
 108 };
 109 #endif
 110
 111 static struct platform_device *devices[] __initdata = {
 112         &mxc_fec_device,
 113 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
 114         &serial_device,
 115 #endif
 116 };
 117
 118 static struct pad_desc eukrea_cpuimx51_pads[] = {
 119         /* UART1 */
 120         MX51_PAD_UART1_RXD__UART1_RXD,
 121         MX51_PAD_UART1_TXD__UART1_TXD,
 122         MX51_PAD_UART1_RTS__UART1_RTS,
 123         MX51_PAD_UART1_CTS__UART1_CTS,
 124
 125         /* I2C2 */
 126         MX51_PAD_GPIO_1_2__I2C2_SCL,
 127         MX51_PAD_GPIO_1_3__I2C2_SDA,
 128         MX51_PAD_NANDF_D10__GPIO_3_30,
 129
 130         /* QUART IRQ */
 131         MX51_PAD_NANDF_D15__GPIO_3_25,
 132         MX51_PAD_NANDF_D14__GPIO_3_26,
 133         MX51_PAD_NANDF_D13__GPIO_3_27,
 134         MX51_PAD_NANDF_D12__GPIO_3_28,
 135
 136         /* USB HOST1 */
 137         MX51_PAD_USBH1_CLK__USBH1_CLK,
 138         MX51_PAD_USBH1_DIR__USBH1_DIR,
 139         MX51_PAD_USBH1_NXT__USBH1_NXT,
 140         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
 141         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
 142         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
 143         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
 144         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
 145         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
 146         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
 147         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 148         MX51_PAD_USBH1_STP__USBH1_STP,
 149 };
 150
 151 static struct imxuart_platform_data uart_pdata = {
 152         .flags = IMXUART_HAVE_RTSCTS,
 153 };
 154
 155 static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = {
 156         .bitrate = 100000,
 157 };
 158
 159 static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
 160         {
 161                 I2C_BOARD_INFO("pcf8563", 0x51),
 162         },
 163 };
 164
 165 /* This function is board specific as the bit mask for the plldiv will also
 166 be different for other Freescale SoCs, thus a common bitmask is not
 167 possible and cannot get place in /plat-mxc/ehci.c.*/
 168 static int initialize_otg_port(struct platform_device *pdev)
 169 {
 170         u32 v;
 171         void __iomem *usb_base;
 172         void __iomem *usbother_base;
 173
 174         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 175         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 176
 177         /* Set the PHY clock to 19.2MHz */
 178         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 179         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 180         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 181         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 182         iounmap(usb_base);
 183         return 0;
 184 }
 185
 186 static int initialize_usbh1_port(struct platform_device *pdev)
 187 {
 188         u32 v;
 189         void __iomem *usb_base;
 190         void __iomem *usbother_base;
 191
 192         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 193         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 194
 195         /* The clock for the USBH1 ULPI port will come externally from the PHY. */
 196         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 197         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
 198         iounmap(usb_base);
 199         return 0;
 200 }
 201
 202 static struct mxc_usbh_platform_data dr_utmi_config = {
 203         .init           = initialize_otg_port,
 204         .portsc = MXC_EHCI_UTMI_16BIT,
 205         .flags  = MXC_EHCI_INTERNAL_PHY,
 206 };
 207
 208 static struct fsl_usb2_platform_data usb_pdata = {
 209         .operating_mode = FSL_USB2_DR_DEVICE,
 210         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 211 };
 212
 213 static struct mxc_usbh_platform_data usbh1_config = {
 214         .init           = initialize_usbh1_port,
 215         .portsc = MXC_EHCI_MODE_ULPI,
 216         .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
 217 };
 218
 219 static int otg_mode_host;
 220
 221 static int __init eukrea_cpuimx51_otg_mode(char *options)
 222 {
 223         if (!strcmp(options, "host"))
 224                 otg_mode_host = 1;
 225         else if (!strcmp(options, "device"))
 226                 otg_mode_host = 0;
 227         else
 228                 pr_info("otg_mode neither \"host\" nor \"device\". "
 229                         "Defaulting to device\n");
 230         return 0;
 231 }
 232 __setup("otg_mode=", eukrea_cpuimx51_otg_mode);
 233
 234 /*
 235  * Board specific initialization.
 236  */
 237 static void __init eukrea_cpuimx51_init(void)
 238 {
 239         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
 240                                         ARRAY_SIZE(eukrea_cpuimx51_pads));
 241
 242         mxc_register_device(&mxc_uart_device0, &uart_pdata);
 243         gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
 244         gpio_direction_input(CPUIMX51_QUARTA_GPIO);
 245         gpio_free(CPUIMX51_QUARTA_GPIO);
 246         gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
 247         gpio_direction_input(CPUIMX51_QUARTB_GPIO);
 248         gpio_free(CPUIMX51_QUARTB_GPIO);
 249         gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
 250         gpio_direction_input(CPUIMX51_QUARTC_GPIO);
 251         gpio_free(CPUIMX51_QUARTC_GPIO);
 252         gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
 253         gpio_direction_input(CPUIMX51_QUARTD_GPIO);
 254         gpio_free(CPUIMX51_QUARTD_GPIO);
 255
 256         platform_add_devices(devices, ARRAY_SIZE(devices));
 257
 258         mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data);
 259         i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
 260                                 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
 261
 262         if (otg_mode_host)
 263                 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
 264         else {
 265                 initialize_otg_port(NULL);
 266                 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
 267         }
 268         mxc_register_device(&mxc_usbh1_device, &usbh1_config);
 269
 270 #ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
 271         eukrea_mbimx51_baseboard_init();
 272 #endif
 273 }
 274
 275 static void __init eukrea_cpuimx51_timer_init(void)
 276 {
 277         mx51_clocks_init(32768, 24000000, 22579200, 0);
 278 }
 279
 280 static struct sys_timer mxc_timer = {
 281         .init   = eukrea_cpuimx51_timer_init,
 282 };
 283
 284 MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
 285         /* Maintainer: Eric Bénard <eric@eukrea.com> */
 286         .phys_io = MX51_AIPS1_BASE_ADDR,
 287         .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
 288         .boot_params = PHYS_OFFSET + 0x100,
 289         .map_io = mx51_map_io,
 290         .init_irq = mx51_init_irq,
 291         .init_machine = eukrea_cpuimx51_init,
 292         .timer = &mxc_timer,
 293 MACHINE_END