release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-msm/devices-msm7x30.c

   1 /*
   2  * Copyright (C) 2008 Google, Inc.
   3  * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18
  19 #include <linux/dma-mapping.h>
  20 #include <mach/irqs.h>
  21 #include <mach/msm_iomap.h>
  22 #include <mach/dma.h>
  23 #include <mach/board.h>
  24
  25 #include "devices.h"
  26 #include "smd_private.h"
  27
  28 #include <asm/mach/flash.h>
  29
  30 #include "clock-pcom.h"
  31
  32 #include <mach/mmc.h>
  33
  34 static struct resource resources_uart2[] = {
  35         {
  36                 .start  = INT_UART2,
  37                 .end    = INT_UART2,
  38                 .flags  = IORESOURCE_IRQ,
  39         },
  40         {
  41                 .start  = MSM_UART2_PHYS,
  42                 .end    = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
  43                 .flags  = IORESOURCE_MEM,
  44         },
  45 };
  46
  47 struct platform_device msm_device_uart2 = {
  48         .name   = "msm_serial",
  49         .id     = 1,
  50         .num_resources  = ARRAY_SIZE(resources_uart2),
  51         .resource       = resources_uart2,
  52 };
  53
  54 struct clk msm_clocks_7x30[] = {
  55         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
  56         CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
  57         CLK_PCOM("cam_m_clk",   CAM_M_CLK,      NULL, 0),
  58         CLK_PCOM("camif_pad_pclk",      CAMIF_PAD_P_CLK,        NULL, OFF),
  59         CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
  60         CLK_PCOM("ecodec_clk",  ECODEC_CLK,     NULL, 0),
  61         CLK_PCOM("emdh_clk",    EMDH_CLK,       NULL, OFF | CLK_MINMAX),
  62         CLK_PCOM("emdh_pclk",   EMDH_P_CLK,     NULL, OFF),
  63         CLK_PCOM("gp_clk",      GP_CLK,         NULL, 0),
  64         CLK_PCOM("grp_2d_clk",  GRP_2D_CLK,     NULL, 0),
  65         CLK_PCOM("grp_2d_pclk", GRP_2D_P_CLK,   NULL, 0),
  66         CLK_PCOM("grp_clk",     GRP_3D_CLK,     NULL, 0),
  67         CLK_PCOM("grp_pclk",    GRP_3D_P_CLK,   NULL, 0),
  68         CLK_7X30S("grp_src_clk", GRP_3D_SRC_CLK, GRP_3D_CLK,    NULL, 0),
  69         CLK_PCOM("hdmi_clk",    HDMI_CLK,       NULL, 0),
  70         CLK_PCOM("imem_clk",    IMEM_CLK,       NULL, OFF),
  71         CLK_PCOM("jpeg_clk",    JPEG_CLK,       NULL, OFF),
  72         CLK_PCOM("jpeg_pclk",   JPEG_P_CLK,     NULL, OFF),
  73         CLK_PCOM("lpa_codec_clk",       LPA_CODEC_CLK,          NULL, 0),
  74         CLK_PCOM("lpa_core_clk",        LPA_CORE_CLK,           NULL, 0),
  75         CLK_PCOM("lpa_pclk",            LPA_P_CLK,              NULL, 0),
  76         CLK_PCOM("mdc_clk",     MDC_CLK,        NULL, 0),
  77         CLK_PCOM("mddi_clk",    PMDH_CLK,       NULL, OFF | CLK_MINMAX),
  78         CLK_PCOM("mddi_pclk",   PMDH_P_CLK,     NULL, 0),
  79         CLK_PCOM("mdp_clk",     MDP_CLK,        NULL, OFF),
  80         CLK_PCOM("mdp_pclk",    MDP_P_CLK,      NULL, 0),
  81         CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
  82         CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
  83         CLK_PCOM("mdp_vsync_clk",       MDP_VSYNC_CLK,  NULL, 0),
  84         CLK_PCOM("mfc_clk",             MFC_CLK,                NULL, 0),
  85         CLK_PCOM("mfc_div2_clk",        MFC_DIV2_CLK,           NULL, 0),
  86         CLK_PCOM("mfc_pclk",            MFC_P_CLK,              NULL, 0),
  87         CLK_PCOM("mi2s_m_clk",          MI2S_M_CLK,             NULL, 0),
  88         CLK_PCOM("mi2s_s_clk",          MI2S_S_CLK,             NULL, 0),
  89         CLK_PCOM("mi2s_codec_rx_m_clk", MI2S_CODEC_RX_M_CLK,  NULL, 0),
  90         CLK_PCOM("mi2s_codec_rx_s_clk", MI2S_CODEC_RX_S_CLK,  NULL, 0),
  91         CLK_PCOM("mi2s_codec_tx_m_clk", MI2S_CODEC_TX_M_CLK,  NULL, 0),
  92         CLK_PCOM("mi2s_codec_tx_s_clk", MI2S_CODEC_TX_S_CLK,  NULL, 0),
  93         CLK_PCOM("pbus_clk",    PBUS_CLK,       NULL, CLK_MIN),
  94         CLK_PCOM("pcm_clk",     PCM_CLK,        NULL, 0),
  95         CLK_PCOM("rotator_clk", AXI_ROTATOR_CLK,                NULL, 0),
  96         CLK_PCOM("rotator_imem_clk",    ROTATOR_IMEM_CLK,       NULL, OFF),
  97         CLK_PCOM("rotator_pclk",        ROTATOR_P_CLK,          NULL, OFF),
  98         CLK_PCOM("sdac_clk",    SDAC_CLK,       NULL, OFF),
  99         CLK_PCOM("spi_clk",     SPI_CLK,        NULL, 0),
 100         CLK_PCOM("spi_pclk",    SPI_P_CLK,      NULL, 0),
 101         CLK_7X30S("tv_src_clk", TV_CLK,         TV_ENC_CLK,     NULL, 0),
 102         CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
 103         CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
 104         CLK_PCOM("uart_clk",    UART2_CLK,      &msm_device_uart2.dev, 0),
 105         CLK_PCOM("usb_hs_clk",          USB_HS_CLK,             NULL, OFF),
 106         CLK_PCOM("usb_hs_pclk",         USB_HS_P_CLK,           NULL, OFF),
 107         CLK_PCOM("usb_hs_core_clk",     USB_HS_CORE_CLK,        NULL, OFF),
 108         CLK_PCOM("usb_hs2_clk",         USB_HS2_CLK,            NULL, OFF),
 109         CLK_PCOM("usb_hs2_pclk",        USB_HS2_P_CLK,          NULL, OFF),
 110         CLK_PCOM("usb_hs2_core_clk",    USB_HS2_CORE_CLK,       NULL, OFF),
 111         CLK_PCOM("usb_hs3_clk",         USB_HS3_CLK,            NULL, OFF),
 112         CLK_PCOM("usb_hs3_pclk",        USB_HS3_P_CLK,          NULL, OFF),
 113         CLK_PCOM("usb_hs3_core_clk",    USB_HS3_CORE_CLK,       NULL, OFF),
 114         CLK_PCOM("vdc_clk",     VDC_CLK,        NULL, OFF | CLK_MIN),
 115         CLK_PCOM("vfe_camif_clk",       VFE_CAMIF_CLK,  NULL, 0),
 116         CLK_PCOM("vfe_clk",     VFE_CLK,        NULL, 0),
 117         CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK,    NULL, 0),
 118         CLK_PCOM("vfe_pclk",    VFE_P_CLK,      NULL, OFF),
 119         CLK_PCOM("vpe_clk",     VPE_CLK,        NULL, 0),
 120
 121         /* 7x30 v2 hardware only. */
 122         CLK_PCOM("csi_clk",     CSI0_CLK,       NULL, 0),
 123         CLK_PCOM("csi_pclk",    CSI0_P_CLK,     NULL, 0),
 124         CLK_PCOM("csi_vfe_clk", CSI0_VFE_CLK,   NULL, 0),
 125 };
 126
 127 unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30);