release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-lpc32xx/timer.c

   1 /*
   2  * arch/arm/mach-lpc32xx/timer.c
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2009 - 2010 NXP Semiconductors
   7  * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
   8  *                    Ed Schouten <e.schouten@fontys.nl>
   9  *                    Laurens Timmermans <l.timmermans@fontys.nl>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/time.h>
  25 #include <linux/err.h>
  26 #include <linux/clockchips.h>
  27
  28 #include <asm/mach/time.h>
  29
  30 #include <mach/hardware.h>
  31 #include <mach/platform.h>
  32 #include "common.h"
  33
  34 static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
  35 {
  36         return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE));
  37 }
  38
  39 static struct clocksource lpc32xx_clksrc = {
  40         .name   = "lpc32xx_clksrc",
  41         .shift  = 24,
  42         .rating = 300,
  43         .read   = lpc32xx_clksrc_read,
  44         .mask   = CLOCKSOURCE_MASK(32),
  45         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
  46 };
  47
  48 static int lpc32xx_clkevt_next_event(unsigned long delta,
  49     struct clock_event_device *dev)
  50 {
  51         __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
  52                 LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
  53         __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
  54         __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
  55                 LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
  56
  57         return 0;
  58 }
  59
  60 static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
  61     struct clock_event_device *dev)
  62 {
  63         switch (mode) {
  64         case CLOCK_EVT_MODE_PERIODIC:
  65                 WARN_ON(1);
  66                 break;
  67
  68         case CLOCK_EVT_MODE_ONESHOT:
  69         case CLOCK_EVT_MODE_SHUTDOWN:
  70                 /*
  71                  * Disable the timer. When using oneshot, we must also
  72                  * disable the timer to wait for the first call to
  73                  * set_next_event().
  74                  */
  75                 __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
  76                 break;
  77
  78         case CLOCK_EVT_MODE_UNUSED:
  79         case CLOCK_EVT_MODE_RESUME:
  80                 break;
  81         }
  82 }
  83
  84 static struct clock_event_device lpc32xx_clkevt = {
  85         .name           = "lpc32xx_clkevt",
  86         .features       = CLOCK_EVT_FEAT_ONESHOT,
  87         .shift          = 32,
  88         .rating         = 300,
  89         .set_next_event = lpc32xx_clkevt_next_event,
  90         .set_mode       = lpc32xx_clkevt_mode,
  91 };
  92
  93 static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
  94 {
  95         struct clock_event_device *evt = &lpc32xx_clkevt;
  96
  97         /* Clear match */
  98         __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
  99                 LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
 100
 101         evt->event_handler(evt);
 102
 103         return IRQ_HANDLED;
 104 }
 105
 106 static struct irqaction lpc32xx_timer_irq = {
 107         .name           = "LPC32XX Timer Tick",
 108         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 109         .handler        = lpc32xx_timer_interrupt,
 110 };
 111
 112 /*
 113  * The clock management driver isn't initialized at this point, so the
 114  * clocks need to be enabled here manually and then tagged as used in
 115  * the clock driver initialization
 116  */
 117 static void __init lpc32xx_timer_init(void)
 118 {
 119         u32 clkrate, pllreg;
 120
 121         /* Enable timer clock */
 122         __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
 123                 LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
 124                 LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
 125
 126         /*
 127          * The clock driver isn't initialized at this point. So determine if
 128          * the SYSCLK is driven from the PLL397 or main oscillator and then use
 129          * it to compute the PLL frequency and the PCLK divider to get the base
 130          * timer rates. This rate is needed to compute the tick rate.
 131          */
 132         if (clk_is_sysclk_mainosc() != 0)
 133                 clkrate = LPC32XX_MAIN_OSC_FREQ;
 134         else
 135                 clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
 136
 137         /* Get ARM HCLKPLL register and convert it into a frequency */
 138         pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
 139         clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
 140
 141         /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
 142         clkrate = clkrate / clk_get_pclk_div();
 143
 144         /* Initial timer setup */
 145         __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
 146         __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
 147                 LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
 148         __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
 149         __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
 150                 LCP32XX_TIMER_CNTR_MCR_STOP(0) |
 151                 LCP32XX_TIMER_CNTR_MCR_RESET(0),
 152                 LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
 153
 154         /* Setup tick interrupt */
 155         setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
 156
 157         /* Setup the clockevent structure. */
 158         lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC,
 159                 lpc32xx_clkevt.shift);
 160         lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1,
 161                 &lpc32xx_clkevt);
 162         lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1,
 163                 &lpc32xx_clkevt) + 1;
 164         lpc32xx_clkevt.cpumask = cpumask_of(0);
 165         clockevents_register_device(&lpc32xx_clkevt);
 166
 167         /* Use timer1 as clock source. */
 168         __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
 169                 LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
 170         __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
 171         __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
 172         __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
 173                 LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
 174         lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate,
 175                 lpc32xx_clksrc.shift);
 176         clocksource_register(&lpc32xx_clksrc);
 177 }
 178
 179 struct sys_timer lpc32xx_timer = {
 180         .init           = &lpc32xx_timer_init,
 181 };