release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-iop13xx/iq81340sc.c

   1 /*
   2  * iq81340sc board support
   3  * Copyright (c) 2005-2006, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16  * Place - Suite 330, Boston, MA 02111-1307 USA.
  17  *
  18  */
  19 #include <linux/pci.h>
  20
  21 #include <mach/hardware.h>
  22 #include <asm/irq.h>
  23 #include <asm/mach/pci.h>
  24 #include <asm/mach-types.h>
  25 #include <asm/mach/arch.h>
  26 #include <mach/pci.h>
  27 #include <asm/mach/time.h>
  28 #include <mach/time.h>
  29
  30 extern int init_atu;
  31
  32 static int __init
  33 iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
  34 {
  35         WARN_ON(idsel < 1 || idsel > 2);
  36
  37         switch (idsel) {
  38         case 1:
  39                 switch (pin) {
  40                 case 1: return ATUX_INTB;
  41                 case 2: return ATUX_INTC;
  42                 case 3: return ATUX_INTD;
  43                 case 4: return ATUX_INTA;
  44                 default: return -1;
  45                 }
  46         case 2:
  47                 switch (pin) {
  48                 case 1: return ATUX_INTC;
  49                 case 2: return ATUX_INTC;
  50                 case 3: return ATUX_INTC;
  51                 case 4: return ATUX_INTC;
  52                 default: return -1;
  53                 }
  54         default: return -1;
  55         }
  56 }
  57
  58 static struct hw_pci iq81340sc_pci __initdata = {
  59         .swizzle        = pci_std_swizzle,
  60         .nr_controllers = 0,
  61         .setup          = iop13xx_pci_setup,
  62         .scan           = iop13xx_scan_bus,
  63         .map_irq        = iq81340sc_atux_map_irq,
  64         .preinit        = iop13xx_pci_init
  65 };
  66
  67 static int __init iq81340sc_pci_init(void)
  68 {
  69         iop13xx_atu_select(&iq81340sc_pci);
  70         pci_common_init(&iq81340sc_pci);
  71         iop13xx_map_pci_memory();
  72
  73         return 0;
  74 }
  75
  76 static void __init iq81340sc_init(void)
  77 {
  78         iop13xx_platform_init();
  79         iq81340sc_pci_init();
  80         iop13xx_add_tpmi_devices();
  81 }
  82
  83 static void __init iq81340sc_timer_init(void)
  84 {
  85         unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
  86         printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq);
  87         iop_init_time(bus_freq);
  88 }
  89
  90 static struct sys_timer iq81340sc_timer = {
  91        .init       = iq81340sc_timer_init,
  92 };
  93
  94 MACHINE_START(IQ81340SC, "Intel IQ81340SC")
  95         /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
  96         .phys_io        = IOP13XX_PMMR_PHYS_MEM_BASE,
  97         .io_pg_offst    = (IOP13XX_PMMR_VIRT_MEM_BASE >> 18) & 0xfffc,
  98         .boot_params    = 0x00000100,
  99         .map_io         = iop13xx_map_io,
 100         .init_irq       = iop13xx_init_irq,
 101         .timer          = &iq81340sc_timer,
 102         .init_machine   = iq81340sc_init,
 103 MACHINE_END