release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-davinci/dm355.c

   1 /*
   2  * TI DaVinci DM355 chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/clk.h>
  13 #include <linux/serial_8250.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/gpio.h>
  17
  18 #include <linux/spi/spi.h>
  19
  20 #include <asm/mach/map.h>
  21
  22 #include <mach/dm355.h>
  23 #include <mach/cputype.h>
  24 #include <mach/edma.h>
  25 #include <mach/psc.h>
  26 #include <mach/mux.h>
  27 #include <mach/irqs.h>
  28 #include <mach/time.h>
  29 #include <mach/serial.h>
  30 #include <mach/common.h>
  31 #include <mach/asp.h>
  32 #include <mach/spi.h>
  33
  34 #include "clock.h"
  35 #include "mux.h"
  36
  37 #define DM355_UART2_BASE        (IO_PHYS + 0x206000)
  38
  39 /*
  40  * Device specific clocks
  41  */
  42 #define DM355_REF_FREQ          24000000        /* 24 or 36 MHz */
  43
  44 static struct pll_data pll1_data = {
  45         .num       = 1,
  46         .phys_base = DAVINCI_PLL1_BASE,
  47         .flags     = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
  48 };
  49
  50 static struct pll_data pll2_data = {
  51         .num       = 2,
  52         .phys_base = DAVINCI_PLL2_BASE,
  53         .flags     = PLL_HAS_PREDIV,
  54 };
  55
  56 static struct clk ref_clk = {
  57         .name = "ref_clk",
  58         .rate = DM355_REF_FREQ,
  59 };
  60
  61 static struct clk pll1_clk = {
  62         .name = "pll1",
  63         .parent = &ref_clk,
  64         .flags = CLK_PLL,
  65         .pll_data = &pll1_data,
  66 };
  67
  68 static struct clk pll1_aux_clk = {
  69         .name = "pll1_aux_clk",
  70         .parent = &pll1_clk,
  71         .flags = CLK_PLL | PRE_PLL,
  72 };
  73
  74 static struct clk pll1_sysclk1 = {
  75         .name = "pll1_sysclk1",
  76         .parent = &pll1_clk,
  77         .flags = CLK_PLL,
  78         .div_reg = PLLDIV1,
  79 };
  80
  81 static struct clk pll1_sysclk2 = {
  82         .name = "pll1_sysclk2",
  83         .parent = &pll1_clk,
  84         .flags = CLK_PLL,
  85         .div_reg = PLLDIV2,
  86 };
  87
  88 static struct clk pll1_sysclk3 = {
  89         .name = "pll1_sysclk3",
  90         .parent = &pll1_clk,
  91         .flags = CLK_PLL,
  92         .div_reg = PLLDIV3,
  93 };
  94
  95 static struct clk pll1_sysclk4 = {
  96         .name = "pll1_sysclk4",
  97         .parent = &pll1_clk,
  98         .flags = CLK_PLL,
  99         .div_reg = PLLDIV4,
 100 };
 101
 102 static struct clk pll1_sysclkbp = {
 103         .name = "pll1_sysclkbp",
 104         .parent = &pll1_clk,
 105         .flags = CLK_PLL | PRE_PLL,
 106         .div_reg = BPDIV
 107 };
 108
 109 static struct clk vpss_dac_clk = {
 110         .name = "vpss_dac",
 111         .parent = &pll1_sysclk3,
 112         .lpsc = DM355_LPSC_VPSS_DAC,
 113 };
 114
 115 static struct clk vpss_master_clk = {
 116         .name = "vpss_master",
 117         .parent = &pll1_sysclk4,
 118         .lpsc = DAVINCI_LPSC_VPSSMSTR,
 119         .flags = CLK_PSC,
 120 };
 121
 122 static struct clk vpss_slave_clk = {
 123         .name = "vpss_slave",
 124         .parent = &pll1_sysclk4,
 125         .lpsc = DAVINCI_LPSC_VPSSSLV,
 126 };
 127
 128 static struct clk clkout1_clk = {
 129         .name = "clkout1",
 130         .parent = &pll1_aux_clk,
 131         /* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
 132 };
 133
 134 static struct clk clkout2_clk = {
 135         .name = "clkout2",
 136         .parent = &pll1_sysclkbp,
 137 };
 138
 139 static struct clk pll2_clk = {
 140         .name = "pll2",
 141         .parent = &ref_clk,
 142         .flags = CLK_PLL,
 143         .pll_data = &pll2_data,
 144 };
 145
 146 static struct clk pll2_sysclk1 = {
 147         .name = "pll2_sysclk1",
 148         .parent = &pll2_clk,
 149         .flags = CLK_PLL,
 150         .div_reg = PLLDIV1,
 151 };
 152
 153 static struct clk pll2_sysclkbp = {
 154         .name = "pll2_sysclkbp",
 155         .parent = &pll2_clk,
 156         .flags = CLK_PLL | PRE_PLL,
 157         .div_reg = BPDIV
 158 };
 159
 160 static struct clk clkout3_clk = {
 161         .name = "clkout3",
 162         .parent = &pll2_sysclkbp,
 163         /* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
 164 };
 165
 166 static struct clk arm_clk = {
 167         .name = "arm_clk",
 168         .parent = &pll1_sysclk1,
 169         .lpsc = DAVINCI_LPSC_ARM,
 170         .flags = ALWAYS_ENABLED,
 171 };
 172
 173 /*
 174  * NOT LISTED below, and not touched by Linux
 175  *   - in SyncReset state by default
 176  *      .lpsc = DAVINCI_LPSC_TPCC,
 177  *      .lpsc = DAVINCI_LPSC_TPTC0,
 178  *      .lpsc = DAVINCI_LPSC_TPTC1,
 179  *      .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
 180  *      .lpsc = DAVINCI_LPSC_MEMSTICK,
 181  *   - in Enabled state by default
 182  *      .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
 183  *      .lpsc = DAVINCI_LPSC_SCR2,      // "bus"
 184  *      .lpsc = DAVINCI_LPSC_SCR3,      // "bus"
 185  *      .lpsc = DAVINCI_LPSC_SCR4,      // "bus"
 186  *      .lpsc = DAVINCI_LPSC_CROSSBAR,  // "emulation"
 187  *      .lpsc = DAVINCI_LPSC_CFG27,     // "test"
 188  *      .lpsc = DAVINCI_LPSC_CFG3,      // "test"
 189  *      .lpsc = DAVINCI_LPSC_CFG5,      // "test"
 190  */
 191
 192 static struct clk mjcp_clk = {
 193         .name = "mjcp",
 194         .parent = &pll1_sysclk1,
 195         .lpsc = DAVINCI_LPSC_IMCOP,
 196 };
 197
 198 static struct clk uart0_clk = {
 199         .name = "uart0",
 200         .parent = &pll1_aux_clk,
 201         .lpsc = DAVINCI_LPSC_UART0,
 202 };
 203
 204 static struct clk uart1_clk = {
 205         .name = "uart1",
 206         .parent = &pll1_aux_clk,
 207         .lpsc = DAVINCI_LPSC_UART1,
 208 };
 209
 210 static struct clk uart2_clk = {
 211         .name = "uart2",
 212         .parent = &pll1_sysclk2,
 213         .lpsc = DAVINCI_LPSC_UART2,
 214 };
 215
 216 static struct clk i2c_clk = {
 217         .name = "i2c",
 218         .parent = &pll1_aux_clk,
 219         .lpsc = DAVINCI_LPSC_I2C,
 220 };
 221
 222 static struct clk asp0_clk = {
 223         .name = "asp0",
 224         .parent = &pll1_sysclk2,
 225         .lpsc = DAVINCI_LPSC_McBSP,
 226 };
 227
 228 static struct clk asp1_clk = {
 229         .name = "asp1",
 230         .parent = &pll1_sysclk2,
 231         .lpsc = DM355_LPSC_McBSP1,
 232 };
 233
 234 static struct clk mmcsd0_clk = {
 235         .name = "mmcsd0",
 236         .parent = &pll1_sysclk2,
 237         .lpsc = DAVINCI_LPSC_MMC_SD,
 238 };
 239
 240 static struct clk mmcsd1_clk = {
 241         .name = "mmcsd1",
 242         .parent = &pll1_sysclk2,
 243         .lpsc = DM355_LPSC_MMC_SD1,
 244 };
 245
 246 static struct clk spi0_clk = {
 247         .name = "spi0",
 248         .parent = &pll1_sysclk2,
 249         .lpsc = DAVINCI_LPSC_SPI,
 250 };
 251
 252 static struct clk spi1_clk = {
 253         .name = "spi1",
 254         .parent = &pll1_sysclk2,
 255         .lpsc = DM355_LPSC_SPI1,
 256 };
 257
 258 static struct clk spi2_clk = {
 259         .name = "spi2",
 260         .parent = &pll1_sysclk2,
 261         .lpsc = DM355_LPSC_SPI2,
 262 };
 263
 264 static struct clk gpio_clk = {
 265         .name = "gpio",
 266         .parent = &pll1_sysclk2,
 267         .lpsc = DAVINCI_LPSC_GPIO,
 268 };
 269
 270 static struct clk aemif_clk = {
 271         .name = "aemif",
 272         .parent = &pll1_sysclk2,
 273         .lpsc = DAVINCI_LPSC_AEMIF,
 274 };
 275
 276 static struct clk pwm0_clk = {
 277         .name = "pwm0",
 278         .parent = &pll1_aux_clk,
 279         .lpsc = DAVINCI_LPSC_PWM0,
 280 };
 281
 282 static struct clk pwm1_clk = {
 283         .name = "pwm1",
 284         .parent = &pll1_aux_clk,
 285         .lpsc = DAVINCI_LPSC_PWM1,
 286 };
 287
 288 static struct clk pwm2_clk = {
 289         .name = "pwm2",
 290         .parent = &pll1_aux_clk,
 291         .lpsc = DAVINCI_LPSC_PWM2,
 292 };
 293
 294 static struct clk pwm3_clk = {
 295         .name = "pwm3",
 296         .parent = &pll1_aux_clk,
 297         .lpsc = DM355_LPSC_PWM3,
 298 };
 299
 300 static struct clk timer0_clk = {
 301         .name = "timer0",
 302         .parent = &pll1_aux_clk,
 303         .lpsc = DAVINCI_LPSC_TIMER0,
 304 };
 305
 306 static struct clk timer1_clk = {
 307         .name = "timer1",
 308         .parent = &pll1_aux_clk,
 309         .lpsc = DAVINCI_LPSC_TIMER1,
 310 };
 311
 312 static struct clk timer2_clk = {
 313         .name = "timer2",
 314         .parent = &pll1_aux_clk,
 315         .lpsc = DAVINCI_LPSC_TIMER2,
 316         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
 317 };
 318
 319 static struct clk timer3_clk = {
 320         .name = "timer3",
 321         .parent = &pll1_aux_clk,
 322         .lpsc = DM355_LPSC_TIMER3,
 323 };
 324
 325 static struct clk rto_clk = {
 326         .name = "rto",
 327         .parent = &pll1_aux_clk,
 328         .lpsc = DM355_LPSC_RTO,
 329 };
 330
 331 static struct clk usb_clk = {
 332         .name = "usb",
 333         .parent = &pll1_sysclk2,
 334         .lpsc = DAVINCI_LPSC_USB,
 335 };
 336
 337 static struct clk_lookup dm355_clks[] = {
 338         CLK(NULL, "ref", &ref_clk),
 339         CLK(NULL, "pll1", &pll1_clk),
 340         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 341         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 342         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 343         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
 344         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 345         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 346         CLK(NULL, "vpss_dac", &vpss_dac_clk),
 347         CLK(NULL, "vpss_master", &vpss_master_clk),
 348         CLK(NULL, "vpss_slave", &vpss_slave_clk),
 349         CLK(NULL, "clkout1", &clkout1_clk),
 350         CLK(NULL, "clkout2", &clkout2_clk),
 351         CLK(NULL, "pll2", &pll2_clk),
 352         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 353         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
 354         CLK(NULL, "clkout3", &clkout3_clk),
 355         CLK(NULL, "arm", &arm_clk),
 356         CLK(NULL, "mjcp", &mjcp_clk),
 357         CLK(NULL, "uart0", &uart0_clk),
 358         CLK(NULL, "uart1", &uart1_clk),
 359         CLK(NULL, "uart2", &uart2_clk),
 360         CLK("i2c_davinci.1", NULL, &i2c_clk),
 361         CLK("davinci-asp.0", NULL, &asp0_clk),
 362         CLK("davinci-asp.1", NULL, &asp1_clk),
 363         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
 364         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
 365         CLK("spi_davinci.0", NULL, &spi0_clk),
 366         CLK("spi_davinci.1", NULL, &spi1_clk),
 367         CLK("spi_davinci.2", NULL, &spi2_clk),
 368         CLK(NULL, "gpio", &gpio_clk),
 369         CLK(NULL, "aemif", &aemif_clk),
 370         CLK(NULL, "pwm0", &pwm0_clk),
 371         CLK(NULL, "pwm1", &pwm1_clk),
 372         CLK(NULL, "pwm2", &pwm2_clk),
 373         CLK(NULL, "pwm3", &pwm3_clk),
 374         CLK(NULL, "timer0", &timer0_clk),
 375         CLK(NULL, "timer1", &timer1_clk),
 376         CLK("watchdog", NULL, &timer2_clk),
 377         CLK(NULL, "timer3", &timer3_clk),
 378         CLK(NULL, "rto", &rto_clk),
 379         CLK(NULL, "usb", &usb_clk),
 380         CLK(NULL, NULL, NULL),
 381 };
 382
 383 /*----------------------------------------------------------------------*/
 384
 385 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
 386
 387 static struct resource dm355_spi0_resources[] = {
 388         {
 389                 .start = 0x01c66000,
 390                 .end   = 0x01c667ff,
 391                 .flags = IORESOURCE_MEM,
 392         },
 393         {
 394                 .start = IRQ_DM355_SPINT0_0,
 395                 .flags = IORESOURCE_IRQ,
 396         },
 397         {
 398                 .start = 17,
 399                 .flags = IORESOURCE_DMA,
 400         },
 401         {
 402                 .start = 16,
 403                 .flags = IORESOURCE_DMA,
 404         },
 405         {
 406                 .start = EVENTQ_1,
 407                 .flags = IORESOURCE_DMA,
 408         },
 409 };
 410
 411 static struct davinci_spi_platform_data dm355_spi0_pdata = {
 412         .version        = SPI_VERSION_1,
 413         .num_chipselect = 2,
 414         .clk_internal   = 1,
 415         .cs_hold        = 1,
 416         .intr_level     = 0,
 417         .poll_mode      = 1,    /* 0 -> interrupt mode 1-> polling mode */
 418         .c2tdelay       = 0,
 419         .t2cdelay       = 0,
 420 };
 421 static struct platform_device dm355_spi0_device = {
 422         .name = "spi_davinci",
 423         .id = 0,
 424         .dev = {
 425                 .dma_mask = &dm355_spi0_dma_mask,
 426                 .coherent_dma_mask = DMA_BIT_MASK(32),
 427                 .platform_data = &dm355_spi0_pdata,
 428         },
 429         .num_resources = ARRAY_SIZE(dm355_spi0_resources),
 430         .resource = dm355_spi0_resources,
 431 };
 432
 433 void __init dm355_init_spi0(unsigned chipselect_mask,
 434                 struct spi_board_info *info, unsigned len)
 435 {
 436         /* for now, assume we need MISO */
 437         davinci_cfg_reg(DM355_SPI0_SDI);
 438
 439         /* not all slaves will be wired up */
 440         if (chipselect_mask & BIT(0))
 441                 davinci_cfg_reg(DM355_SPI0_SDENA0);
 442         if (chipselect_mask & BIT(1))
 443                 davinci_cfg_reg(DM355_SPI0_SDENA1);
 444
 445         spi_register_board_info(info, len);
 446
 447         platform_device_register(&dm355_spi0_device);
 448 }
 449
 450 /*----------------------------------------------------------------------*/
 451
 452 #define INTMUX          0x18
 453 #define EVTMUX          0x1c
 454
 455 /*
 456  * Device specific mux setup
 457  *
 458  *      soc     description     mux  mode   mode  mux    dbg
 459  *                              reg  offset mask  mode
 460  */
 461 static const struct mux_config dm355_pins[] = {
 462 #ifdef CONFIG_DAVINCI_MUX
 463 MUX_CFG(DM355,  MMCSD0,         4,   2,     1,    0,     false)
 464
 465 MUX_CFG(DM355,  SD1_CLK,        3,   6,     1,    1,     false)
 466 MUX_CFG(DM355,  SD1_CMD,        3,   7,     1,    1,     false)
 467 MUX_CFG(DM355,  SD1_DATA3,      3,   8,     3,    1,     false)
 468 MUX_CFG(DM355,  SD1_DATA2,      3,   10,    3,    1,     false)
 469 MUX_CFG(DM355,  SD1_DATA1,      3,   12,    3,    1,     false)
 470 MUX_CFG(DM355,  SD1_DATA0,      3,   14,    3,    1,     false)
 471
 472 MUX_CFG(DM355,  I2C_SDA,        3,   19,    1,    1,     false)
 473 MUX_CFG(DM355,  I2C_SCL,        3,   20,    1,    1,     false)
 474
 475 MUX_CFG(DM355,  MCBSP0_BDX,     3,   0,     1,    1,     false)
 476 MUX_CFG(DM355,  MCBSP0_X,       3,   1,     1,    1,     false)
 477 MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
 478 MUX_CFG(DM355,  MCBSP0_BDR,     3,   3,     1,    1,     false)
 479 MUX_CFG(DM355,  MCBSP0_R,       3,   4,     1,    1,     false)
 480 MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
 481
 482 MUX_CFG(DM355,  SPI0_SDI,       4,   1,     1,    0,     false)
 483 MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
 484 MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
 485
 486 INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
 487 INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
 488 INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
 489
 490 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
 491 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
 492 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
 493
 494 MUX_CFG(DM355,  VOUT_FIELD,     1,   18,    3,    1,     false)
 495 MUX_CFG(DM355,  VOUT_FIELD_G70, 1,   18,    3,    0,     false)
 496 MUX_CFG(DM355,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 497 MUX_CFG(DM355,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 498 MUX_CFG(DM355,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 499
 500 MUX_CFG(DM355,  VIN_PCLK,       0,   14,    1,    1,     false)
 501 MUX_CFG(DM355,  VIN_CAM_WEN,    0,   13,    1,    1,     false)
 502 MUX_CFG(DM355,  VIN_CAM_VD,     0,   12,    1,    1,     false)
 503 MUX_CFG(DM355,  VIN_CAM_HD,     0,   11,    1,    1,     false)
 504 MUX_CFG(DM355,  VIN_YIN_EN,     0,   10,    1,    1,     false)
 505 MUX_CFG(DM355,  VIN_CINL_EN,    0,   0,   0xff, 0x55,    false)
 506 MUX_CFG(DM355,  VIN_CINH_EN,    0,   8,     3,    3,     false)
 507 #endif
 508 };
 509
 510 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 511         [IRQ_DM355_CCDC_VDINT0]         = 2,
 512         [IRQ_DM355_CCDC_VDINT1]         = 6,
 513         [IRQ_DM355_CCDC_VDINT2]         = 6,
 514         [IRQ_DM355_IPIPE_HST]           = 6,
 515         [IRQ_DM355_H3AINT]              = 6,
 516         [IRQ_DM355_IPIPE_SDR]           = 6,
 517         [IRQ_DM355_IPIPEIFINT]          = 6,
 518         [IRQ_DM355_OSDINT]              = 7,
 519         [IRQ_DM355_VENCINT]             = 6,
 520         [IRQ_ASQINT]                    = 6,
 521         [IRQ_IMXINT]                    = 6,
 522         [IRQ_USBINT]                    = 4,
 523         [IRQ_DM355_RTOINT]              = 4,
 524         [IRQ_DM355_UARTINT2]            = 7,
 525         [IRQ_DM355_TINT6]               = 7,
 526         [IRQ_CCINT0]                    = 5,    /* dma */
 527         [IRQ_CCERRINT]                  = 5,    /* dma */
 528         [IRQ_TCERRINT0]                 = 5,    /* dma */
 529         [IRQ_TCERRINT]                  = 5,    /* dma */
 530         [IRQ_DM355_SPINT2_1]            = 7,
 531         [IRQ_DM355_TINT7]               = 4,
 532         [IRQ_DM355_SDIOINT0]            = 7,
 533         [IRQ_MBXINT]                    = 7,
 534         [IRQ_MBRINT]                    = 7,
 535         [IRQ_MMCINT]                    = 7,
 536         [IRQ_DM355_MMCINT1]             = 7,
 537         [IRQ_DM355_PWMINT3]             = 7,
 538         [IRQ_DDRINT]                    = 7,
 539         [IRQ_AEMIFINT]                  = 7,
 540         [IRQ_DM355_SDIOINT1]            = 4,
 541         [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
 542         [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
 543         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 544         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 545         [IRQ_PWMINT0]                   = 7,
 546         [IRQ_PWMINT1]                   = 7,
 547         [IRQ_PWMINT2]                   = 7,
 548         [IRQ_I2C]                       = 3,
 549         [IRQ_UARTINT0]                  = 3,
 550         [IRQ_UARTINT1]                  = 3,
 551         [IRQ_DM355_SPINT0_0]            = 3,
 552         [IRQ_DM355_SPINT0_1]            = 3,
 553         [IRQ_DM355_GPIO0]               = 3,
 554         [IRQ_DM355_GPIO1]               = 7,
 555         [IRQ_DM355_GPIO2]               = 4,
 556         [IRQ_DM355_GPIO3]               = 4,
 557         [IRQ_DM355_GPIO4]               = 7,
 558         [IRQ_DM355_GPIO5]               = 7,
 559         [IRQ_DM355_GPIO6]               = 7,
 560         [IRQ_DM355_GPIO7]               = 7,
 561         [IRQ_DM355_GPIO8]               = 7,
 562         [IRQ_DM355_GPIO9]               = 7,
 563         [IRQ_DM355_GPIOBNK0]            = 7,
 564         [IRQ_DM355_GPIOBNK1]            = 7,
 565         [IRQ_DM355_GPIOBNK2]            = 7,
 566         [IRQ_DM355_GPIOBNK3]            = 7,
 567         [IRQ_DM355_GPIOBNK4]            = 7,
 568         [IRQ_DM355_GPIOBNK5]            = 7,
 569         [IRQ_DM355_GPIOBNK6]            = 7,
 570         [IRQ_COMMTX]                    = 7,
 571         [IRQ_COMMRX]                    = 7,
 572         [IRQ_EMUINT]                    = 7,
 573 };
 574
 575 /*----------------------------------------------------------------------*/
 576
 577 static const s8
 578 queue_tc_mapping[][2] = {
 579         /* {event queue no, TC no} */
 580         {0, 0},
 581         {1, 1},
 582         {-1, -1},
 583 };
 584
 585 static const s8
 586 queue_priority_mapping[][2] = {
 587         /* {event queue no, Priority} */
 588         {0, 3},
 589         {1, 7},
 590         {-1, -1},
 591 };
 592
 593 static struct edma_soc_info edma_cc0_info = {
 594         .n_channel              = 64,
 595         .n_region               = 4,
 596         .n_slot                 = 128,
 597         .n_tc                   = 2,
 598         .n_cc                   = 1,
 599         .queue_tc_mapping       = queue_tc_mapping,
 600         .queue_priority_mapping = queue_priority_mapping,
 601 };
 602
 603 static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
 604        &edma_cc0_info,
 605 };
 606
 607 static struct resource edma_resources[] = {
 608         {
 609                 .name   = "edma_cc0",
 610                 .start  = 0x01c00000,
 611                 .end    = 0x01c00000 + SZ_64K - 1,
 612                 .flags  = IORESOURCE_MEM,
 613         },
 614         {
 615                 .name   = "edma_tc0",
 616                 .start  = 0x01c10000,
 617                 .end    = 0x01c10000 + SZ_1K - 1,
 618                 .flags  = IORESOURCE_MEM,
 619         },
 620         {
 621                 .name   = "edma_tc1",
 622                 .start  = 0x01c10400,
 623                 .end    = 0x01c10400 + SZ_1K - 1,
 624                 .flags  = IORESOURCE_MEM,
 625         },
 626         {
 627                 .name   = "edma0",
 628                 .start  = IRQ_CCINT0,
 629                 .flags  = IORESOURCE_IRQ,
 630         },
 631         {
 632                 .name   = "edma0_err",
 633                 .start  = IRQ_CCERRINT,
 634                 .flags  = IORESOURCE_IRQ,
 635         },
 636         /* not using (or muxing) TC*_ERR */
 637 };
 638
 639 static struct platform_device dm355_edma_device = {
 640         .name                   = "edma",
 641         .id                     = 0,
 642         .dev.platform_data      = dm355_edma_info,
 643         .num_resources          = ARRAY_SIZE(edma_resources),
 644         .resource               = edma_resources,
 645 };
 646
 647 static struct resource dm355_asp1_resources[] = {
 648         {
 649                 .start  = DAVINCI_ASP1_BASE,
 650                 .end    = DAVINCI_ASP1_BASE + SZ_8K - 1,
 651                 .flags  = IORESOURCE_MEM,
 652         },
 653         {
 654                 .start  = DAVINCI_DMA_ASP1_TX,
 655                 .end    = DAVINCI_DMA_ASP1_TX,
 656                 .flags  = IORESOURCE_DMA,
 657         },
 658         {
 659                 .start  = DAVINCI_DMA_ASP1_RX,
 660                 .end    = DAVINCI_DMA_ASP1_RX,
 661                 .flags  = IORESOURCE_DMA,
 662         },
 663 };
 664
 665 static struct platform_device dm355_asp1_device = {
 666         .name           = "davinci-asp",
 667         .id             = 1,
 668         .num_resources  = ARRAY_SIZE(dm355_asp1_resources),
 669         .resource       = dm355_asp1_resources,
 670 };
 671
 672 static void dm355_ccdc_setup_pinmux(void)
 673 {
 674         davinci_cfg_reg(DM355_VIN_PCLK);
 675         davinci_cfg_reg(DM355_VIN_CAM_WEN);
 676         davinci_cfg_reg(DM355_VIN_CAM_VD);
 677         davinci_cfg_reg(DM355_VIN_CAM_HD);
 678         davinci_cfg_reg(DM355_VIN_YIN_EN);
 679         davinci_cfg_reg(DM355_VIN_CINL_EN);
 680         davinci_cfg_reg(DM355_VIN_CINH_EN);
 681 }
 682
 683 static struct resource dm355_vpss_resources[] = {
 684         {
 685                 /* VPSS BL Base address */
 686                 .name           = "vpss",
 687                 .start          = 0x01c70800,
 688                 .end            = 0x01c70800 + 0xff,
 689                 .flags          = IORESOURCE_MEM,
 690         },
 691         {
 692                 /* VPSS CLK Base address */
 693                 .name           = "vpss",
 694                 .start          = 0x01c70000,
 695                 .end            = 0x01c70000 + 0xf,
 696                 .flags          = IORESOURCE_MEM,
 697         },
 698 };
 699
 700 static struct platform_device dm355_vpss_device = {
 701         .name                   = "vpss",
 702         .id                     = -1,
 703         .dev.platform_data      = "dm355_vpss",
 704         .num_resources          = ARRAY_SIZE(dm355_vpss_resources),
 705         .resource               = dm355_vpss_resources,
 706 };
 707
 708 static struct resource vpfe_resources[] = {
 709         {
 710                 .start          = IRQ_VDINT0,
 711                 .end            = IRQ_VDINT0,
 712                 .flags          = IORESOURCE_IRQ,
 713         },
 714         {
 715                 .start          = IRQ_VDINT1,
 716                 .end            = IRQ_VDINT1,
 717                 .flags          = IORESOURCE_IRQ,
 718         },
 719 };
 720
 721 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 722 static struct resource dm355_ccdc_resource[] = {
 723         /* CCDC Base address */
 724         {
 725                 .flags          = IORESOURCE_MEM,
 726                 .start          = 0x01c70600,
 727                 .end            = 0x01c70600 + 0x1ff,
 728         },
 729 };
 730 static struct platform_device dm355_ccdc_dev = {
 731         .name           = "dm355_ccdc",
 732         .id             = -1,
 733         .num_resources  = ARRAY_SIZE(dm355_ccdc_resource),
 734         .resource       = dm355_ccdc_resource,
 735         .dev = {
 736                 .dma_mask               = &vpfe_capture_dma_mask,
 737                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 738                 .platform_data          = dm355_ccdc_setup_pinmux,
 739         },
 740 };
 741
 742 static struct platform_device vpfe_capture_dev = {
 743         .name           = CAPTURE_DRV_NAME,
 744         .id             = -1,
 745         .num_resources  = ARRAY_SIZE(vpfe_resources),
 746         .resource       = vpfe_resources,
 747         .dev = {
 748                 .dma_mask               = &vpfe_capture_dma_mask,
 749                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 750         },
 751 };
 752
 753 void dm355_set_vpfe_config(struct vpfe_config *cfg)
 754 {
 755         vpfe_capture_dev.dev.platform_data = cfg;
 756 }
 757
 758 /*----------------------------------------------------------------------*/
 759
 760 static struct map_desc dm355_io_desc[] = {
 761         {
 762                 .virtual        = IO_VIRT,
 763                 .pfn            = __phys_to_pfn(IO_PHYS),
 764                 .length         = IO_SIZE,
 765                 .type           = MT_DEVICE
 766         },
 767         {
 768                 .virtual        = SRAM_VIRT,
 769                 .pfn            = __phys_to_pfn(0x00010000),
 770                 .length         = SZ_32K,
 771                 .type           = MT_MEMORY_NONCACHED,
 772         },
 773 };
 774
 775 /* Contents of JTAG ID register used to identify exact cpu type */
 776 static struct davinci_id dm355_ids[] = {
 777         {
 778                 .variant        = 0x0,
 779                 .part_no        = 0xb73b,
 780                 .manufacturer   = 0x00f,
 781                 .cpu_id         = DAVINCI_CPU_ID_DM355,
 782                 .name           = "dm355",
 783         },
 784 };
 785
 786 static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 787
 788 /*
 789  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 790  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 791  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 792  * T1_TOP: Timer 1, top   :  <unused>
 793  */
 794 static struct davinci_timer_info dm355_timer_info = {
 795         .timers         = davinci_timer_instance,
 796         .clockevent_id  = T0_BOT,
 797         .clocksource_id = T0_TOP,
 798 };
 799
 800 static struct plat_serial8250_port dm355_serial_platform_data[] = {
 801         {
 802                 .mapbase        = DAVINCI_UART0_BASE,
 803                 .irq            = IRQ_UARTINT0,
 804                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 805                                   UPF_IOREMAP,
 806                 .iotype         = UPIO_MEM,
 807                 .regshift       = 2,
 808         },
 809         {
 810                 .mapbase        = DAVINCI_UART1_BASE,
 811                 .irq            = IRQ_UARTINT1,
 812                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 813                                   UPF_IOREMAP,
 814                 .iotype         = UPIO_MEM,
 815                 .regshift       = 2,
 816         },
 817         {
 818                 .mapbase        = DM355_UART2_BASE,
 819                 .irq            = IRQ_DM355_UARTINT2,
 820                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 821                                   UPF_IOREMAP,
 822                 .iotype         = UPIO_MEM,
 823                 .regshift       = 2,
 824         },
 825         {
 826                 .flags          = 0
 827         },
 828 };
 829
 830 static struct platform_device dm355_serial_device = {
 831         .name                   = "serial8250",
 832         .id                     = PLAT8250_DEV_PLATFORM,
 833         .dev                    = {
 834                 .platform_data  = dm355_serial_platform_data,
 835         },
 836 };
 837
 838 static struct davinci_soc_info davinci_soc_info_dm355 = {
 839         .io_desc                = dm355_io_desc,
 840         .io_desc_num            = ARRAY_SIZE(dm355_io_desc),
 841         .jtag_id_reg            = 0x01c40028,
 842         .ids                    = dm355_ids,
 843         .ids_num                = ARRAY_SIZE(dm355_ids),
 844         .cpu_clks               = dm355_clks,
 845         .psc_bases              = dm355_psc_bases,
 846         .psc_bases_num          = ARRAY_SIZE(dm355_psc_bases),
 847         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 848         .pinmux_pins            = dm355_pins,
 849         .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
 850         .intc_base              = DAVINCI_ARM_INTC_BASE,
 851         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 852         .intc_irq_prios         = dm355_default_priorities,
 853         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 854         .timer_info             = &dm355_timer_info,
 855         .gpio_type              = GPIO_TYPE_DAVINCI,
 856         .gpio_base              = DAVINCI_GPIO_BASE,
 857         .gpio_num               = 104,
 858         .gpio_irq               = IRQ_DM355_GPIOBNK0,
 859         .serial_dev             = &dm355_serial_device,
 860         .sram_dma               = 0x00010000,
 861         .sram_len               = SZ_32K,
 862         .reset_device           = &davinci_wdt_device,
 863 };
 864
 865 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
 866 {
 867         /* we don't use ASP1 IRQs, or we'd need to mux them ... */
 868         if (evt_enable & ASP1_TX_EVT_EN)
 869                 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
 870
 871         if (evt_enable & ASP1_RX_EVT_EN)
 872                 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
 873
 874         dm355_asp1_device.dev.platform_data = pdata;
 875         platform_device_register(&dm355_asp1_device);
 876 }
 877
 878 void __init dm355_init(void)
 879 {
 880         davinci_common_init(&davinci_soc_info_dm355);
 881 }
 882
 883 static int __init dm355_init_devices(void)
 884 {
 885         if (!cpu_is_davinci_dm355())
 886                 return 0;
 887
 888         /* Add ccdc clock aliases */
 889         clk_add_alias("master", dm355_ccdc_dev.name, "vpss_master", NULL);
 890         clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_master", NULL);
 891         davinci_cfg_reg(DM355_INT_EDMA_CC);
 892         platform_device_register(&dm355_edma_device);
 893         platform_device_register(&dm355_vpss_device);
 894         platform_device_register(&dm355_ccdc_dev);
 895         platform_device_register(&vpfe_capture_dev);
 896
 897         return 0;
 898 }
 899 postcore_initcall(dm355_init_devices);