release/src-rt-6.x.4708/linux/linux-2.6.36/arch/alpha/kernel/sys_miata.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_miata.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999, 2000 Richard Henderson
   7  *
   8  * Code supporting the MIATA (EV56+PYXIS).
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/types.h>
  13 #include <linux/mm.h>
  14 #include <linux/sched.h>
  15 #include <linux/pci.h>
  16 #include <linux/init.h>
  17 #include <linux/reboot.h>
  18
  19 #include <asm/ptrace.h>
  20 #include <asm/system.h>
  21 #include <asm/dma.h>
  22 #include <asm/irq.h>
  23 #include <asm/mmu_context.h>
  24 #include <asm/io.h>
  25 #include <asm/pgtable.h>
  26 #include <asm/core_cia.h>
  27 #include <asm/tlbflush.h>
  28
  29 #include "proto.h"
  30 #include "irq_impl.h"
  31 #include "pci_impl.h"
  32 #include "machvec_impl.h"
  33
  34
  35 static void
  36 miata_srm_device_interrupt(unsigned long vector)
  37 {
  38         int irq;
  39
  40         irq = (vector - 0x800) >> 4;
  41
  42         /*
  43          * I really hate to do this, but the MIATA SRM console ignores the
  44          *  low 8 bits in the interrupt summary register, and reports the
  45          *  vector 0x80 *lower* than I expected from the bit numbering in
  46          *  the documentation.
  47          * This was done because the low 8 summary bits really aren't used
  48          *  for reporting any interrupts (the PCI-ISA bridge, bit 7, isn't
  49          *  used for this purpose, as PIC interrupts are delivered as the
  50          *  vectors 0x800-0x8f0).
  51          * But I really don't want to change the fixup code for allocation
  52          *  of IRQs, nor the alpha_irq_mask maintenance stuff, both of which
  53          *  look nice and clean now.
  54          * So, here's this grotty hack... :-(
  55          */
  56         if (irq >= 16)
  57                 irq = irq + 8;
  58
  59         handle_irq(irq);
  60 }
  61
  62 static void __init
  63 miata_init_irq(void)
  64 {
  65         if (alpha_using_srm)
  66                 alpha_mv.device_interrupt = miata_srm_device_interrupt;
  67
  68
  69         init_i8259a_irqs();
  70
  71         /* Not interested in the bogus interrupts (3,10), Fan Fault (0),
  72            NMI (1), or EIDE (9).
  73
  74            We also disable the risers (4,5), since we don't know how to
  75            route the interrupts behind the bridge.  */
  76         init_pyxis_irqs(0x63b0000);
  77
  78         common_init_isa_dma();
  79         setup_irq(16+2, &halt_switch_irqaction);        /* SRM only? */
  80         setup_irq(16+6, &timer_cascade_irqaction);
  81 }
  82
  83
  84 /*
  85  * PCI Fixup configuration.
  86  *
  87  * Summary @ PYXIS_INT_REQ:
  88  * Bit      Meaning
  89  * 0        Fan Fault
  90  * 1        NMI
  91  * 2        Halt/Reset switch
  92  * 3        none
  93  * 4        CID0 (Riser ID)
  94  * 5        CID1 (Riser ID)
  95  * 6        Interval timer
  96  * 7        PCI-ISA Bridge
  97  * 8        Ethernet
  98  * 9        EIDE (deprecated, ISA 14/15 used)
  99  *10        none
 100  *11        USB
 101  *12        Interrupt Line A from slot 4
 102  *13        Interrupt Line B from slot 4
 103  *14        Interrupt Line C from slot 4
 104  *15        Interrupt Line D from slot 4
 105  *16        Interrupt Line A from slot 5
 106  *17        Interrupt line B from slot 5
 107  *18        Interrupt Line C from slot 5
 108  *19        Interrupt Line D from slot 5
 109  *20        Interrupt Line A from slot 1
 110  *21        Interrupt Line B from slot 1
 111  *22        Interrupt Line C from slot 1
 112  *23        Interrupt Line D from slot 1
 113  *24        Interrupt Line A from slot 2
 114  *25        Interrupt Line B from slot 2
 115  *26        Interrupt Line C from slot 2
 116  *27        Interrupt Line D from slot 2
 117  *27        Interrupt Line A from slot 3
 118  *29        Interrupt Line B from slot 3
 119  *30        Interrupt Line C from slot 3
 120  *31        Interrupt Line D from slot 3
 121  *
 122  * The device to slot mapping looks like:
 123  *
 124  * Slot     Device
 125  *  3       DC21142 Ethernet
 126  *  4       EIDE CMD646
 127  *  5       none
 128  *  6       USB
 129  *  7       PCI-ISA bridge
 130  *  8       PCI-PCI Bridge      (SBU Riser)
 131  *  9       none
 132  * 10       none
 133  * 11       PCI on board slot 4 (SBU Riser)
 134  * 12       PCI on board slot 5 (SBU Riser)
 135  *
 136  *  These are behind the bridge, so I'm not sure what to do...
 137  *
 138  * 13       PCI on board slot 1 (SBU Riser)
 139  * 14       PCI on board slot 2 (SBU Riser)
 140  * 15       PCI on board slot 3 (SBU Riser)
 141  *
 142  *
 143  * This two layered interrupt approach means that we allocate IRQ 16 and
 144  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
 145  * comes in on.  This makes interrupt processing much easier.
 146  */
 147
 148 static int __init
 149 miata_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 150 {
 151         static char irq_tab[18][5] __initdata = {
 152                 /*INT    INTA   INTB   INTC   INTD */
 153                 {16+ 8, 16+ 8, 16+ 8, 16+ 8, 16+ 8},  /* IdSel 14,  DC21142 */
 154                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 15,  EIDE    */
 155                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 16,  none    */
 156                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 17,  none    */
 157                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 18,  PCI-ISA */
 158                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 19,  PCI-PCI */
 159                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 20,  none    */
 160                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 21,  none    */
 161                 {16+12, 16+12, 16+13, 16+14, 16+15},  /* IdSel 22,  slot 4  */
 162                 {16+16, 16+16, 16+17, 16+18, 16+19},  /* IdSel 23,  slot 5  */
 163                 /* the next 7 are actually on PCI bus 1, across the bridge */
 164                 {16+11, 16+11, 16+11, 16+11, 16+11},  /* IdSel 24,  QLISP/GL*/
 165                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 25,  none    */
 166                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 26,  none    */
 167                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 27,  none    */
 168                 {16+20, 16+20, 16+21, 16+22, 16+23},  /* IdSel 28,  slot 1  */
 169                 {16+24, 16+24, 16+25, 16+26, 16+27},  /* IdSel 29,  slot 2  */
 170                 {16+28, 16+28, 16+29, 16+30, 16+31},  /* IdSel 30,  slot 3  */
 171                 /* This bridge is on the main bus of the later orig MIATA */
 172                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 31,  PCI-PCI */
 173         };
 174         const long min_idsel = 3, max_idsel = 20, irqs_per_slot = 5;
 175
 176         /* the USB function of the 82c693 has it's interrupt connected to
 177            the 2nd 8259 controller. So we have to check for it first. */
 178
 179         if((slot == 7) && (PCI_FUNC(dev->devfn) == 3)) {
 180                 u8 irq=0;
 181                 struct pci_dev *pdev = pci_get_slot(dev->bus, dev->devfn & ~7);
 182                 if(pdev == NULL || pci_read_config_byte(pdev, 0x40,&irq) != PCIBIOS_SUCCESSFUL) {
 183                         pci_dev_put(pdev);
 184                         return -1;
 185                 }
 186                 else    {
 187                         pci_dev_put(pdev);
 188                         return irq;
 189                 }
 190         }
 191
 192         return COMMON_TABLE_LOOKUP;
 193 }
 194
 195 static u8 __init
 196 miata_swizzle(struct pci_dev *dev, u8 *pinp)
 197 {
 198         int slot, pin = *pinp;
 199
 200         if (dev->bus->number == 0) {
 201                 slot = PCI_SLOT(dev->devfn);
 202         }
 203         /* Check for the built-in bridge.  */
 204         else if ((PCI_SLOT(dev->bus->self->devfn) == 8) ||
 205                  (PCI_SLOT(dev->bus->self->devfn) == 20)) {
 206                 slot = PCI_SLOT(dev->devfn) + 9;
 207         }
 208         else
 209         {
 210                 /* Must be a card-based bridge.  */
 211                 do {
 212                         if ((PCI_SLOT(dev->bus->self->devfn) == 8) ||
 213                             (PCI_SLOT(dev->bus->self->devfn) == 20)) {
 214                                 slot = PCI_SLOT(dev->devfn) + 9;
 215                                 break;
 216                         }
 217                         pin = pci_swizzle_interrupt_pin(dev, pin);
 218
 219                         /* Move up the chain of bridges.  */
 220                         dev = dev->bus->self;
 221                         /* Slot of the next bridge.  */
 222                         slot = PCI_SLOT(dev->devfn);
 223                 } while (dev->bus->self);
 224         }
 225         *pinp = pin;
 226         return slot;
 227 }
 228
 229 static void __init
 230 miata_init_pci(void)
 231 {
 232         cia_init_pci();
 233         SMC669_Init(0); /* it might be a GL (fails harmlessly if not) */
 234         es1888_init();
 235 }
 236
 237 static void
 238 miata_kill_arch(int mode)
 239 {
 240         cia_kill_arch(mode);
 241
 242 #ifndef ALPHA_RESTORE_SRM_SETUP
 243         switch(mode) {
 244         case LINUX_REBOOT_CMD_RESTART:
 245                 /* Who said DEC engineers have no sense of humor? ;-)  */
 246                 if (alpha_using_srm) {
 247                         *(vuip) PYXIS_RESET = 0x0000dead;
 248                         mb();
 249                 }
 250                 break;
 251         case LINUX_REBOOT_CMD_HALT:
 252                 break;
 253         case LINUX_REBOOT_CMD_POWER_OFF:
 254                 break;
 255         }
 256
 257         halt();
 258 #endif
 259 }
 260
 261
 262 /*
 263  * The System Vector
 264  */
 265
 266 struct alpha_machine_vector miata_mv __initmv = {
 267         .vector_name            = "Miata",
 268         DO_EV5_MMU,
 269         DO_DEFAULT_RTC,
 270         DO_PYXIS_IO,
 271         .machine_check          = cia_machine_check,
 272         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 273         .min_io_address         = DEFAULT_IO_BASE,
 274         .min_mem_address        = DEFAULT_MEM_BASE,
 275         .pci_dac_offset         = PYXIS_DAC_OFFSET,
 276
 277         .nr_irqs                = 48,
 278         .device_interrupt       = pyxis_device_interrupt,
 279
 280         .init_arch              = pyxis_init_arch,
 281         .init_irq               = miata_init_irq,
 282         .init_rtc               = common_init_rtc,
 283         .init_pci               = miata_init_pci,
 284         .kill_arch              = miata_kill_arch,
 285         .pci_map_irq            = miata_map_irq,
 286         .pci_swizzle            = miata_swizzle,
 287 };
 288 ALIAS_MV(miata)