release/src-rt-6.x.4708/linux/linux-2.6.36/arch/alpha/kernel/sys_cabriolet.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_cabriolet.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999, 2000 Richard Henderson
   7  *
   8  * Code supporting the Cabriolet (AlphaPC64), EB66+, and EB164,
   9  * PC164 and LX164.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/mm.h>
  15 #include <linux/sched.h>
  16 #include <linux/pci.h>
  17 #include <linux/init.h>
  18 #include <linux/bitops.h>
  19
  20 #include <asm/ptrace.h>
  21 #include <asm/system.h>
  22 #include <asm/dma.h>
  23 #include <asm/irq.h>
  24 #include <asm/mmu_context.h>
  25 #include <asm/io.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/core_apecs.h>
  28 #include <asm/core_cia.h>
  29 #include <asm/core_lca.h>
  30 #include <asm/tlbflush.h>
  31
  32 #include "proto.h"
  33 #include "irq_impl.h"
  34 #include "pci_impl.h"
  35 #include "machvec_impl.h"
  36 #include "pc873xx.h"
  37
  38 /* Note mask bit is true for DISABLED irqs.  */
  39 static unsigned long cached_irq_mask = ~0UL;
  40
  41 static inline void
  42 cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
  43 {
  44         int ofs = (irq - 16) / 8;
  45         outb(mask >> (16 + ofs * 8), 0x804 + ofs);
  46 }
  47
  48 static inline void
  49 cabriolet_enable_irq(unsigned int irq)
  50 {
  51         cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq));
  52 }
  53
  54 static void
  55 cabriolet_disable_irq(unsigned int irq)
  56 {
  57         cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
  58 }
  59
  60 static unsigned int
  61 cabriolet_startup_irq(unsigned int irq)
  62 {
  63         cabriolet_enable_irq(irq);
  64         return 0; /* never anything pending */
  65 }
  66
  67 static void
  68 cabriolet_end_irq(unsigned int irq)
  69 {
  70         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
  71                 cabriolet_enable_irq(irq);
  72 }
  73
  74 static struct irq_chip cabriolet_irq_type = {
  75         .name           = "CABRIOLET",
  76         .startup        = cabriolet_startup_irq,
  77         .shutdown       = cabriolet_disable_irq,
  78         .enable         = cabriolet_enable_irq,
  79         .disable        = cabriolet_disable_irq,
  80         .ack            = cabriolet_disable_irq,
  81         .end            = cabriolet_end_irq,
  82 };
  83
  84 static void
  85 cabriolet_device_interrupt(unsigned long v)
  86 {
  87         unsigned long pld;
  88         unsigned int i;
  89
  90         /* Read the interrupt summary registers */
  91         pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16);
  92
  93         /*
  94          * Now for every possible bit set, work through them and call
  95          * the appropriate interrupt handler.
  96          */
  97         while (pld) {
  98                 i = ffz(~pld);
  99                 pld &= pld - 1; /* clear least bit set */
 100                 if (i == 4) {
 101                         isa_device_interrupt(v);
 102                 } else {
 103                         handle_irq(16 + i);
 104                 }
 105         }
 106 }
 107
 108 static void __init
 109 common_init_irq(void (*srm_dev_int)(unsigned long v))
 110 {
 111         init_i8259a_irqs();
 112
 113         if (alpha_using_srm) {
 114                 alpha_mv.device_interrupt = srm_dev_int;
 115                 init_srm_irqs(35, 0);
 116         }
 117         else {
 118                 long i;
 119
 120                 outb(0xff, 0x804);
 121                 outb(0xff, 0x805);
 122                 outb(0xff, 0x806);
 123
 124                 for (i = 16; i < 35; ++i) {
 125                         irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
 126                         irq_desc[i].chip = &cabriolet_irq_type;
 127                 }
 128         }
 129
 130         common_init_isa_dma();
 131         setup_irq(16+4, &isa_cascade_irqaction);
 132 }
 133
 134 #ifndef CONFIG_ALPHA_PC164
 135 static void __init
 136 cabriolet_init_irq(void)
 137 {
 138         common_init_irq(srm_device_interrupt);
 139 }
 140 #endif
 141
 142 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
 143
 144 static void
 145 pc164_srm_device_interrupt(unsigned long v)
 146 {
 147         __min_ipl = getipl();
 148         srm_device_interrupt(v);
 149         __min_ipl = 0;
 150 }
 151
 152 static void
 153 pc164_device_interrupt(unsigned long v)
 154 {
 155         __min_ipl = getipl();
 156         cabriolet_device_interrupt(v);
 157         __min_ipl = 0;
 158 }
 159
 160 static void __init
 161 pc164_init_irq(void)
 162 {
 163         common_init_irq(pc164_srm_device_interrupt);
 164 }
 165 #endif
 166
 167 /*
 168  * The EB66+ is very similar to the EB66 except that it does not have
 169  * the on-board NCR and Tulip chips.  In the code below, I have used
 170  * slot number to refer to the id select line and *not* the slot
 171  * number used in the EB66+ documentation.  However, in the table,
 172  * I've given the slot number, the id select line and the Jxx number
 173  * that's printed on the board.  The interrupt pins from the PCI slots
 174  * are wired into 3 interrupt summary registers at 0x804, 0x805 and
 175  * 0x806 ISA.
 176  *
 177  * In the table, -1 means don't assign an IRQ number.  This is usually
 178  * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
 179  */
 180
 181 static inline int __init
 182 eb66p_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 183 {
 184         static char irq_tab[5][5] __initdata = {
 185                 /*INT  INTA  INTB  INTC   INTD */
 186                 {16+0, 16+0, 16+5,  16+9, 16+13},  /* IdSel 6,  slot 0, J25 */
 187                 {16+1, 16+1, 16+6, 16+10, 16+14},  /* IdSel 7,  slot 1, J26 */
 188                 {  -1,   -1,   -1,    -1,    -1},  /* IdSel 8,  SIO         */
 189                 {16+2, 16+2, 16+7, 16+11, 16+15},  /* IdSel 9,  slot 2, J27 */
 190                 {16+3, 16+3, 16+8, 16+12,  16+6}   /* IdSel 10, slot 3, J28 */
 191         };
 192         const long min_idsel = 6, max_idsel = 10, irqs_per_slot = 5;
 193         return COMMON_TABLE_LOOKUP;
 194 }
 195
 196
 197 /*
 198  * The AlphaPC64 is very similar to the EB66+ except that its slots
 199  * are numbered differently.  In the code below, I have used slot
 200  * number to refer to the id select line and *not* the slot number
 201  * used in the AlphaPC64 documentation.  However, in the table, I've
 202  * given the slot number, the id select line and the Jxx number that's
 203  * printed on the board.  The interrupt pins from the PCI slots are
 204  * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
 205  * ISA.
 206  *
 207  * In the table, -1 means don't assign an IRQ number.  This is usually
 208  * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
 209  */
 210
 211 static inline int __init
 212 cabriolet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 213 {
 214         static char irq_tab[5][5] __initdata = {
 215                 /*INT   INTA  INTB  INTC   INTD */
 216                 { 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5,  slot 2, J21 */
 217                 { 16+0, 16+0, 16+5,  16+9, 16+13}, /* IdSel 6,  slot 0, J19 */
 218                 { 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7,  slot 1, J20 */
 219                 {   -1,   -1,   -1,    -1,    -1}, /* IdSel 8,  SIO         */
 220                 { 16+3, 16+3, 16+8, 16+12, 16+16}  /* IdSel 9,  slot 3, J22 */
 221         };
 222         const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5;
 223         return COMMON_TABLE_LOOKUP;
 224 }
 225
 226 static inline void __init
 227 cabriolet_enable_ide(void)
 228 {
 229         if (pc873xx_probe() == -1) {
 230                 printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
 231          } else {
 232                 printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
 233                         pc873xx_get_model(), pc873xx_get_base());
 234
 235                 pc873xx_enable_ide();
 236         }
 237 }
 238
 239 static inline void __init
 240 cabriolet_init_pci(void)
 241 {
 242         common_init_pci();
 243         cabriolet_enable_ide();
 244 }
 245
 246 static inline void __init
 247 cia_cab_init_pci(void)
 248 {
 249         cia_init_pci();
 250         cabriolet_enable_ide();
 251 }
 252
 253 /*
 254  * The PC164 and LX164 have 19 PCI interrupts, four from each of the four
 255  * PCI slots, the SIO, PCI/IDE, and USB.
 256  *
 257  * Each of the interrupts can be individually masked. This is
 258  * accomplished by setting the appropriate bit in the mask register.
 259  * A bit is set by writing a "1" to the desired position in the mask
 260  * register and cleared by writing a "0". There are 3 mask registers
 261  * located at ISA address 804h, 805h and 806h.
 262  *
 263  * An I/O read at ISA address 804h, 805h, 806h will return the
 264  * state of the 11 PCI interrupts and not the state of the MASKED
 265  * interrupts.
 266  *
 267  * Note: A write to I/O 804h, 805h, and 806h the mask register will be
 268  * updated.
 269  *
 270  *
 271  *                              ISA DATA<7:0>
 272  * ISA     +--------------------------------------------------------------+
 273  * ADDRESS |   7   |   6   |   5   |   4   |   3   |   2  |   1   |   0   |
 274  *         +==============================================================+
 275  * 0x804   | INTB0 |  USB  |  IDE  |  SIO  | INTA3 |INTA2 | INTA1 | INTA0 |
 276  *         +--------------------------------------------------------------+
 277  * 0x805   | INTD0 | INTC3 | INTC2 | INTC1 | INTC0 |INTB3 | INTB2 | INTB1 |
 278  *         +--------------------------------------------------------------+
 279  * 0x806   | Rsrv  | Rsrv  | Rsrv  | Rsrv  | Rsrv  |INTD3 | INTD2 | INTD1 |
 280  *         +--------------------------------------------------------------+
 281  *         * Rsrv = reserved bits
 282  *         Note: The mask register is write-only.
 283  *
 284  * IdSel
 285  *   5   32 bit PCI option slot 2
 286  *   6   64 bit PCI option slot 0
 287  *   7   64 bit PCI option slot 1
 288  *   8   Saturn I/O
 289  *   9   32 bit PCI option slot 3
 290  *  10   USB
 291  *  11   IDE
 292  *
 293  */
 294
 295 static inline int __init
 296 alphapc164_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 297 {
 298         static char irq_tab[7][5] __initdata = {
 299                 /*INT   INTA  INTB   INTC   INTD */
 300                 { 16+2, 16+2, 16+9,  16+13, 16+17}, /* IdSel  5, slot 2, J20 */
 301                 { 16+0, 16+0, 16+7,  16+11, 16+15}, /* IdSel  6, slot 0, J29 */
 302                 { 16+1, 16+1, 16+8,  16+12, 16+16}, /* IdSel  7, slot 1, J26 */
 303                 {   -1,   -1,   -1,    -1,    -1},  /* IdSel  8, SIO */
 304                 { 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel  9, slot 3, J19 */
 305                 { 16+6, 16+6, 16+6,  16+6,  16+6},  /* IdSel 10, USB */
 306                 { 16+5, 16+5, 16+5,  16+5,  16+5}   /* IdSel 11, IDE */
 307         };
 308         const long min_idsel = 5, max_idsel = 11, irqs_per_slot = 5;
 309         return COMMON_TABLE_LOOKUP;
 310 }
 311
 312 static inline void __init
 313 alphapc164_init_pci(void)
 314 {
 315         cia_init_pci();
 316         SMC93x_Init();
 317 }
 318
 319
 320 /*
 321  * The System Vector
 322  */
 323
 324 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET)
 325 struct alpha_machine_vector cabriolet_mv __initmv = {
 326         .vector_name            = "Cabriolet",
 327         DO_EV4_MMU,
 328         DO_DEFAULT_RTC,
 329         DO_APECS_IO,
 330         .machine_check          = apecs_machine_check,
 331         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 332         .min_io_address         = DEFAULT_IO_BASE,
 333         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 334
 335         .nr_irqs                = 35,
 336         .device_interrupt       = cabriolet_device_interrupt,
 337
 338         .init_arch              = apecs_init_arch,
 339         .init_irq               = cabriolet_init_irq,
 340         .init_rtc               = common_init_rtc,
 341         .init_pci               = cabriolet_init_pci,
 342         .pci_map_irq            = cabriolet_map_irq,
 343         .pci_swizzle            = common_swizzle,
 344 };
 345 #ifndef CONFIG_ALPHA_EB64P
 346 ALIAS_MV(cabriolet)
 347 #endif
 348 #endif
 349
 350 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB164)
 351 struct alpha_machine_vector eb164_mv __initmv = {
 352         .vector_name            = "EB164",
 353         DO_EV5_MMU,
 354         DO_DEFAULT_RTC,
 355         DO_CIA_IO,
 356         .machine_check          = cia_machine_check,
 357         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 358         .min_io_address         = DEFAULT_IO_BASE,
 359         .min_mem_address        = CIA_DEFAULT_MEM_BASE,
 360
 361         .nr_irqs                = 35,
 362         .device_interrupt       = cabriolet_device_interrupt,
 363
 364         .init_arch              = cia_init_arch,
 365         .init_irq               = cabriolet_init_irq,
 366         .init_rtc               = common_init_rtc,
 367         .init_pci               = cia_cab_init_pci,
 368         .kill_arch              = cia_kill_arch,
 369         .pci_map_irq            = cabriolet_map_irq,
 370         .pci_swizzle            = common_swizzle,
 371 };
 372 ALIAS_MV(eb164)
 373 #endif
 374
 375 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66P)
 376 struct alpha_machine_vector eb66p_mv __initmv = {
 377         .vector_name            = "EB66+",
 378         DO_EV4_MMU,
 379         DO_DEFAULT_RTC,
 380         DO_LCA_IO,
 381         .machine_check          = lca_machine_check,
 382         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 383         .min_io_address         = DEFAULT_IO_BASE,
 384         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 385
 386         .nr_irqs                = 35,
 387         .device_interrupt       = cabriolet_device_interrupt,
 388
 389         .init_arch              = lca_init_arch,
 390         .init_irq               = cabriolet_init_irq,
 391         .init_rtc               = common_init_rtc,
 392         .init_pci               = cabriolet_init_pci,
 393         .pci_map_irq            = eb66p_map_irq,
 394         .pci_swizzle            = common_swizzle,
 395 };
 396 ALIAS_MV(eb66p)
 397 #endif
 398
 399 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LX164)
 400 struct alpha_machine_vector lx164_mv __initmv = {
 401         .vector_name            = "LX164",
 402         DO_EV5_MMU,
 403         DO_DEFAULT_RTC,
 404         DO_PYXIS_IO,
 405         .machine_check          = cia_machine_check,
 406         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 407         .min_io_address         = DEFAULT_IO_BASE,
 408         .min_mem_address        = DEFAULT_MEM_BASE,
 409         .pci_dac_offset         = PYXIS_DAC_OFFSET,
 410
 411         .nr_irqs                = 35,
 412         .device_interrupt       = cabriolet_device_interrupt,
 413
 414         .init_arch              = pyxis_init_arch,
 415         .init_irq               = cabriolet_init_irq,
 416         .init_rtc               = common_init_rtc,
 417         .init_pci               = alphapc164_init_pci,
 418         .kill_arch              = cia_kill_arch,
 419         .pci_map_irq            = alphapc164_map_irq,
 420         .pci_swizzle            = common_swizzle,
 421 };
 422 ALIAS_MV(lx164)
 423 #endif
 424
 425 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
 426 struct alpha_machine_vector pc164_mv __initmv = {
 427         .vector_name            = "PC164",
 428         DO_EV5_MMU,
 429         DO_DEFAULT_RTC,
 430         DO_CIA_IO,
 431         .machine_check          = cia_machine_check,
 432         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 433         .min_io_address         = DEFAULT_IO_BASE,
 434         .min_mem_address        = CIA_DEFAULT_MEM_BASE,
 435
 436         .nr_irqs                = 35,
 437         .device_interrupt       = pc164_device_interrupt,
 438
 439         .init_arch              = cia_init_arch,
 440         .init_irq               = pc164_init_irq,
 441         .init_rtc               = common_init_rtc,
 442         .init_pci               = alphapc164_init_pci,
 443         .kill_arch              = cia_kill_arch,
 444         .pci_map_irq            = alphapc164_map_irq,
 445         .pci_swizzle            = common_swizzle,
 446 };
 447 ALIAS_MV(pc164)
 448 #endif