release/src-rt-6.x.4708/linux/linux-2.6.36/arch/alpha/include/asm/core_apecs.h

   1 #ifndef __ALPHA_APECS__H__
   2 #define __ALPHA_APECS__H__
   3
   4 #include <linux/types.h>
   5 #include <asm/compiler.h>
   6
   7 /*
   8  * APECS is the internal name for the 2107x chipset which provides
   9  * memory controller and PCI access for the 21064 chip based systems.
  10  *
  11  * This file is based on:
  12  *
  13  * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets
  14  * Data Sheet
  15  *
  16  * EC-N0648-72
  17  *
  18  *
  19  * david.rusling@reo.mts.dec.com Initial Version.
  20  *
  21  */
  22
  23
  24 /*
  25  * 21071-DA Control and Status registers.
  26  * These are used for PCI memory access.
  27  */
  28 #define APECS_IOC_DCSR                  (IDENT_ADDR + 0x1A0000000UL)
  29 #define APECS_IOC_PEAR                  (IDENT_ADDR + 0x1A0000020UL)
  30 #define APECS_IOC_SEAR                  (IDENT_ADDR + 0x1A0000040UL)
  31 #define APECS_IOC_DR1                   (IDENT_ADDR + 0x1A0000060UL)
  32 #define APECS_IOC_DR2                   (IDENT_ADDR + 0x1A0000080UL)
  33 #define APECS_IOC_DR3                   (IDENT_ADDR + 0x1A00000A0UL)
  34
  35 #define APECS_IOC_TB1R                  (IDENT_ADDR + 0x1A00000C0UL)
  36 #define APECS_IOC_TB2R                  (IDENT_ADDR + 0x1A00000E0UL)
  37
  38 #define APECS_IOC_PB1R                  (IDENT_ADDR + 0x1A0000100UL)
  39 #define APECS_IOC_PB2R                  (IDENT_ADDR + 0x1A0000120UL)
  40
  41 #define APECS_IOC_PM1R                  (IDENT_ADDR + 0x1A0000140UL)
  42 #define APECS_IOC_PM2R                  (IDENT_ADDR + 0x1A0000160UL)
  43
  44 #define APECS_IOC_HAXR0                 (IDENT_ADDR + 0x1A0000180UL)
  45 #define APECS_IOC_HAXR1                 (IDENT_ADDR + 0x1A00001A0UL)
  46 #define APECS_IOC_HAXR2                 (IDENT_ADDR + 0x1A00001C0UL)
  47
  48 #define APECS_IOC_PMLT                  (IDENT_ADDR + 0x1A00001E0UL)
  49
  50 #define APECS_IOC_TLBTAG0               (IDENT_ADDR + 0x1A0000200UL)
  51 #define APECS_IOC_TLBTAG1               (IDENT_ADDR + 0x1A0000220UL)
  52 #define APECS_IOC_TLBTAG2               (IDENT_ADDR + 0x1A0000240UL)
  53 #define APECS_IOC_TLBTAG3               (IDENT_ADDR + 0x1A0000260UL)
  54 #define APECS_IOC_TLBTAG4               (IDENT_ADDR + 0x1A0000280UL)
  55 #define APECS_IOC_TLBTAG5               (IDENT_ADDR + 0x1A00002A0UL)
  56 #define APECS_IOC_TLBTAG6               (IDENT_ADDR + 0x1A00002C0UL)
  57 #define APECS_IOC_TLBTAG7               (IDENT_ADDR + 0x1A00002E0UL)
  58
  59 #define APECS_IOC_TLBDATA0              (IDENT_ADDR + 0x1A0000300UL)
  60 #define APECS_IOC_TLBDATA1              (IDENT_ADDR + 0x1A0000320UL)
  61 #define APECS_IOC_TLBDATA2              (IDENT_ADDR + 0x1A0000340UL)
  62 #define APECS_IOC_TLBDATA3              (IDENT_ADDR + 0x1A0000360UL)
  63 #define APECS_IOC_TLBDATA4              (IDENT_ADDR + 0x1A0000380UL)
  64 #define APECS_IOC_TLBDATA5              (IDENT_ADDR + 0x1A00003A0UL)
  65 #define APECS_IOC_TLBDATA6              (IDENT_ADDR + 0x1A00003C0UL)
  66 #define APECS_IOC_TLBDATA7              (IDENT_ADDR + 0x1A00003E0UL)
  67
  68 #define APECS_IOC_TBIA                  (IDENT_ADDR + 0x1A0000400UL)
  69
  70
  71 /*
  72  * 21071-CA Control and Status registers.
  73  * These are used to program memory timing,
  74  *  configure memory and initialise the B-Cache.
  75  */
  76 #define APECS_MEM_GCR                   (IDENT_ADDR + 0x180000000UL)
  77 #define APECS_MEM_EDSR                  (IDENT_ADDR + 0x180000040UL)
  78 #define APECS_MEM_TAR                   (IDENT_ADDR + 0x180000060UL)
  79 #define APECS_MEM_ELAR                  (IDENT_ADDR + 0x180000080UL)
  80 #define APECS_MEM_EHAR                  (IDENT_ADDR + 0x1800000a0UL)
  81 #define APECS_MEM_SFT_RST               (IDENT_ADDR + 0x1800000c0UL)
  82 #define APECS_MEM_LDxLAR                (IDENT_ADDR + 0x1800000e0UL)
  83 #define APECS_MEM_LDxHAR                (IDENT_ADDR + 0x180000100UL)
  84 #define APECS_MEM_GTR                   (IDENT_ADDR + 0x180000200UL)
  85 #define APECS_MEM_RTR                   (IDENT_ADDR + 0x180000220UL)
  86 #define APECS_MEM_VFPR                  (IDENT_ADDR + 0x180000240UL)
  87 #define APECS_MEM_PDLDR                 (IDENT_ADDR + 0x180000260UL)
  88 #define APECS_MEM_PDhDR                 (IDENT_ADDR + 0x180000280UL)
  89
  90 /* Bank x Base Address Register */
  91 #define APECS_MEM_B0BAR                 (IDENT_ADDR + 0x180000800UL)
  92 #define APECS_MEM_B1BAR                 (IDENT_ADDR + 0x180000820UL)
  93 #define APECS_MEM_B2BAR                 (IDENT_ADDR + 0x180000840UL)
  94 #define APECS_MEM_B3BAR                 (IDENT_ADDR + 0x180000860UL)
  95 #define APECS_MEM_B4BAR                 (IDENT_ADDR + 0x180000880UL)
  96 #define APECS_MEM_B5BAR                 (IDENT_ADDR + 0x1800008A0UL)
  97 #define APECS_MEM_B6BAR                 (IDENT_ADDR + 0x1800008C0UL)
  98 #define APECS_MEM_B7BAR                 (IDENT_ADDR + 0x1800008E0UL)
  99 #define APECS_MEM_B8BAR                 (IDENT_ADDR + 0x180000900UL)
 100
 101 /* Bank x Configuration Register */
 102 #define APECS_MEM_B0BCR                 (IDENT_ADDR + 0x180000A00UL)
 103 #define APECS_MEM_B1BCR                 (IDENT_ADDR + 0x180000A20UL)
 104 #define APECS_MEM_B2BCR                 (IDENT_ADDR + 0x180000A40UL)
 105 #define APECS_MEM_B3BCR                 (IDENT_ADDR + 0x180000A60UL)
 106 #define APECS_MEM_B4BCR                 (IDENT_ADDR + 0x180000A80UL)
 107 #define APECS_MEM_B5BCR                 (IDENT_ADDR + 0x180000AA0UL)
 108 #define APECS_MEM_B6BCR                 (IDENT_ADDR + 0x180000AC0UL)
 109 #define APECS_MEM_B7BCR                 (IDENT_ADDR + 0x180000AE0UL)
 110 #define APECS_MEM_B8BCR                 (IDENT_ADDR + 0x180000B00UL)
 111
 112 /* Bank x Timing Register A */
 113 #define APECS_MEM_B0TRA                 (IDENT_ADDR + 0x180000C00UL)
 114 #define APECS_MEM_B1TRA                 (IDENT_ADDR + 0x180000C20UL)
 115 #define APECS_MEM_B2TRA                 (IDENT_ADDR + 0x180000C40UL)
 116 #define APECS_MEM_B3TRA                 (IDENT_ADDR + 0x180000C60UL)
 117 #define APECS_MEM_B4TRA                 (IDENT_ADDR + 0x180000C80UL)
 118 #define APECS_MEM_B5TRA                 (IDENT_ADDR + 0x180000CA0UL)
 119 #define APECS_MEM_B6TRA                 (IDENT_ADDR + 0x180000CC0UL)
 120 #define APECS_MEM_B7TRA                 (IDENT_ADDR + 0x180000CE0UL)
 121 #define APECS_MEM_B8TRA                 (IDENT_ADDR + 0x180000D00UL)
 122
 123 /* Bank x Timing Register B */
 124 #define APECS_MEM_B0TRB                 (IDENT_ADDR + 0x180000E00UL)
 125 #define APECS_MEM_B1TRB                 (IDENT_ADDR + 0x180000E20UL)
 126 #define APECS_MEM_B2TRB                 (IDENT_ADDR + 0x180000E40UL)
 127 #define APECS_MEM_B3TRB                 (IDENT_ADDR + 0x180000E60UL)
 128 #define APECS_MEM_B4TRB                 (IDENT_ADDR + 0x180000E80UL)
 129 #define APECS_MEM_B5TRB                 (IDENT_ADDR + 0x180000EA0UL)
 130 #define APECS_MEM_B6TRB                 (IDENT_ADDR + 0x180000EC0UL)
 131 #define APECS_MEM_B7TRB                 (IDENT_ADDR + 0x180000EE0UL)
 132 #define APECS_MEM_B8TRB                 (IDENT_ADDR + 0x180000F00UL)
 133
 134
 135 /*
 136  * Memory spaces:
 137  */
 138 #define APECS_IACK_SC                   (IDENT_ADDR + 0x1b0000000UL)
 139 #define APECS_CONF                      (IDENT_ADDR + 0x1e0000000UL)
 140 #define APECS_IO                        (IDENT_ADDR + 0x1c0000000UL)
 141 #define APECS_SPARSE_MEM                (IDENT_ADDR + 0x200000000UL)
 142 #define APECS_DENSE_MEM                 (IDENT_ADDR + 0x300000000UL)
 143
 144
 145 /*
 146  * Bit definitions for I/O Controller status register 0:
 147  */
 148 #define APECS_IOC_STAT0_CMD             0xf
 149 #define APECS_IOC_STAT0_ERR             (1<<4)
 150 #define APECS_IOC_STAT0_LOST            (1<<5)
 151 #define APECS_IOC_STAT0_THIT            (1<<6)
 152 #define APECS_IOC_STAT0_TREF            (1<<7)
 153 #define APECS_IOC_STAT0_CODE_SHIFT      8
 154 #define APECS_IOC_STAT0_CODE_MASK       0x7
 155 #define APECS_IOC_STAT0_P_NBR_SHIFT     13
 156 #define APECS_IOC_STAT0_P_NBR_MASK      0x7ffff
 157
 158 #define APECS_HAE_ADDRESS               APECS_IOC_HAXR1
 159
 160
 161 /*
 162  * Data structure for handling APECS machine checks:
 163  */
 164
 165 struct el_apecs_mikasa_sysdata_mcheck
 166 {
 167         unsigned long coma_gcr;
 168         unsigned long coma_edsr;
 169         unsigned long coma_ter;
 170         unsigned long coma_elar;
 171         unsigned long coma_ehar;
 172         unsigned long coma_ldlr;
 173         unsigned long coma_ldhr;
 174         unsigned long coma_base0;
 175         unsigned long coma_base1;
 176         unsigned long coma_base2;
 177         unsigned long coma_base3;
 178         unsigned long coma_cnfg0;
 179         unsigned long coma_cnfg1;
 180         unsigned long coma_cnfg2;
 181         unsigned long coma_cnfg3;
 182         unsigned long epic_dcsr;
 183         unsigned long epic_pear;
 184         unsigned long epic_sear;
 185         unsigned long epic_tbr1;
 186         unsigned long epic_tbr2;
 187         unsigned long epic_pbr1;
 188         unsigned long epic_pbr2;
 189         unsigned long epic_pmr1;
 190         unsigned long epic_pmr2;
 191         unsigned long epic_harx1;
 192         unsigned long epic_harx2;
 193         unsigned long epic_pmlt;
 194         unsigned long epic_tag0;
 195         unsigned long epic_tag1;
 196         unsigned long epic_tag2;
 197         unsigned long epic_tag3;
 198         unsigned long epic_tag4;
 199         unsigned long epic_tag5;
 200         unsigned long epic_tag6;
 201         unsigned long epic_tag7;
 202         unsigned long epic_data0;
 203         unsigned long epic_data1;
 204         unsigned long epic_data2;
 205         unsigned long epic_data3;
 206         unsigned long epic_data4;
 207         unsigned long epic_data5;
 208         unsigned long epic_data6;
 209         unsigned long epic_data7;
 210
 211         unsigned long pceb_vid;
 212         unsigned long pceb_did;
 213         unsigned long pceb_revision;
 214         unsigned long pceb_command;
 215         unsigned long pceb_status;
 216         unsigned long pceb_latency;
 217         unsigned long pceb_control;
 218         unsigned long pceb_arbcon;
 219         unsigned long pceb_arbpri;
 220
 221         unsigned long esc_id;
 222         unsigned long esc_revision;
 223         unsigned long esc_int0;
 224         unsigned long esc_int1;
 225         unsigned long esc_elcr0;
 226         unsigned long esc_elcr1;
 227         unsigned long esc_last_eisa;
 228         unsigned long esc_nmi_stat;
 229
 230         unsigned long pci_ir;
 231         unsigned long pci_imr;
 232         unsigned long svr_mgr;
 233 };
 234
 235 /* This for the normal APECS machines.  */
 236 struct el_apecs_sysdata_mcheck
 237 {
 238         unsigned long coma_gcr;
 239         unsigned long coma_edsr;
 240         unsigned long coma_ter;
 241         unsigned long coma_elar;
 242         unsigned long coma_ehar;
 243         unsigned long coma_ldlr;
 244         unsigned long coma_ldhr;
 245         unsigned long coma_base0;
 246         unsigned long coma_base1;
 247         unsigned long coma_base2;
 248         unsigned long coma_cnfg0;
 249         unsigned long coma_cnfg1;
 250         unsigned long coma_cnfg2;
 251         unsigned long epic_dcsr;
 252         unsigned long epic_pear;
 253         unsigned long epic_sear;
 254         unsigned long epic_tbr1;
 255         unsigned long epic_tbr2;
 256         unsigned long epic_pbr1;
 257         unsigned long epic_pbr2;
 258         unsigned long epic_pmr1;
 259         unsigned long epic_pmr2;
 260         unsigned long epic_harx1;
 261         unsigned long epic_harx2;
 262         unsigned long epic_pmlt;
 263         unsigned long epic_tag0;
 264         unsigned long epic_tag1;
 265         unsigned long epic_tag2;
 266         unsigned long epic_tag3;
 267         unsigned long epic_tag4;
 268         unsigned long epic_tag5;
 269         unsigned long epic_tag6;
 270         unsigned long epic_tag7;
 271         unsigned long epic_data0;
 272         unsigned long epic_data1;
 273         unsigned long epic_data2;
 274         unsigned long epic_data3;
 275         unsigned long epic_data4;
 276         unsigned long epic_data5;
 277         unsigned long epic_data6;
 278         unsigned long epic_data7;
 279 };
 280
 281 struct el_apecs_procdata
 282 {
 283         unsigned long paltemp[32];  /* PAL TEMP REGS. */
 284         /* EV4-specific fields */
 285         unsigned long exc_addr;     /* Address of excepting instruction. */
 286         unsigned long exc_sum;      /* Summary of arithmetic traps. */
 287         unsigned long exc_mask;     /* Exception mask (from exc_sum). */
 288         unsigned long iccsr;        /* IBox hardware enables. */
 289         unsigned long pal_base;     /* Base address for PALcode. */
 290         unsigned long hier;         /* Hardware Interrupt Enable. */
 291         unsigned long hirr;         /* Hardware Interrupt Request. */
 292         unsigned long csr;          /* D-stream fault info. */
 293         unsigned long dc_stat;      /* D-cache status (ECC/Parity Err). */
 294         unsigned long dc_addr;      /* EV3 Phys Addr for ECC/DPERR. */
 295         unsigned long abox_ctl;     /* ABox Control Register. */
 296         unsigned long biu_stat;     /* BIU Status. */
 297         unsigned long biu_addr;     /* BUI Address. */
 298         unsigned long biu_ctl;      /* BIU Control. */
 299         unsigned long fill_syndrome;/* For correcting ECC errors. */
 300         unsigned long fill_addr;    /* Cache block which was being read */
 301         unsigned long va;           /* Effective VA of fault or miss. */
 302         unsigned long bc_tag;       /* Backup Cache Tag Probe Results.*/
 303 };
 304
 305
 306 #ifdef __KERNEL__
 307
 308 #ifndef __EXTERN_INLINE
 309 #define __EXTERN_INLINE extern inline
 310 #define __IO_EXTERN_INLINE
 311 #endif
 312
 313 /*
 314  * I/O functions:
 315  *
 316  * Unlike Jensen, the APECS machines have no concept of local
 317  * I/O---everything goes over the PCI bus.
 318  *
 319  * There is plenty room for optimization here.  In particular,
 320  * the Alpha's insb/insw/extb/extw should be useful in moving
 321  * data to/from the right byte-lanes.
 322  */
 323
 324 #define vip     volatile int __force *
 325 #define vuip    volatile unsigned int __force *
 326 #define vulp    volatile unsigned long __force *
 327
 328 #define APECS_SET_HAE                                           \
 329         do {                                                    \
 330                 if (addr >= (1UL << 24)) {                      \
 331                         unsigned long msb = addr & 0xf8000000;  \
 332                         addr -= msb;                            \
 333                         set_hae(msb);                           \
 334                 }                                               \
 335         } while (0)
 336
 337 __EXTERN_INLINE unsigned int apecs_ioread8(void __iomem *xaddr)
 338 {
 339         unsigned long addr = (unsigned long) xaddr;
 340         unsigned long result, base_and_type;
 341
 342         if (addr >= APECS_DENSE_MEM) {
 343                 addr -= APECS_DENSE_MEM;
 344                 APECS_SET_HAE;
 345                 base_and_type = APECS_SPARSE_MEM + 0x00;
 346         } else {
 347                 addr -= APECS_IO;
 348                 base_and_type = APECS_IO + 0x00;
 349         }
 350
 351         result = *(vip) ((addr << 5) + base_and_type);
 352         return __kernel_extbl(result, addr & 3);
 353 }
 354
 355 __EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr)
 356 {
 357         unsigned long addr = (unsigned long) xaddr;
 358         unsigned long w, base_and_type;
 359
 360         if (addr >= APECS_DENSE_MEM) {
 361                 addr -= APECS_DENSE_MEM;
 362                 APECS_SET_HAE;
 363                 base_and_type = APECS_SPARSE_MEM + 0x00;
 364         } else {
 365                 addr -= APECS_IO;
 366                 base_and_type = APECS_IO + 0x00;
 367         }
 368
 369         w = __kernel_insbl(b, addr & 3);
 370         *(vuip) ((addr << 5) + base_and_type) = w;
 371 }
 372
 373 __EXTERN_INLINE unsigned int apecs_ioread16(void __iomem *xaddr)
 374 {
 375         unsigned long addr = (unsigned long) xaddr;
 376         unsigned long result, base_and_type;
 377
 378         if (addr >= APECS_DENSE_MEM) {
 379                 addr -= APECS_DENSE_MEM;
 380                 APECS_SET_HAE;
 381                 base_and_type = APECS_SPARSE_MEM + 0x08;
 382         } else {
 383                 addr -= APECS_IO;
 384                 base_and_type = APECS_IO + 0x08;
 385         }
 386
 387         result = *(vip) ((addr << 5) + base_and_type);
 388         return __kernel_extwl(result, addr & 3);
 389 }
 390
 391 __EXTERN_INLINE void apecs_iowrite16(u16 b, void __iomem *xaddr)
 392 {
 393         unsigned long addr = (unsigned long) xaddr;
 394         unsigned long w, base_and_type;
 395
 396         if (addr >= APECS_DENSE_MEM) {
 397                 addr -= APECS_DENSE_MEM;
 398                 APECS_SET_HAE;
 399                 base_and_type = APECS_SPARSE_MEM + 0x08;
 400         } else {
 401                 addr -= APECS_IO;
 402                 base_and_type = APECS_IO + 0x08;
 403         }
 404
 405         w = __kernel_inswl(b, addr & 3);
 406         *(vuip) ((addr << 5) + base_and_type) = w;
 407 }
 408
 409 __EXTERN_INLINE unsigned int apecs_ioread32(void __iomem *xaddr)
 410 {
 411         unsigned long addr = (unsigned long) xaddr;
 412         if (addr < APECS_DENSE_MEM)
 413                 addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
 414         return *(vuip)addr;
 415 }
 416
 417 __EXTERN_INLINE void apecs_iowrite32(u32 b, void __iomem *xaddr)
 418 {
 419         unsigned long addr = (unsigned long) xaddr;
 420         if (addr < APECS_DENSE_MEM)
 421                 addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
 422         *(vuip)addr = b;
 423 }
 424
 425 __EXTERN_INLINE void __iomem *apecs_ioportmap(unsigned long addr)
 426 {
 427         return (void __iomem *)(addr + APECS_IO);
 428 }
 429
 430 __EXTERN_INLINE void __iomem *apecs_ioremap(unsigned long addr,
 431                                             unsigned long size)
 432 {
 433         return (void __iomem *)(addr + APECS_DENSE_MEM);
 434 }
 435
 436 __EXTERN_INLINE int apecs_is_ioaddr(unsigned long addr)
 437 {
 438         return addr >= IDENT_ADDR + 0x180000000UL;
 439 }
 440
 441 __EXTERN_INLINE int apecs_is_mmio(const volatile void __iomem *addr)
 442 {
 443         return (unsigned long)addr >= APECS_DENSE_MEM;
 444 }
 445
 446 #undef APECS_SET_HAE
 447
 448 #undef vip
 449 #undef vuip
 450 #undef vulp
 451
 452 #undef __IO_PREFIX
 453 #define __IO_PREFIX             apecs
 454 #define apecs_trivial_io_bw     0
 455 #define apecs_trivial_io_lq     0
 456 #define apecs_trivial_rw_bw     2
 457 #define apecs_trivial_rw_lq     1
 458 #define apecs_trivial_iounmap   1
 459 #include <asm/io_trivial.h>
 460
 461 #ifdef __IO_EXTERN_INLINE
 462 #undef __EXTERN_INLINE
 463 #undef __IO_EXTERN_INLINE
 464 #endif
 465
 466 #endif /* __KERNEL__ */
 467
 468 #endif /* __ALPHA_APECS__H__ */