GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / include / usbrdl.h
blob0efa255578d2ec49800de9ca71bf248fd6968eea
1 /*
2 * Broadcom USB remote download definitions
4 * Copyright (C) 2012, Broadcom Corporation
5 * All Rights Reserved.
6 *
7 * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
8 * the contents of this file may not be disclosed to third parties, copied
9 * or duplicated in any form, in whole or in part, without the prior
10 * written permission of Broadcom Corporation.
12 * $Id: usbrdl.h 314495 2012-02-12 07:56:39Z $
15 #ifndef _USB_RDL_H
16 #define _USB_RDL_H
18 /* Control messages: bRequest values */
19 #define DL_GETSTATE 0 /* returns the rdl_state_t struct */
20 #define DL_CHECK_CRC 1 /* currently unused */
21 #define DL_GO 2 /* execute downloaded image */
22 #define DL_START 3 /* initialize dl state */
23 #define DL_REBOOT 4 /* reboot the device in 2 seconds */
24 #define DL_GETVER 5 /* returns the bootrom_id_t struct */
25 #define DL_GO_PROTECTED 6 /* execute the downloaded code and set reset event
26 * to occur in 2 seconds. It is the responsibility
27 * of the downloaded code to clear this event
29 #define DL_EXEC 7 /* jump to a supplied address */
30 #define DL_RESETCFG 8 /* To support single enum on dongle
31 * - Not used by bootloader
33 #define DL_DEFER_RESP_OK 9 /* Potentially defer the response to setup
34 * if resp unavailable
37 #define DL_HWCMD_MASK 0xfc /* Mask for hardware read commands: */
38 #define DL_RDHW 0x10 /* Read a hardware address (Ctl-in) */
39 #define DL_RDHW32 0x10 /* Read a 32 bit word */
40 #define DL_RDHW16 0x11 /* Read 16 bits */
41 #define DL_RDHW8 0x12 /* Read an 8 bit byte */
42 #define DL_WRHW 0x14 /* Write a hardware address (Ctl-out) */
43 #define DL_WRHW_BLK 0x13 /* Block write to hardware access */
45 #define DL_CMD_RDHW 1 /* read data from a backplane address */
46 #define DL_CMD_WRHW 2 /* write data to a backplane address */
48 #ifndef LINUX_POSTMOGRIFY_REMOVAL
49 #define DL_JTCONF 0x15 /* Get JTAG configuration (Ctl_in)
50 * Set JTAG configuration (Ctl-out)
52 #define DL_JTON 0x16 /* Turn on jtag master (Ctl-in) */
53 #define DL_JTOFF 0x17 /* Turn on jtag master (Ctl-in) */
54 #define DL_RDRJT 0x18 /* Read a JTAG register (Ctl-in) */
55 #define DL_WRJT 0x19 /* Write a hardware address over JTAG (Ctl/Bulk-out) */
56 #define DL_WRRJT 0x1a /* Write a JTAG register (Ctl/Bulk-out) */
57 #define DL_JTRST 0x1b /* Reset jtag fsm on jtag DUT (Ctl-in) */
59 #define DL_RDJT 0x1c /* Read a hardware address over JTAG (Ctl-in) */
60 #define DL_RDJT32 0x1c /* Read 32 bits */
61 #define DL_RDJT16 0x1e /* Read 16 bits (sz = 4 - low bits) */
62 #define DL_RDJT8 0x1f /* Read 8 bits */
64 #define DL_MRDJT 0x20 /* Multiple read over JTAG (Ctl-out+Bulk-in) */
65 #define DL_MRDJT32 0x20 /* M-read 32 bits */
66 #define DL_MRDJT16 0x22 /* M-read 16 bits (sz = 4 - low bits) */
67 #define DL_MRDJT6 0x23 /* M-read 8 bits */
68 #define DL_MRDIJT 0x24 /* M-read over JTAG (Ctl-out+Bulk-in) with auto-increment */
69 #define DL_MRDIJT32 0x24 /* M-read 32 bits w/ai */
70 #define DL_MRDIJT16 0x26 /* M-read 16 bits w/ai (sz = 4 - low bits) */
71 #define DL_MRDIJT8 0x27 /* M-read 8 bits w/ai */
72 #define DL_MRDDJT 0x28 /* M-read over JTAG (Ctl-out+Bulk-in) with auto-decrement */
73 #define DL_MRDDJT32 0x28 /* M-read 32 bits w/ad */
74 #define DL_MRDDJT16 0x2a /* M-read 16 bits w/ad (sz = 4 - low bits) */
75 #define DL_MRDDJT8 0x2b /* M-read 8 bits w/ad */
76 #define DL_MWRJT 0x2c /* Multiple write over JTAG (Bulk-out) */
77 #define DL_MWRIJT 0x2d /* With auto-increment */
78 #define DL_MWRDJT 0x2e /* With auto-decrement */
79 #define DL_VRDJT 0x2f /* Vector read over JTAG (Bulk-out+Bulk-in) */
80 #define DL_VWRJT 0x30 /* Vector write over JTAG (Bulk-out+Bulk-in) */
81 #define DL_SCJT 0x31 /* Jtag scan (Bulk-out+Bulk-in) */
83 #define DL_CFRD 0x33 /* Reserved for dmamem use */
84 #define DL_CFWR 0x34 /* Reserved for dmamem use */
85 #define DL_GET_NVRAM 0x35 /* Query nvram parameter */
87 #define DL_DBGTRIG 0xFF /* Trigger bRequest type to aid debug */
89 #define DL_JTERROR 0x80000000
90 #endif /* LINUX_POSTMOGRIFY_REMOVAL */
92 /* states */
93 #define DL_WAITING 0 /* waiting to rx first pkt that includes the hdr info */
94 #define DL_READY 1 /* hdr was good, waiting for more of the compressed image */
95 #define DL_BAD_HDR 2 /* hdr was corrupted */
96 #define DL_BAD_CRC 3 /* compressed image was corrupted */
97 #define DL_RUNNABLE 4 /* download was successful, waiting for go cmd */
98 #define DL_START_FAIL 5 /* failed to initialize correctly */
99 #define DL_NVRAM_TOOBIG 6 /* host specified nvram data exceeds DL_NVRAM value */
100 #define DL_IMAGE_TOOBIG 7 /* download image too big (exceeds DATA_START for rdl) */
102 #define TIMEOUT 5000 /* Timeout for usb commands */
104 struct bcm_device_id {
105 char *name;
106 uint32 vend;
107 uint32 prod;
110 typedef struct {
111 uint32 state;
112 uint32 bytes;
113 } rdl_state_t;
115 typedef struct {
116 uint32 chip; /* Chip id */
117 uint32 chiprev; /* Chip rev */
118 uint32 ramsize; /* Size of RAM */
119 uint32 remapbase; /* Current remap base address */
120 uint32 boardtype; /* Type of board */
121 uint32 boardrev; /* Board revision */
122 } bootrom_id_t;
124 /* struct for backplane & jtag accesses */
125 typedef struct {
126 uint32 cmd; /* tag to identify the cmd */
127 uint32 addr; /* backplane address for write */
128 uint32 len; /* length of data: 1, 2, 4 bytes */
129 uint32 data; /* data to write */
130 } hwacc_t;
132 /* struct for backplane */
133 typedef struct {
134 uint32 cmd; /* tag to identify the cmd */
135 uint32 addr; /* backplane address for write */
136 uint32 len; /* length of data: 1, 2, 4 bytes */
137 uint8 data[1]; /* data to write */
138 } hwacc_blk_t;
140 #ifndef LINUX_POSTMOGRIFY_REMOVAL
141 typedef struct {
142 uint32 chip; /* Chip id */
143 uint32 chiprev; /* Chip rev */
144 uint32 ccrev; /* Chipcommon core rev */
145 uint32 siclock; /* Backplane clock */
146 } jtagd_id_t;
148 /* Jtag configuration structure */
149 typedef struct {
150 uint32 cmd; /* tag to identify the cmd */
151 uint8 clkd; /* Jtag clock divisor */
152 uint8 disgpio; /* Gpio to disable external driver */
153 uint8 irsz; /* IR size for readreg/writereg */
154 uint8 drsz; /* DR size for readreg/writereg */
156 uint8 bigend; /* Big endian */
157 uint8 mode; /* Current mode */
158 uint16 delay; /* Delay between jtagm "simple commands" */
160 uint32 retries; /* Number of retries for jtagm operations */
161 uint32 ctrl; /* Jtag control reg copy */
162 uint32 ir_lvbase; /* Bits to add to IR values in LV tap */
163 uint32 dretries; /* Number of retries for dma operations */
164 } jtagconf_t;
166 /* struct for jtag scan */
167 #define MAX_USB_IR_BITS 256
168 #define MAX_USB_DR_BITS 3072
169 #define USB_IR_WORDS (MAX_USB_IR_BITS / 32)
170 #define USB_DR_WORDS (MAX_USB_DR_BITS / 32)
171 typedef struct {
172 uint32 cmd; /* tag to identify the cmd */
173 uint32 irsz; /* IR size in bits */
174 uint32 drsz; /* DR size in bits */
175 uint32 ts; /* Terminal state (def, pause, rti) */
176 uint32 data[USB_IR_WORDS + USB_DR_WORDS]; /* IR & DR data */
177 } scjt_t;
178 #endif /* LINUX_POSTMOGRIFY_REMOVAL */
180 /* struct for querying nvram params from bootloader */
181 #define QUERY_STRING_MAX 32
182 typedef struct {
183 uint32 cmd; /* tag to identify the cmd */
184 char var[QUERY_STRING_MAX]; /* param name */
185 } nvparam_t;
187 typedef void (*exec_fn_t)(void *sih);
189 #define USB_CTRL_IN (USB_TYPE_VENDOR | 0x80 | USB_RECIP_INTERFACE)
190 #define USB_CTRL_OUT (USB_TYPE_VENDOR | 0 | USB_RECIP_INTERFACE)
192 #define USB_CTRL_EP_TIMEOUT 500 /* Timeout used in USB control_msg transactions. */
194 #define RDL_CHUNK 1500 /* size of each dl transfer */
196 /* bootloader makes special use of trx header "offsets" array */
197 #define TRX_OFFSETS_DLFWLEN_IDX 0 /* Size of the fw; used in uncompressed case */
198 #define TRX_OFFSETS_JUMPTO_IDX 1 /* RAM address for jumpto after download */
199 #define TRX_OFFSETS_NVM_LEN_IDX 2 /* Length of appended NVRAM data */
200 #ifdef BCMTRXV2
201 /* The NVRAM region part of trx will be digitally signed in SDR image,
202 * so is the need for new cfg region which could pass parameters
203 * which dones not need to be digitally signed
205 #define TRX_OFFSETS_DSG_LEN_IDX 3 /* Length of digital signature for the first image */
206 #define TRX_OFFSETS_CFG_LEN_IDX 4 /* Length of config region, which is not digitally signed */
207 #endif /* BCMTRXV2 */
209 #define TRX_OFFSETS_DLBASE_IDX 0 /* RAM start address for download */
211 #endif /* _USB_RDL_H */