release/src-rt-6.x.4708/include/sbsocram.h

   1 /*
   2  * BCM47XX Sonics SiliconBackplane embedded ram core
   3  *
   4  * Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id: sbsocram.h 271781 2011-07-13 20:00:06Z $
  19  */
  20
  21 #ifndef _SBSOCRAM_H
  22 #define _SBSOCRAM_H
  23
  24 #ifndef _LANGUAGE_ASSEMBLY
  25
  26 /* cpp contortions to concatenate w/arg prescan */
  27 #ifndef PAD
  28 #define _PADLINE(line)  pad ## line
  29 #define _XSTR(line)     _PADLINE(line)
  30 #define PAD             _XSTR(__LINE__)
  31 #endif  /* PAD */
  32
  33 /* Memcsocram core registers */
  34 typedef volatile struct sbsocramregs {
  35         uint32  coreinfo;
  36         uint32  bwalloc;
  37         uint32  extracoreinfo;
  38         uint32  biststat;
  39         uint32  bankidx;
  40         uint32  standbyctrl;
  41
  42         uint32  errlogstatus;   /* rev 6 */
  43         uint32  errlogaddr;     /* rev 6 */
  44         /* used for patching rev 3 & 5 */
  45         uint32  cambankidx;
  46         uint32  cambankstandbyctrl;
  47         uint32  cambankpatchctrl;
  48         uint32  cambankpatchtblbaseaddr;
  49         uint32  cambankcmdreg;
  50         uint32  cambankdatareg;
  51         uint32  cambankmaskreg;
  52         uint32  PAD[1];
  53         uint32  bankinfo;       /* corev 8 */
  54         uint32  PAD[15];
  55         uint32  extmemconfig;
  56         uint32  extmemparitycsr;
  57         uint32  extmemparityerrdata;
  58         uint32  extmemparityerrcnt;
  59         uint32  extmemwrctrlandsize;
  60         uint32  PAD[84];
  61         uint32  workaround;
  62         uint32  pwrctl;         /* corerev >= 2 */
  63         uint32  PAD[133];
  64         uint32  sr_control;     /* corerev >= 15 */
  65         uint32  sr_status;      /* corerev >= 15 */
  66         uint32  sr_address;     /* corerev >= 15 */
  67         uint32  sr_data;        /* corerev >= 15 */
  68 } sbsocramregs_t;
  69
  70 #endif  /* _LANGUAGE_ASSEMBLY */
  71
  72 /* Register offsets */
  73 #define SR_COREINFO             0x00
  74 #define SR_BWALLOC              0x04
  75 #define SR_BISTSTAT             0x0c
  76 #define SR_BANKINDEX            0x10
  77 #define SR_BANKSTBYCTL          0x14
  78 #define SR_PWRCTL               0x1e8
  79
  80 /* Coreinfo register */
  81 #define SRCI_PT_MASK            0x00070000      /* corerev >= 6; port type[18:16] */
  82 #define SRCI_PT_SHIFT           16
  83 /* port types : SRCI_PT_<processorPT>_<backplanePT> */
  84 #define SRCI_PT_OCP_OCP         0
  85 #define SRCI_PT_AXI_OCP         1
  86 #define SRCI_PT_ARM7AHB_OCP     2
  87 #define SRCI_PT_CM3AHB_OCP      3
  88 #define SRCI_PT_AXI_AXI         4
  89 #define SRCI_PT_AHB_AXI         5
  90 /* corerev >= 3 */
  91 #define SRCI_LSS_MASK           0x00f00000
  92 #define SRCI_LSS_SHIFT          20
  93 #define SRCI_LRS_MASK           0x0f000000
  94 #define SRCI_LRS_SHIFT          24
  95
  96 /* In corerev 0, the memory size is 2 to the power of the
  97  * base plus 16 plus to the contents of the memsize field plus 1.
  98  */
  99 #define SRCI_MS0_MASK           0xf
 100 #define SR_MS0_BASE             16
 101
 102 /*
 103  * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
 104  * the memory size is number of banks times bank size.
 105  * The same applies to rom size.
 106  */
 107 #define SRCI_ROMNB_MASK         0xf000
 108 #define SRCI_ROMNB_SHIFT        12
 109 #define SRCI_ROMBSZ_MASK        0xf00
 110 #define SRCI_ROMBSZ_SHIFT       8
 111 #define SRCI_SRNB_MASK          0xf0
 112 #define SRCI_SRNB_SHIFT         4
 113 #define SRCI_SRBSZ_MASK         0xf
 114 #define SRCI_SRBSZ_SHIFT        0
 115
 116 #define SR_BSZ_BASE             14
 117
 118 /* Standby control register */
 119 #define SRSC_SBYOVR_MASK        0x80000000
 120 #define SRSC_SBYOVR_SHIFT       31
 121 #define SRSC_SBYOVRVAL_MASK     0x60000000
 122 #define SRSC_SBYOVRVAL_SHIFT    29
 123 #define SRSC_SBYEN_MASK         0x01000000      /* rev >= 3 */
 124 #define SRSC_SBYEN_SHIFT        24
 125
 126 /* Power control register */
 127 #define SRPC_PMU_STBYDIS_MASK   0x00000010      /* rev >= 3 */
 128 #define SRPC_PMU_STBYDIS_SHIFT  4
 129 #define SRPC_STBYOVRVAL_MASK    0x00000008
 130 #define SRPC_STBYOVRVAL_SHIFT   3
 131 #define SRPC_STBYOVR_MASK       0x00000007
 132 #define SRPC_STBYOVR_SHIFT      0
 133
 134 /* Extra core capability register */
 135 #define SRECC_NUM_BANKS_MASK   0x000000F0
 136 #define SRECC_NUM_BANKS_SHIFT  4
 137 #define SRECC_BANKSIZE_MASK    0x0000000F
 138 #define SRECC_BANKSIZE_SHIFT   0
 139
 140 #define SRECC_BANKSIZE(value)    (1 << (value))
 141
 142 /* CAM bank patch control */
 143 #define SRCBPC_PATCHENABLE 0x80000000
 144
 145 #define SRP_ADDRESS   0x0001FFFC
 146 #define SRP_VALID     0x8000
 147
 148 /* CAM bank command reg */
 149 #define SRCMD_WRITE  0x00020000
 150 #define SRCMD_READ   0x00010000
 151 #define SRCMD_DONE   0x80000000
 152
 153 #define SRCMD_DONE_DLY  1000
 154
 155 /* bankidx and bankinfo reg defines corerev >= 8 */
 156 #define SOCRAM_BANKINFO_SZMASK          0x7f
 157 #define SOCRAM_BANKIDX_ROM_MASK         0x100
 158
 159 #define SOCRAM_BANKIDX_MEMTYPE_SHIFT    8
 160 /* socram bankinfo memtype */
 161 #define SOCRAM_MEMTYPE_RAM              0
 162 #define SOCRAM_MEMTYPE_R0M              1
 163 #define SOCRAM_MEMTYPE_DEVRAM           2
 164
 165 #define SOCRAM_BANKINFO_REG             0x40
 166 #define SOCRAM_BANKIDX_REG              0x10
 167 #define SOCRAM_BANKINFO_STDBY_MASK      0x400
 168 #define SOCRAM_BANKINFO_STDBY_TIMER     0x800
 169
 170 /* bankinfo rev >= 10 */
 171 #define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT         13
 172 #define SOCRAM_BANKINFO_DEVRAMSEL_MASK          0x2000
 173 #define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT         14
 174 #define SOCRAM_BANKINFO_DEVRAMPRO_MASK          0x4000
 175 #define SOCRAM_BANKINFO_SLPSUPP_SHIFT           15
 176 #define SOCRAM_BANKINFO_SLPSUPP_MASK            0x8000
 177 #define SOCRAM_BANKINFO_RETNTRAM_SHIFT          16
 178 #define SOCRAM_BANKINFO_RETNTRAM_MASK           0x00010000
 179 #define SOCRAM_BANKINFO_PDASZ_SHIFT             17
 180 #define SOCRAM_BANKINFO_PDASZ_MASK              0x003E0000
 181 #define SOCRAM_BANKINFO_DEVRAMREMAP_SHIFT       24
 182 #define SOCRAM_BANKINFO_DEVRAMREMAP_MASK        0x01000000
 183
 184 /* extracoreinfo register */
 185 #define SOCRAM_DEVRAMBANK_MASK          0xF000
 186 #define SOCRAM_DEVRAMBANK_SHIFT         12
 187
 188 /* bank info to calculate bank size */
 189 #define   SOCRAM_BANKINFO_SZBASE          8192
 190 #define SOCRAM_BANKSIZE_SHIFT         13      /* SOCRAM_BANKINFO_SZBASE */
 191
 192
 193 #endif  /* _SBSOCRAM_H */