release/src-rt-6.x.4708/include/sbmemc.h

   1 /*
   2  * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
   3  *
   4  * Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id: sbmemc.h 241182 2011-02-17 21:50:03Z $
  19  */
  20
  21 #ifndef _SBMEMC_H
  22 #define _SBMEMC_H
  23
  24 #ifdef _LANGUAGE_ASSEMBLY
  25
  26 #define MEMC_CONTROL            0x00
  27 #define MEMC_CONFIG             0x04
  28 #define MEMC_REFRESH            0x08
  29 #define MEMC_BISTSTAT           0x0c
  30 #define MEMC_MODEBUF            0x10
  31 #define MEMC_BKCLS              0x14
  32 #define MEMC_PRIORINV           0x18
  33 #define MEMC_DRAMTIM            0x1c
  34 #define MEMC_INTSTAT            0x20
  35 #define MEMC_INTMASK            0x24
  36 #define MEMC_INTINFO            0x28
  37 #define MEMC_NCDLCTL            0x30
  38 #define MEMC_RDNCDLCOR          0x34
  39 #define MEMC_WRNCDLCOR          0x38
  40 #define MEMC_MISCDLYCTL         0x3c
  41 #define MEMC_DQSGATENCDL        0x40
  42 #define MEMC_SPARE              0x44
  43 #define MEMC_TPADDR             0x48
  44 #define MEMC_TPDATA             0x4c
  45 #define MEMC_BARRIER            0x50
  46 #define MEMC_CORE               0x54
  47
  48 #else   /* !_LANGUAGE_ASSEMBLY */
  49
  50 /* Sonics side: MEMC core registers */
  51 typedef volatile struct sbmemcregs {
  52         uint32  control;
  53         uint32  config;
  54         uint32  refresh;
  55         uint32  biststat;
  56         uint32  modebuf;
  57         uint32  bkcls;
  58         uint32  priorinv;
  59         uint32  dramtim;
  60         uint32  intstat;
  61         uint32  intmask;
  62         uint32  intinfo;
  63         uint32  reserved1;
  64         uint32  ncdlctl;
  65         uint32  rdncdlcor;
  66         uint32  wrncdlcor;
  67         uint32  miscdlyctl;
  68         uint32  dqsgatencdl;
  69         uint32  spare;
  70         uint32  tpaddr;
  71         uint32  tpdata;
  72         uint32  barrier;
  73         uint32  core;
  74 } sbmemcregs_t;
  75
  76 #endif  /* _LANGUAGE_ASSEMBLY */
  77
  78 /* MEMC Core Init values (OCP ID 0x80f) */
  79
  80 /* For sdr: */
  81 #define MEMC_SD_CONFIG_INIT     0x00048000
  82 #define MEMC_SD_DRAMTIM2_INIT   0x000754d8
  83 #define MEMC_SD_DRAMTIM3_INIT   0x000754da
  84 #define MEMC_SD_RDNCDLCOR_INIT  0x00000000
  85 #define MEMC_SD_WRNCDLCOR_INIT  0x49351200
  86 #define MEMC_SD1_WRNCDLCOR_INIT 0x14500200      /* For corerev 1 (4712) */
  87 #define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
  88 #define MEMC_SD1_MISCDLYCTL_INIT 0x00021416     /* For corerev 1 (4712) */
  89 #define MEMC_SD_CONTROL_INIT0   0x00000002
  90 #define MEMC_SD_CONTROL_INIT1   0x00000008
  91 #define MEMC_SD_CONTROL_INIT2   0x00000004
  92 #define MEMC_SD_CONTROL_INIT3   0x00000010
  93 #define MEMC_SD_CONTROL_INIT4   0x00000001
  94 #define MEMC_SD_MODEBUF_INIT    0x00000000
  95 #define MEMC_SD_REFRESH_INIT    0x0000840f
  96
  97
  98 /* This is for SDRM8X8X4 */
  99 #define MEMC_SDR_INIT           0x0008
 100 #define MEMC_SDR_MODE           0x32
 101 #define MEMC_SDR_NCDL           0x00020032
 102 #define MEMC_SDR1_NCDL          0x0002020f      /* For corerev 1 (4712) */
 103
 104 /* For ddr: */
 105 #define MEMC_CONFIG_INIT        0x00048000
 106 #define MEMC_DRAMTIM2_INIT      0x000754d8
 107 #define MEMC_DRAMTIM25_INIT     0x000754d9
 108 #define MEMC_RDNCDLCOR_INIT     0x00000000
 109 #define MEMC_RDNCDLCOR_SIMINIT  0xf6f6f6f6      /* For hdl sim */
 110 #define MEMC_WRNCDLCOR_INIT     0x49351200
 111 #define MEMC_1_WRNCDLCOR_INIT   0x14500200
 112 #define MEMC_DQSGATENCDL_INIT   0x00030000
 113 #define MEMC_MISCDLYCTL_INIT    0x21061c1b
 114 #define MEMC_1_MISCDLYCTL_INIT  0x21021400
 115 #define MEMC_NCDLCTL_INIT       0x00002001
 116 #define MEMC_CONTROL_INIT0      0x00000002
 117 #define MEMC_CONTROL_INIT1      0x00000008
 118 #define MEMC_MODEBUF_INIT0      0x00004000
 119 #define MEMC_CONTROL_INIT2      0x00000010
 120 #define MEMC_MODEBUF_INIT1      0x00000100
 121 #define MEMC_CONTROL_INIT3      0x00000010
 122 #define MEMC_CONTROL_INIT4      0x00000008
 123 #define MEMC_REFRESH_INIT       0x0000840f
 124 #define MEMC_CONTROL_INIT5      0x00000004
 125 #define MEMC_MODEBUF_INIT2      0x00000000
 126 #define MEMC_CONTROL_INIT6      0x00000010
 127 #define MEMC_CONTROL_INIT7      0x00000001
 128
 129
 130 /* This is for DDRM16X16X2 */
 131 #define MEMC_DDR_INIT           0x0009
 132 #define MEMC_DDR_MODE           0x62
 133 #define MEMC_DDR_NCDL           0x0005050a
 134 #define MEMC_DDR1_NCDL          0x00000a0a      /* For corerev 1 (4712) */
 135
 136 /* mask for sdr/ddr calibration registers */
 137 #define MEMC_RDNCDLCOR_RD_MASK  0x000000ff
 138 #define MEMC_WRNCDLCOR_WR_MASK  0x000000ff
 139 #define MEMC_DQSGATENCDL_G_MASK 0x000000ff
 140
 141 /* masks for miscdlyctl registers */
 142 #define MEMC_MISC_SM_MASK       0x30000000
 143 #define MEMC_MISC_SM_SHIFT      28
 144 #define MEMC_MISC_SD_MASK       0x0f000000
 145 #define MEMC_MISC_SD_SHIFT      24
 146
 147 /* hw threshhold for calculating wr/rd for sdr memc */
 148 #define MEMC_CD_THRESHOLD       128
 149
 150 /* Low bit of init register says if memc is ddr or sdr */
 151 #define MEMC_CONFIG_DDR         0x00000001
 152
 153 #endif  /* _SBMEMC_H */