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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / include / qspi_core.h
blob3ee9efee4c07e55b12aaf653a392bb0761f7ef6d
1 /*
2 * qspi - Broadcom QSPI specific definitions
3 *
4 * Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * $Id: $
19 */
20
21 #ifndef _qspi_core_h_
22 #define _qspi_core_h_
23
24 /* cpp contortions to concatenate w/arg prescan */
25 #ifndef PAD
26 #define _PADLINE(line) pad ## line
27 #define _XSTR(line) _PADLINE(line)
28 #define PAD _XSTR(__LINE__)
29 #endif /* PAD */
30
31 typedef volatile struct {
32 /* BSPI */
33 uint32 bspi_revision_id; /* 0x0 */
34 uint32 bspi_scratch; /* 0x4 */
35 uint32 bspi_mast_n_boot_ctrl; /* 0x8 */
36 uint32 bspi_busy_status; /* 0xc */
37 uint32 bspi_intr_status; /* 0x10 */
38 uint32 bspi_b0_status; /* 0x14 */
39 uint32 bspi_b0_ctrl; /* 0x18 */
40 uint32 bspi_b1_status; /* 0x1c */
41 uint32 bspi_b1_ctrl; /* 0x20 */
42 uint32 bspi_strap_override_ctrl; /* 0x24 */
43 uint32 bspi_flex_mode_enable; /* 0x28 */
44 uint32 bspi_bits_per_cycle; /* 0x2c */
45 uint32 bspi_bits_per_phase; /* 0x30 */
46 uint32 bspi_cmd_and_mode_byte; /* 0x34 */
47 uint32 bspi_bspi_flash_upper_addr_byte; /* 0x38 */
48 uint32 bspi_bspi_xor_value; /* 0x3c */
49 uint32 bspi_bspi_xor_enable; /* 0x40 */
50 uint32 bspi_bspi_pio_mode_enable; /* 0x44 */
51 uint32 bspi_bspi_pio_iodir; /* 0x48 */
52 uint32 bspi_bspi_pio_data; /* 0x4c */
53 uint32 PAD[44]; /* 0x50 ~ 0xfc */
54
55 /* RAF */
56 uint32 raf_start_addr; /* 0x100 */
57 uint32 raf_num_words; /* 0x104 */
58 uint32 raf_ctrl; /* 0x108 */
59 uint32 raf_fullness; /* 0x10c */
60 uint32 raf_watermark; /* 0x110 */
61 uint32 raf_status; /* 0x114 */
62 uint32 raf_read_data; /* 0x118 */
63 uint32 raf_word_cnt; /* 0x11c */
64 uint32 raf_curr_addr; /* 0x120 */
65 uint32 PAD[55]; /* 0x124 ~ 0x1fc */
66
67 /* MSPI */
68 uint32 mspi_spcr0_lsb; /* 0x200 */
69 uint32 mspi_spcr0_msb; /* 0x204 */
70 uint32 mspi_spcr1_lsb; /* 0x208 */
71 uint32 mspi_spcr1_msb; /* 0x20c */
72 uint32 mspi_newqp; /* 0x210 */
73 uint32 mspi_endqp; /* 0x214 */
74 uint32 mspi_spcr2; /* 0x218 */
75 uint32 PAD; /* 0x21c */
76 uint32 mspi_mspi_status; /* 0x220 */
77 uint32 mspi_cptqp; /* 0x224 */
78 uint32 PAD[6]; /* 0x228 ~ 0x23c */
79 uint32 mspi_txram[32]; /* 0x240 ~ 0x2b8 */
80 uint32 mspi_rxram[32]; /* 0x2c0 ~ 0x33c */
81 uint32 mspi_cdram[16]; /* 0x340 ~ 0x37c */
82 uint32 mspi_write_lock; /* 0x380 */
83 uint32 mspi_disable_flush_gen; /* 0x384 */
84 uint32 PAD[6]; /* 0x388 ~ 0x39C */
85
86 /* Interrupt */
87 uint32 intr_raf_lr_fullness_reached; /* 0x3a0 */
88 uint32 intr_raf_lr_truncated; /* 0x3a4 */
89 uint32 intr_raf_lr_impatient; /* 0x3a8 */
90 uint32 intr_raf_lr_session_done; /* 0x3ac */
91 uint32 intr_raf_lr_overread; /* 0x3b0 */
92 uint32 intr_mspi_done; /* 0x3b4 */
93 uint32 intr_mspi_halt_set_transaction_done; /* 0x3b8 */
94 } qspiregs_t;
95
96 /*
97 * SPCR0_LSB - SPCR0_LSB REGISTER
98 */
99 /* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
100 #define MSPI_SPCR0_LSB_reserved0_MASK 0xffffff00
101 #define MSPI_SPCR0_LSB_reserved0_SHIFT 8
102
103 /* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
104 #define MSPI_SPCR0_LSB_SPBR_MASK 0x000000ff
105 #define MSPI_SPCR0_LSB_SPBR_SHIFT 0
106 #define MSPI_SPCR0_LSB_SPBR_DEFAULT 0
107
108 /*
109 * SPCR0_MSB - SPCR0_MSB Register
110 */
111 /* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
112 #define MSPI_SPCR0_MSB_reserved0_MASK 0xffffff00
113 #define MSPI_SPCR0_MSB_reserved0_SHIFT 8
114
115 /* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
116 #define MSPI_SPCR0_MSB_MSTR_MASK 0x00000080
117 #define MSPI_SPCR0_MSB_MSTR_SHIFT 7
118 #define MSPI_SPCR0_MSB_MSTR_DEFAULT 1
119
120 /* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
121 #define MSPI_SPCR0_MSB_StartTransDelay_MASK 0x00000040
122 #define MSPI_SPCR0_MSB_StartTransDelay_SHIFT 6
123 #define MSPI_SPCR0_MSB_StartTransDelay_DEFAULT 0
124
125 /* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
126 #define MSPI_SPCR0_MSB_BitS_MASK 0x0000003c
127 #define MSPI_SPCR0_MSB_BitS_SHIFT 2
128 #define MSPI_SPCR0_MSB_BitS_DEFAULT 0
129
130 /* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
131 #define MSPI_SPCR0_MSB_CPOL_MASK 0x00000002
132 #define MSPI_SPCR0_MSB_CPOL_SHIFT 1
133 #define MSPI_SPCR0_MSB_CPOL_DEFAULT 0
134
135 /* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
136 #define MSPI_SPCR0_MSB_CPHA_MASK 0x00000001
137 #define MSPI_SPCR0_MSB_CPHA_SHIFT 0
138 #define MSPI_SPCR0_MSB_CPHA_DEFAULT 0
139
140 /*
141 * SPCR1_LSB - SPCR1_LSB REGISTER
142 */
143 /* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
144 #define MSPI_SPCR1_LSB_reserved0_MASK 0xffffff00
145 #define MSPI_SPCR1_LSB_reserved0_SHIFT 8
146
147 /* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
148 #define MSPI_SPCR1_LSB_DTL_MASK 0x000000ff
149 #define MSPI_SPCR1_LSB_DTL_SHIFT 0
150 #define MSPI_SPCR1_LSB_DTL_DEFAULT 0
151
152 /*
153 * SPCR1_MSB - SPCR1_MSB REGISTER
154 */
155 /* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
156 #define MSPI_SPCR1_MSB_reserved0_MASK 0xffffff00
157 #define MSPI_SPCR1_MSB_reserved0_SHIFT 8
158
159 /* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
160 #define MSPI_SPCR1_MSB_RDSCLK_MASK 0x000000ff
161 #define MSPI_SPCR1_MSB_RDSCLK_SHIFT 0
162 #define MSPI_SPCR1_MSB_RDSCLK_DEFAULT 0
163
164 /*
165 * NEWQP - NEWQP REGISTER
166 */
167 /* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
168 #define MSPI_NEWQP_reserved0_MASK 0xfffffff0
169 #define MSPI_NEWQP_reserved0_SHIFT 4
170
171 /* HIF_MSPI :: NEWQP :: newqp [03:00] */
172 #define MSPI_NEWQP_newqp_MASK 0x0000000f
173 #define MSPI_NEWQP_newqp_SHIFT 0
174 #define MSPI_NEWQP_newqp_DEFAULT 0
175
176 /*
177 * ENDQP - ENDQP REGISTER
178 */
179 /* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
180 #define MSPI_ENDQP_reserved0_MASK 0xfffffff0
181 #define MSPI_ENDQP_reserved0_SHIFT 4
182
183 /* HIF_MSPI :: ENDQP :: endqp [03:00] */
184 #define MSPI_ENDQP_endqp_MASK 0x0000000f
185 #define MSPI_ENDQP_endqp_SHIFT 0
186 #define MSPI_ENDQP_endqp_DEFAULT 0
187
188 /*
189 * SPCR2 - SPCR2 REGISTER
190 */
191 /* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
192 #define MSPI_SPCR2_reserved0_MASK 0xffffff00
193 #define MSPI_SPCR2_reserved0_SHIFT 8
194
195 /* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
196 #define MSPI_SPCR2_cont_after_cmd_MASK 0x00000080
197 #define MSPI_SPCR2_cont_after_cmd_SHIFT 7
198 #define MSPI_SPCR2_cont_after_cmd_DEFAULT 0
199
200 /* HIF_MSPI :: SPCR2 :: spe [06:06] */
201 #define MSPI_SPCR2_spe_MASK 0x00000040
202 #define MSPI_SPCR2_spe_SHIFT 6
203 #define MSPI_SPCR2_spe_DEFAULT 0
204
205 /* HIF_MSPI :: SPCR2 :: spifie [05:05] */
206 #define MSPI_SPCR2_spifie_MASK 0x00000020
207 #define MSPI_SPCR2_spifie_SHIFT 5
208 #define MSPI_SPCR2_spifie_DEFAULT 0
209
210 /* HIF_MSPI :: SPCR2 :: wren [04:04] */
211 #define MSPI_SPCR2_wren_MASK 0x00000010
212 #define MSPI_SPCR2_wren_SHIFT 4
213 #define MSPI_SPCR2_wren_DEFAULT 0
214
215 /* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
216 #define MSPI_SPCR2_wrt0_MASK 0x00000008
217 #define MSPI_SPCR2_wrt0_SHIFT 3
218 #define MSPI_SPCR2_wrt0_DEFAULT 0
219
220 /* HIF_MSPI :: SPCR2 :: loopq [02:02] */
221 #define MSPI_SPCR2_loopq_MASK 0x00000004
222 #define MSPI_SPCR2_loopq_SHIFT 2
223 #define MSPI_SPCR2_loopq_DEFAULT 0
224
225 /* HIF_MSPI :: SPCR2 :: hie [01:01] */
226 #define MSPI_SPCR2_hie_MASK 0x00000002
227 #define MSPI_SPCR2_hie_SHIFT 1
228 #define MSPI_SPCR2_hie_DEFAULT 0
229
230 /* HIF_MSPI :: SPCR2 :: halt [00:00] */
231 #define MSPI_SPCR2_halt_MASK 0x00000001
232 #define MSPI_SPCR2_halt_SHIFT 0
233 #define MSPI_SPCR2_halt_DEFAULT 0
234
235 /*
236 * MSPI_STATUS - MSPI STATUS REGISTER
237 */
238 /* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
239 #define MSPI_MSPI_STATUS_reserved0_MASK 0xfffffffc
240 #define MSPI_MSPI_STATUS_reserved0_SHIFT 2
241
242 /* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
243 #define MSPI_MSPI_STATUS_HALTA_MASK 0x00000002
244 #define MSPI_MSPI_STATUS_HALTA_SHIFT 1
245 #define MSPI_MSPI_STATUS_HALTA_DEFAULT 0
246
247 /* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
248 #define MSPI_MSPI_STATUS_SPIF_MASK 0x00000001
249 #define MSPI_MSPI_STATUS_SPIF_SHIFT 0
250 #define MSPI_MSPI_STATUS_SPIF_DEFAULT 0
251
252 /*
253 * CPTQP - CPTQP REGISTER
254 */
255 /* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
256 #define MSPI_CPTQP_reserved0_MASK 0xfffffff0
257 #define MSPI_CPTQP_reserved0_SHIFT 4
258
259 /* HIF_MSPI :: CPTQP :: cptqp [03:00] */
260 #define MSPI_CPTQP_cptqp_MASK 0x0000000f
261 #define MSPI_CPTQP_cptqp_SHIFT 0
262 #define MSPI_CPTQP_cptqp_DEFAULT 0
263
264 /*
265 * TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
266 */
267 /* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
268 #define MSPI_TXRAM00_reserved0_MASK 0xffffff00
269 #define MSPI_TXRAM00_reserved0_SHIFT 8
270
271 /* HIF_MSPI :: TXRAM00 :: txram [07:00] */
272 #define MSPI_TXRAM00_txram_MASK 0x000000ff
273 #define MSPI_TXRAM00_txram_SHIFT 0
274
275 /*
276 * TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
277 */
278 /* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
279 #define MSPI_TXRAM01_reserved0_MASK 0xffffff00
280 #define MSPI_TXRAM01_reserved0_SHIFT 8
281
282 /* HIF_MSPI :: TXRAM01 :: txram [07:00] */
283 #define MSPI_TXRAM01_txram_MASK 0x000000ff
284 #define MSPI_TXRAM01_txram_SHIFT 0
285
286 /*
287 * TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
288 */
289 /* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
290 #define MSPI_TXRAM02_reserved0_MASK 0xffffff00
291 #define MSPI_TXRAM02_reserved0_SHIFT 8
292
293 /* HIF_MSPI :: TXRAM02 :: txram [07:00] */
294 #define MSPI_TXRAM02_txram_MASK 0x000000ff
295 #define MSPI_TXRAM02_txram_SHIFT 0
296
297 /*
298 * TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
299 */
300 /* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
301 #define MSPI_TXRAM03_reserved0_MASK 0xffffff00
302 #define MSPI_TXRAM03_reserved0_SHIFT 8
303
304 /* HIF_MSPI :: TXRAM03 :: txram [07:00] */
305 #define MSPI_TXRAM03_txram_MASK 0x000000ff
306 #define MSPI_TXRAM03_txram_SHIFT 0
307
308 /*
309 * TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
310 */
311 /* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
312 #define MSPI_TXRAM04_reserved0_MASK 0xffffff00
313 #define MSPI_TXRAM04_reserved0_SHIFT 8
314
315 /* HIF_MSPI :: TXRAM04 :: txram [07:00] */
316 #define MSPI_TXRAM04_txram_MASK 0x000000ff
317 #define MSPI_TXRAM04_txram_SHIFT 0
318
319 /*
320 * TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
321 */
322 /* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
323 #define MSPI_TXRAM05_reserved0_MASK 0xffffff00
324 #define MSPI_TXRAM05_reserved0_SHIFT 8
325
326 /* HIF_MSPI :: TXRAM05 :: txram [07:00] */
327 #define MSPI_TXRAM05_txram_MASK 0x000000ff
328 #define MSPI_TXRAM05_txram_SHIFT 0
329
330 /*
331 * TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
332 */
333 /* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
334 #define MSPI_TXRAM06_reserved0_MASK 0xffffff00
335 #define MSPI_TXRAM06_reserved0_SHIFT 8
336
337 /* HIF_MSPI :: TXRAM06 :: txram [07:00] */
338 #define MSPI_TXRAM06_txram_MASK 0x000000ff
339 #define MSPI_TXRAM06_txram_SHIFT 0
340
341 /*
342 * TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
343 */
344 /* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
345 #define MSPI_TXRAM07_reserved0_MASK 0xffffff00
346 #define MSPI_TXRAM07_reserved0_SHIFT 8
347
348 /* HIF_MSPI :: TXRAM07 :: txram [07:00] */
349 #define MSPI_TXRAM07_txram_MASK 0x000000ff
350 #define MSPI_TXRAM07_txram_SHIFT 0
351
352 /*
353 * TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
354 */
355 /* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
356 #define MSPI_TXRAM08_reserved0_MASK 0xffffff00
357 #define MSPI_TXRAM08_reserved0_SHIFT 8
358
359 /* HIF_MSPI :: TXRAM08 :: txram [07:00] */
360 #define MSPI_TXRAM08_txram_MASK 0x000000ff
361 #define MSPI_TXRAM08_txram_SHIFT 0
362
363 /*
364 * TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
365 */
366 /* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
367 #define MSPI_TXRAM09_reserved0_MASK 0xffffff00
368 #define MSPI_TXRAM09_reserved0_SHIFT 8
369
370 /* HIF_MSPI :: TXRAM09 :: txram [07:00] */
371 #define MSPI_TXRAM09_txram_MASK 0x000000ff
372 #define MSPI_TXRAM09_txram_SHIFT 0
373
374 /*
375 * TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
376 */
377 /* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
378 #define MSPI_TXRAM10_reserved0_MASK 0xffffff00
379 #define MSPI_TXRAM10_reserved0_SHIFT 8
380
381 /* HIF_MSPI :: TXRAM10 :: txram [07:00] */
382 #define MSPI_TXRAM10_txram_MASK 0x000000ff
383 #define MSPI_TXRAM10_txram_SHIFT 0
384
385 /*
386 * TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
387 */
388 /* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
389 #define MSPI_TXRAM11_reserved0_MASK 0xffffff00
390 #define MSPI_TXRAM11_reserved0_SHIFT 8
391
392 /* HIF_MSPI :: TXRAM11 :: txram [07:00] */
393 #define MSPI_TXRAM11_txram_MASK 0x000000ff
394 #define MSPI_TXRAM11_txram_SHIFT 0
395
396 /*
397 * TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
398 */
399 /* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
400 #define MSPI_TXRAM12_reserved0_MASK 0xffffff00
401 #define MSPI_TXRAM12_reserved0_SHIFT 8
402
403 /* HIF_MSPI :: TXRAM12 :: txram [07:00] */
404 #define MSPI_TXRAM12_txram_MASK 0x000000ff
405 #define MSPI_TXRAM12_txram_SHIFT 0
406
407 /*
408 * TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
409 */
410 /* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
411 #define MSPI_TXRAM13_reserved0_MASK 0xffffff00
412 #define MSPI_TXRAM13_reserved0_SHIFT 8
413
414 /* HIF_MSPI :: TXRAM13 :: txram [07:00] */
415 #define MSPI_TXRAM13_txram_MASK 0x000000ff
416 #define MSPI_TXRAM13_txram_SHIFT 0
417
418 /*
419 * TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
420 */
421 /* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
422 #define MSPI_TXRAM14_reserved0_MASK 0xffffff00
423 #define MSPI_TXRAM14_reserved0_SHIFT 8
424
425 /* HIF_MSPI :: TXRAM14 :: txram [07:00] */
426 #define MSPI_TXRAM14_txram_MASK 0x000000ff
427 #define MSPI_TXRAM14_txram_SHIFT 0
428
429 /*
430 * TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
431 */
432 /* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
433 #define MSPI_TXRAM15_reserved0_MASK 0xffffff00
434 #define MSPI_TXRAM15_reserved0_SHIFT 8
435
436 /* HIF_MSPI :: TXRAM15 :: txram [07:00] */
437 #define MSPI_TXRAM15_txram_MASK 0x000000ff
438 #define MSPI_TXRAM15_txram_SHIFT 0
439
440 /*
441 * TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
442 */
443 /* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
444 #define MSPI_TXRAM16_reserved0_MASK 0xffffff00
445 #define MSPI_TXRAM16_reserved0_SHIFT 8
446
447 /* HIF_MSPI :: TXRAM16 :: txram [07:00] */
448 #define MSPI_TXRAM16_txram_MASK 0x000000ff
449 #define MSPI_TXRAM16_txram_SHIFT 0
450
451 /*
452 * TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
453 */
454 /* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
455 #define MSPI_TXRAM17_reserved0_MASK 0xffffff00
456 #define MSPI_TXRAM17_reserved0_SHIFT 8
457
458 /* HIF_MSPI :: TXRAM17 :: txram [07:00] */
459 #define MSPI_TXRAM17_txram_MASK 0x000000ff
460 #define MSPI_TXRAM17_txram_SHIFT 0
461
462 /*
463 * TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
464 */
465 /* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
466 #define MSPI_TXRAM18_reserved0_MASK 0xffffff00
467 #define MSPI_TXRAM18_reserved0_SHIFT 8
468
469 /* HIF_MSPI :: TXRAM18 :: txram [07:00] */
470 #define MSPI_TXRAM18_txram_MASK 0x000000ff
471 #define MSPI_TXRAM18_txram_SHIFT 0
472
473 /*
474 * TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
475 */
476 /* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
477 #define MSPI_TXRAM19_reserved0_MASK 0xffffff00
478 #define MSPI_TXRAM19_reserved0_SHIFT 8
479
480 /* HIF_MSPI :: TXRAM19 :: txram [07:00] */
481 #define MSPI_TXRAM19_txram_MASK 0x000000ff
482 #define MSPI_TXRAM19_txram_SHIFT 0
483
484 /*
485 * TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
486 */
487 /* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
488 #define MSPI_TXRAM20_reserved0_MASK 0xffffff00
489 #define MSPI_TXRAM20_reserved0_SHIFT 8
490
491 /* HIF_MSPI :: TXRAM20 :: txram [07:00] */
492 #define MSPI_TXRAM20_txram_MASK 0x000000ff
493 #define MSPI_TXRAM20_txram_SHIFT 0
494
495 /*
496 * TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
497 */
498 /* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
499 #define MSPI_TXRAM21_reserved0_MASK 0xffffff00
500 #define MSPI_TXRAM21_reserved0_SHIFT 8
501
502 /* HIF_MSPI :: TXRAM21 :: txram [07:00] */
503 #define MSPI_TXRAM21_txram_MASK 0x000000ff
504 #define MSPI_TXRAM21_txram_SHIFT 0
505
506 /*
507 * TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
508 */
509 /* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
510 #define MSPI_TXRAM22_reserved0_MASK 0xffffff00
511 #define MSPI_TXRAM22_reserved0_SHIFT 8
512
513 /* HIF_MSPI :: TXRAM22 :: txram [07:00] */
514 #define MSPI_TXRAM22_txram_MASK 0x000000ff
515 #define MSPI_TXRAM22_txram_SHIFT 0
516
517 /*
518 * TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
519 */
520 /* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
521 #define MSPI_TXRAM23_reserved0_MASK 0xffffff00
522 #define MSPI_TXRAM23_reserved0_SHIFT 8
523
524 /* HIF_MSPI :: TXRAM23 :: txram [07:00] */
525 #define MSPI_TXRAM23_txram_MASK 0x000000ff
526 #define MSPI_TXRAM23_txram_SHIFT 0
527
528 /*
529 * TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
530 */
531 /* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
532 #define MSPI_TXRAM24_reserved0_MASK 0xffffff00
533 #define MSPI_TXRAM24_reserved0_SHIFT 8
534
535 /* HIF_MSPI :: TXRAM24 :: txram [07:00] */
536 #define MSPI_TXRAM24_txram_MASK 0x000000ff
537 #define MSPI_TXRAM24_txram_SHIFT 0
538
539 /*
540 * TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
541 */
542 /* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
543 #define MSPI_TXRAM25_reserved0_MASK 0xffffff00
544 #define MSPI_TXRAM25_reserved0_SHIFT 8
545
546 /* HIF_MSPI :: TXRAM25 :: txram [07:00] */
547 #define MSPI_TXRAM25_txram_MASK 0x000000ff
548 #define MSPI_TXRAM25_txram_SHIFT 0
549
550 /*
551 * TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
552 */
553 /* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
554 #define MSPI_TXRAM26_reserved0_MASK 0xffffff00
555 #define MSPI_TXRAM26_reserved0_SHIFT 8
556
557 /* HIF_MSPI :: TXRAM26 :: txram [07:00] */
558 #define MSPI_TXRAM26_txram_MASK 0x000000ff
559 #define MSPI_TXRAM26_txram_SHIFT 0
560
561 /*
562 * TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
563 */
564 /* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
565 #define MSPI_TXRAM27_reserved0_MASK 0xffffff00
566 #define MSPI_TXRAM27_reserved0_SHIFT 8
567
568 /* HIF_MSPI :: TXRAM27 :: txram [07:00] */
569 #define MSPI_TXRAM27_txram_MASK 0x000000ff
570 #define MSPI_TXRAM27_txram_SHIFT 0
571
572 /*
573 * TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
574 */
575 /* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
576 #define MSPI_TXRAM28_reserved0_MASK 0xffffff00
577 #define MSPI_TXRAM28_reserved0_SHIFT 8
578
579 /* HIF_MSPI :: TXRAM28 :: txram [07:00] */
580 #define MSPI_TXRAM28_txram_MASK 0x000000ff
581 #define MSPI_TXRAM28_txram_SHIFT 0
582
583 /*
584 * TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
585 */
586 /* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
587 #define MSPI_TXRAM29_reserved0_MASK 0xffffff00
588 #define MSPI_TXRAM29_reserved0_SHIFT 8
589
590 /* HIF_MSPI :: TXRAM29 :: txram [07:00] */
591 #define MSPI_TXRAM29_txram_MASK 0x000000ff
592 #define MSPI_TXRAM29_txram_SHIFT 0
593
594 /*
595 * TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
596 */
597 /* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
598 #define MSPI_TXRAM30_reserved0_MASK 0xffffff00
599 #define MSPI_TXRAM30_reserved0_SHIFT 8
600
601 /* HIF_MSPI :: TXRAM30 :: txram [07:00] */
602 #define MSPI_TXRAM30_txram_MASK 0x000000ff
603 #define MSPI_TXRAM30_txram_SHIFT 0
604
605 /*
606 * TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
607 */
608 /* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
609 #define MSPI_TXRAM31_reserved0_MASK 0xffffff00
610 #define MSPI_TXRAM31_reserved0_SHIFT 8
611
612 /* HIF_MSPI :: TXRAM31 :: txram [07:00] */
613 #define MSPI_TXRAM31_txram_MASK 0x000000ff
614 #define MSPI_TXRAM31_txram_SHIFT 0
615
616 /*
617 * RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
618 */
619 /* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
620 #define MSPI_RXRAM00_reserved0_MASK 0xffffff00
621 #define MSPI_RXRAM00_reserved0_SHIFT 8
622
623 /* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
624 #define MSPI_RXRAM00_rxram_MASK 0x000000ff
625 #define MSPI_RXRAM00_rxram_SHIFT 0
626
627 /*
628 * RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
629 */
630 /* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
631 #define MSPI_RXRAM01_reserved0_MASK 0xffffff00
632 #define MSPI_RXRAM01_reserved0_SHIFT 8
633
634 /* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
635 #define MSPI_RXRAM01_rxram_MASK 0x000000ff
636 #define MSPI_RXRAM01_rxram_SHIFT 0
637
638 /*
639 * RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
640 */
641 /* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
642 #define MSPI_RXRAM02_reserved0_MASK 0xffffff00
643 #define MSPI_RXRAM02_reserved0_SHIFT 8
644
645 /* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
646 #define MSPI_RXRAM02_rxram_MASK 0x000000ff
647 #define MSPI_RXRAM02_rxram_SHIFT 0
648
649 /*
650 * RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
651 */
652 /* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
653 #define MSPI_RXRAM03_reserved0_MASK 0xffffff00
654 #define MSPI_RXRAM03_reserved0_SHIFT 8
655
656 /* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
657 #define MSPI_RXRAM03_rxram_MASK 0x000000ff
658 #define MSPI_RXRAM03_rxram_SHIFT 0
659
660 /*
661 * RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
662 */
663 /* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
664 #define MSPI_RXRAM04_reserved0_MASK 0xffffff00
665 #define MSPI_RXRAM04_reserved0_SHIFT 8
666
667 /* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
668 #define MSPI_RXRAM04_rxram_MASK 0x000000ff
669 #define MSPI_RXRAM04_rxram_SHIFT 0
670
671 /*
672 * RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
673 */
674 /* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
675 #define MSPI_RXRAM05_reserved0_MASK 0xffffff00
676 #define MSPI_RXRAM05_reserved0_SHIFT 8
677
678 /* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
679 #define MSPI_RXRAM05_rxram_MASK 0x000000ff
680 #define MSPI_RXRAM05_rxram_SHIFT 0
681
682 /*
683 * RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
684 */
685 /* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
686 #define MSPI_RXRAM06_reserved0_MASK 0xffffff00
687 #define MSPI_RXRAM06_reserved0_SHIFT 8
688
689 /* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
690 #define MSPI_RXRAM06_rxram_MASK 0x000000ff
691 #define MSPI_RXRAM06_rxram_SHIFT 0
692
693 /*
694 * RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
695 */
696 /* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
697 #define MSPI_RXRAM07_reserved0_MASK 0xffffff00
698 #define MSPI_RXRAM07_reserved0_SHIFT 8
699
700 /* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
701 #define MSPI_RXRAM07_rxram_MASK 0x000000ff
702 #define MSPI_RXRAM07_rxram_SHIFT 0
703
704 /*
705 * RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
706 */
707 /* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
708 #define MSPI_RXRAM08_reserved0_MASK 0xffffff00
709 #define MSPI_RXRAM08_reserved0_SHIFT 8
710
711 /* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
712 #define MSPI_RXRAM08_rxram_MASK 0x000000ff
713 #define MSPI_RXRAM08_rxram_SHIFT 0
714
715 /*
716 * RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
717 */
718 /* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
719 #define MSPI_RXRAM09_reserved0_MASK 0xffffff00
720 #define MSPI_RXRAM09_reserved0_SHIFT 8
721
722 /* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
723 #define MSPI_RXRAM09_rxram_MASK 0x000000ff
724 #define MSPI_RXRAM09_rxram_SHIFT 0
725
726 /*
727 * RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
728 */
729 /* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
730 #define MSPI_RXRAM10_reserved0_MASK 0xffffff00
731 #define MSPI_RXRAM10_reserved0_SHIFT 8
732
733 /* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
734 #define MSPI_RXRAM10_rxram_MASK 0x000000ff
735 #define MSPI_RXRAM10_rxram_SHIFT 0
736
737 /*
738 * RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
739 */
740 /* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
741 #define MSPI_RXRAM11_reserved0_MASK 0xffffff00
742 #define MSPI_RXRAM11_reserved0_SHIFT 8
743
744 /* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
745 #define MSPI_RXRAM11_rxram_MASK 0x000000ff
746 #define MSPI_RXRAM11_rxram_SHIFT 0
747
748 /*
749 * RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
750 */
751 /* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
752 #define MSPI_RXRAM12_reserved0_MASK 0xffffff00
753 #define MSPI_RXRAM12_reserved0_SHIFT 8
754
755 /* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
756 #define MSPI_RXRAM12_rxram_MASK 0x000000ff
757 #define MSPI_RXRAM12_rxram_SHIFT 0
758
759 /*
760 * RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
761 */
762 /* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
763 #define MSPI_RXRAM13_reserved0_MASK 0xffffff00
764 #define MSPI_RXRAM13_reserved0_SHIFT 8
765
766 /* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
767 #define MSPI_RXRAM13_rxram_MASK 0x000000ff
768 #define MSPI_RXRAM13_rxram_SHIFT 0
769
770 /*
771 * RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
772 */
773 /* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
774 #define MSPI_RXRAM14_reserved0_MASK 0xffffff00
775 #define MSPI_RXRAM14_reserved0_SHIFT 8
776
777 /* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
778 #define MSPI_RXRAM14_rxram_MASK 0x000000ff
779 #define MSPI_RXRAM14_rxram_SHIFT 0
780
781 /*
782 * RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
783 */
784 /* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
785 #define MSPI_RXRAM15_reserved0_MASK 0xffffff00
786 #define MSPI_RXRAM15_reserved0_SHIFT 8
787
788 /* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
789 #define MSPI_RXRAM15_rxram_MASK 0x000000ff
790 #define MSPI_RXRAM15_rxram_SHIFT 0
791
792 /*
793 * RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
794 */
795 /* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
796 #define MSPI_RXRAM16_reserved0_MASK 0xffffff00
797 #define MSPI_RXRAM16_reserved0_SHIFT 8
798
799 /* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
800 #define MSPI_RXRAM16_rxram_MASK 0x000000ff
801 #define MSPI_RXRAM16_rxram_SHIFT 0
802
803 /*
804 * RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
805 */
806 /* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
807 #define MSPI_RXRAM17_reserved0_MASK 0xffffff00
808 #define MSPI_RXRAM17_reserved0_SHIFT 8
809
810 /* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
811 #define MSPI_RXRAM17_rxram_MASK 0x000000ff
812 #define MSPI_RXRAM17_rxram_SHIFT 0
813
814 /*
815 * RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
816 */
817 /* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
818 #define MSPI_RXRAM18_reserved0_MASK 0xffffff00
819 #define MSPI_RXRAM18_reserved0_SHIFT 8
820
821 /* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
822 #define MSPI_RXRAM18_rxram_MASK 0x000000ff
823 #define MSPI_RXRAM18_rxram_SHIFT 0
824
825 /*
826 * RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
827 */
828 /* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
829 #define MSPI_RXRAM19_reserved0_MASK 0xffffff00
830 #define MSPI_RXRAM19_reserved0_SHIFT 8
831
832 /* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
833 #define MSPI_RXRAM19_rxram_MASK 0x000000ff
834 #define MSPI_RXRAM19_rxram_SHIFT 0
835
836 /*
837 * RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
838 */
839 /* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
840 #define MSPI_RXRAM20_reserved0_MASK 0xffffff00
841 #define MSPI_RXRAM20_reserved0_SHIFT 8
842
843 /* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
844 #define MSPI_RXRAM20_rxram_MASK 0x000000ff
845 #define MSPI_RXRAM20_rxram_SHIFT 0
846
847 /*
848 * RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
849 */
850 /* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
851 #define MSPI_RXRAM21_reserved0_MASK 0xffffff00
852 #define MSPI_RXRAM21_reserved0_SHIFT 8
853
854 /* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
855 #define MSPI_RXRAM21_rxram_MASK 0x000000ff
856 #define MSPI_RXRAM21_rxram_SHIFT 0
857
858 /*
859 * RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
860 */
861 /* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
862 #define MSPI_RXRAM22_reserved0_MASK 0xffffff00
863 #define MSPI_RXRAM22_reserved0_SHIFT 8
864
865 /* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
866 #define MSPI_RXRAM22_rxram_MASK 0x000000ff
867 #define MSPI_RXRAM22_rxram_SHIFT 0
868
869 /*
870 * RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
871 */
872 /* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
873 #define MSPI_RXRAM23_reserved0_MASK 0xffffff00
874 #define MSPI_RXRAM23_reserved0_SHIFT 8
875
876 /* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
877 #define MSPI_RXRAM23_rxram_MASK 0x000000ff
878 #define MSPI_RXRAM23_rxram_SHIFT 0
879
880 /*
881 * RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
882 */
883 /* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
884 #define MSPI_RXRAM24_reserved0_MASK 0xffffff00
885 #define MSPI_RXRAM24_reserved0_SHIFT 8
886
887 /* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
888 #define MSPI_RXRAM24_rxram_MASK 0x000000ff
889 #define MSPI_RXRAM24_rxram_SHIFT 0
890
891 /*
892 * RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
893 */
894 /* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
895 #define MSPI_RXRAM25_reserved0_MASK 0xffffff00
896 #define MSPI_RXRAM25_reserved0_SHIFT 8
897
898 /* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
899 #define MSPI_RXRAM25_rxram_MASK 0x000000ff
900 #define MSPI_RXRAM25_rxram_SHIFT 0
901
902 /*
903 * RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
904 */
905 /* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
906 #define MSPI_RXRAM26_reserved0_MASK 0xffffff00
907 #define MSPI_RXRAM26_reserved0_SHIFT 8
908
909 /* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
910 #define MSPI_RXRAM26_rxram_MASK 0x000000ff
911 #define MSPI_RXRAM26_rxram_SHIFT 0
912
913 /*
914 * RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
915 */
916 /* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
917 #define MSPI_RXRAM27_reserved0_MASK 0xffffff00
918 #define MSPI_RXRAM27_reserved0_SHIFT 8
919
920 /* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
921 #define MSPI_RXRAM27_rxram_MASK 0x000000ff
922 #define MSPI_RXRAM27_rxram_SHIFT 0
923
924 /*
925 * RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
926 */
927 /* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
928 #define MSPI_RXRAM28_reserved0_MASK 0xffffff00
929 #define MSPI_RXRAM28_reserved0_SHIFT 8
930
931 /* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
932 #define MSPI_RXRAM28_rxram_MASK 0x000000ff
933 #define MSPI_RXRAM28_rxram_SHIFT 0
934
935 /*
936 * RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
937 */
938 /* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
939 #define MSPI_RXRAM29_reserved0_MASK 0xffffff00
940 #define MSPI_RXRAM29_reserved0_SHIFT 8
941
942 /* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
943 #define MSPI_RXRAM29_rxram_MASK 0x000000ff
944 #define MSPI_RXRAM29_rxram_SHIFT 0
945
946 /*
947 * RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
948 */
949 /* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
950 #define MSPI_RXRAM30_reserved0_MASK 0xffffff00
951 #define MSPI_RXRAM30_reserved0_SHIFT 8
952
953 /* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
954 #define MSPI_RXRAM30_rxram_MASK 0x000000ff
955 #define MSPI_RXRAM30_rxram_SHIFT 0
956
957 /*
958 * RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
959 */
960 /* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
961 #define MSPI_RXRAM31_reserved0_MASK 0xffffff00
962 #define MSPI_RXRAM31_reserved0_SHIFT 8
963
964 /* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
965 #define MSPI_RXRAM31_rxram_MASK 0x000000ff
966 #define MSPI_RXRAM31_rxram_SHIFT 0
967
968 /*
969 * CDRAM00 - 8-bit command (queue pointer = 0)
970 */
971 /* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
972 #define MSPI_CDRAM00_reserved0_MASK 0xffffff00
973 #define MSPI_CDRAM00_reserved0_SHIFT 8
974
975 /* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
976 #define MSPI_CDRAM00_cdram_MASK 0x000000ff
977 #define MSPI_CDRAM00_cdram_SHIFT 0
978
979 /*
980 * CDRAM01 - 8-bit command (queue pointer = 1)
981 */
982 /* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
983 #define MSPI_CDRAM01_reserved0_MASK 0xffffff00
984 #define MSPI_CDRAM01_reserved0_SHIFT 8
985
986 /* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
987 #define MSPI_CDRAM01_cdram_MASK 0x000000ff
988 #define MSPI_CDRAM01_cdram_SHIFT 0
989
990 /*
991 * CDRAM02 - 8-bit command (queue pointer = 2)
992 */
993 /* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
994 #define MSPI_CDRAM02_reserved0_MASK 0xffffff00
995 #define MSPI_CDRAM02_reserved0_SHIFT 8
996
997 /* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
998 #define MSPI_CDRAM02_cdram_MASK 0x000000ff
999 #define MSPI_CDRAM02_cdram_SHIFT 0
1000
1001 /*
1002 * CDRAM03 - 8-bit command (queue pointer = 3)
1003 */
1004 /* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
1005 #define MSPI_CDRAM03_reserved0_MASK 0xffffff00
1006 #define MSPI_CDRAM03_reserved0_SHIFT 8
1007
1008 /* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
1009 #define MSPI_CDRAM03_cdram_MASK 0x000000ff
1010 #define MSPI_CDRAM03_cdram_SHIFT 0
1011
1012 /*
1013 * CDRAM04 - 8-bit command (queue pointer = 4)
1014 */
1015 /* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
1016 #define MSPI_CDRAM04_reserved0_MASK 0xffffff00
1017 #define MSPI_CDRAM04_reserved0_SHIFT 8
1018
1019 /* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
1020 #define MSPI_CDRAM04_cdram_MASK 0x000000ff
1021 #define MSPI_CDRAM04_cdram_SHIFT 0
1022
1023 /*
1024 * CDRAM05 - 8-bit command (queue pointer = 5)
1025 */
1026 /* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
1027 #define MSPI_CDRAM05_reserved0_MASK 0xffffff00
1028 #define MSPI_CDRAM05_reserved0_SHIFT 8
1029
1030 /* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
1031 #define MSPI_CDRAM05_cdram_MASK 0x000000ff
1032 #define MSPI_CDRAM05_cdram_SHIFT 0
1033
1034 /*
1035 * CDRAM06 - 8-bit command (queue pointer = 6)
1036 */
1037 /* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
1038 #define MSPI_CDRAM06_reserved0_MASK 0xffffff00
1039 #define MSPI_CDRAM06_reserved0_SHIFT 8
1040
1041 /* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
1042 #define MSPI_CDRAM06_cdram_MASK 0x000000ff
1043 #define MSPI_CDRAM06_cdram_SHIFT 0
1044
1045 /*
1046 * CDRAM07 - 8-bit command (queue pointer = 7)
1047 */
1048 /* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
1049 #define MSPI_CDRAM07_reserved0_MASK 0xffffff00
1050 #define MSPI_CDRAM07_reserved0_SHIFT 8
1051
1052 /* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
1053 #define MSPI_CDRAM07_cdram_MASK 0x000000ff
1054 #define MSPI_CDRAM07_cdram_SHIFT 0
1055
1056 /*
1057 * CDRAM08 - 8-bit command (queue pointer = 8)
1058 */
1059 /* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
1060 #define MSPI_CDRAM08_reserved0_MASK 0xffffff00
1061 #define MSPI_CDRAM08_reserved0_SHIFT 8
1062
1063 /* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
1064 #define MSPI_CDRAM08_cdram_MASK 0x000000ff
1065 #define MSPI_CDRAM08_cdram_SHIFT 0
1066
1067 /*
1068 * CDRAM09 - 8-bit command (queue pointer = 9)
1069 */
1070 /* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
1071 #define MSPI_CDRAM09_reserved0_MASK 0xffffff00
1072 #define MSPI_CDRAM09_reserved0_SHIFT 8
1073
1074 /* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
1075 #define MSPI_CDRAM09_cdram_MASK 0x000000ff
1076 #define MSPI_CDRAM09_cdram_SHIFT 0
1077
1078 /*
1079 * CDRAM10 - 8-bit command (queue pointer = a)
1080 */
1081 /* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
1082 #define MSPI_CDRAM10_reserved0_MASK 0xffffff00
1083 #define MSPI_CDRAM10_reserved0_SHIFT 8
1084
1085 /* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
1086 #define MSPI_CDRAM10_cdram_MASK 0x000000ff
1087 #define MSPI_CDRAM10_cdram_SHIFT 0
1088
1089 /*
1090 * CDRAM11 - 8-bit command (queue pointer = b)
1091 */
1092 /* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
1093 #define MSPI_CDRAM11_reserved0_MASK 0xffffff00
1094 #define MSPI_CDRAM11_reserved0_SHIFT 8
1095
1096 /* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
1097 #define MSPI_CDRAM11_cdram_MASK 0x000000ff
1098 #define MSPI_CDRAM11_cdram_SHIFT 0
1099
1100 /*
1101 * CDRAM12 - 8-bit command (queue pointer = c)
1102 */
1103 /* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
1104 #define MSPI_CDRAM12_reserved0_MASK 0xffffff00
1105 #define MSPI_CDRAM12_reserved0_SHIFT 8
1106
1107 /* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
1108 #define MSPI_CDRAM12_cdram_MASK 0x000000ff
1109 #define MSPI_CDRAM12_cdram_SHIFT 0
1110
1111 /*
1112 * CDRAM13 - 8-bit command (queue pointer = d)
1113 */
1114 /* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
1115 #define MSPI_CDRAM13_reserved0_MASK 0xffffff00
1116 #define MSPI_CDRAM13_reserved0_SHIFT 8
1117
1118 /* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
1119 #define MSPI_CDRAM13_cdram_MASK 0x000000ff
1120 #define MSPI_CDRAM13_cdram_SHIFT 0
1121
1122 /*
1123 * CDRAM14 - 8-bit command (queue pointer = e)
1124 */
1125 /* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
1126 #define MSPI_CDRAM14_reserved0_MASK 0xffffff00
1127 #define MSPI_CDRAM14_reserved0_SHIFT 8
1128
1129 /* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
1130 #define MSPI_CDRAM14_cdram_MASK 0x000000ff
1131 #define MSPI_CDRAM14_cdram_SHIFT 0
1132
1133 /*
1134 * CDRAM15 - 8-bit command (queue pointer = f)
1135 */
1136 /* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
1137 #define MSPI_CDRAM15_reserved0_MASK 0xffffff00
1138 #define MSPI_CDRAM15_reserved0_SHIFT 8
1139
1140 /* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
1141 #define MSPI_CDRAM15_cdram_MASK 0x000000ff
1142 #define MSPI_CDRAM15_cdram_SHIFT 0
1143
1144 /*
1145 * WRITE_LOCK - Control bit to lock group of write commands
1146 */
1147 /* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
1148 #define MSPI_WRITE_LOCK_reserved0_MASK 0xfffffffe
1149 #define MSPI_WRITE_LOCK_reserved0_SHIFT 1
1150
1151 /* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
1152 #define MSPI_WRITE_LOCK_WriteLock_MASK 0x00000001
1153 #define MSPI_WRITE_LOCK_WriteLock_SHIFT 0
1154 #define MSPI_WRITE_LOCK_WriteLock_DEFAULT 0
1155
1156 /*
1157 * DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
1158 */
1159 /* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
1160 #define MSPI_DISABLE_FLUSH_GEN_reserved0_MASK 0xfffffffe
1161 #define MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT 1
1162
1163 /* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
1164 #define MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK 0x00000001
1165 #define MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT 0
1166 #define MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT 0
1167
1168 /* BSPI register fields */
1169 #define BSPI_BITS_PER_PHASE_ADDR_MARK 0x00010000
1170
1171 #define SPI_PP_CMD (0x02)
1172 #define SPI_READ_CMD (0x03)
1173 #define SPI_WRDI_CMD (0x04)
1174 #define SPI_RDSR_CMD (0x05)
1175 #define SPI_WREN_CMD (0x06)
1176 #define SPI_SSE_CMD (0x20)
1177 #define SPI_READ_ID_CMD (0x90)
1178 #define SPI_RDID_CMD (0x9F)
1179 #define SPI_SE_CMD (0xD8)
1180 #define SPI_EN4B_CMD (0xB7)
1181 #define SPI_EX4B_CMD (0xE9)
1182
1183 #define SPI_AT_BUF1_LOAD 0x53
1184 #define SPI_AT_PAGE_ERASE 0x81
1185 #define SPI_AT_BUF1_WRITE 0x84
1186 #define SPI_AT_BUF1_PROGRAM 0x88
1187 #define SPI_AT_STATUS 0xD7
1188 #define SPI_AT_READY 0x80
1189
1190
1191 #define SPI_POLLING_INTERVAL 10 /* in usecs */
1192 #define SPI_CDRAM_CONT 0x80
1193
1194 #define SPI_CDRAM_PCS_PCS0 0x01
1195 #define SPI_CDRAM_PCS_PCS1 0x02
1196 #define SPI_CDRAM_PCS_PCS2 0x04
1197 #define SPI_CDRAM_PCS_PCS3 0x08
1198 #define SPI_CDRAM_PCS_DSCK 0x10
1199 #define SPI_CDRAM_PCS_DISABLE_ALL (SPI_CDRAM_PCS_PCS0 | SPI_CDRAM_PCS_PCS1 | \
1200 SPI_CDRAM_PCS_PCS2 | SPI_CDRAM_PCS_PCS3)
1201 #define SPI_CDRAM_BITSE 0x40
1202
1203 #define SPI_SYSTEM_CLK 216000000 /* 216 MHz */
1204 #define MAX_SPI_BAUD 13500000 /* SPBR = 8 (minimum value), 216MHZ */
1205
1206 #define BSPI_Pcs_eUpgSpiPcs2 0
1207 #define FLASH_SPI_BYTE_ORDER_FIX 1
1208
1209 #endif /* _qspi_core_h_ */
Tomato firmware and modifications.