release/src-rt-6.x.4708/include/nand_core.h

   1 /*
   2  * nand - Broadcom NAND specific definitions
   3  *
   4  * Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id:$
  19  */
  20
  21 #ifndef _nand_core_h_
  22 #define _nand_core_h_
  23
  24 /* cpp contortions to concatenate w/arg prescan */
  25 #ifndef PAD
  26 #define _PADLINE(line)  pad ## line
  27 #define _XSTR(line)     _PADLINE(line)
  28 #define PAD             _XSTR(__LINE__)
  29 #endif  /* PAD */
  30
  31 typedef volatile struct nandregs {
  32         uint32 revision;                /* 0x000 */
  33         uint32 cmd_start;               /* 0x004 */
  34         uint32 cmd_ext_address;         /* 0x008 */
  35         uint32 cmd_address;             /* 0x00c */
  36         uint32 cmd_end_address;         /* 0x010 */
  37         uint32 intfc_status;            /* 0x014 */
  38         uint32 cs_nand_select;          /* 0x018 */
  39         uint32 cs_nand_xor;             /* 0x01c */
  40         uint32 ll_op;                   /* 0x020 */
  41         uint32 mplane_base_ext_address; /* 0x024 */
  42         uint32 mplane_base_address;     /* 0x028 */
  43         uint32 PAD[9];                  /* 0x02C ~ 0x04C */
  44
  45         uint32 acc_control_cs0;         /* 0x050 */
  46         uint32 config_cs0;              /* 0x054 */
  47         uint32 timing_1_cs0;            /* 0x058 */
  48         uint32 timing_2_cs0;            /* 0x05c */
  49         uint32 acc_control_cs1;         /* 0x060 */
  50         uint32 config_cs1;              /* 0x064 */
  51         uint32 timing_1_cs1;            /* 0x068 */
  52         uint32 timing_2_cs1;            /* 0x06c */
  53         uint32 PAD[20];                 /* 0x070 ~ 0x0bc */
  54
  55         uint32 corr_stat_threshold;     /* 0x0c0 */
  56         uint32 PAD[1];                  /* 0x0c4 */
  57
  58         uint32 blk_wr_protect;          /* 0x0c8 */
  59         uint32 multiplane_opcodes_1;    /* 0x0cc */
  60         uint32 multiplane_opcodes_2;    /* 0x0d0 */
  61         uint32 multiplane_ctrl;         /* 0x0d4 */
  62         uint32 PAD[9];                  /* 0x0d8 ~ 0x0f8 */
  63
  64         uint32 uncorr_error_count;      /* 0x0fc */
  65         uint32 corr_error_count;        /* 0x100 */
  66         uint32 read_error_count;        /* 0x104 */
  67         uint32 block_lock_status;       /* 0x108 */
  68         uint32 ecc_corr_ext_addr;       /* 0x10c */
  69         uint32 ecc_corr_addr;           /* 0x110 */
  70         uint32 ecc_unc_ext_addr;        /* 0x114 */
  71         uint32 ecc_unc_addr;            /* 0x118 */
  72         uint32 flash_read_ext_addr;     /* 0x11c */
  73         uint32 flash_read_addr;         /* 0x120 */
  74         uint32 program_page_ext_addr;   /* 0x124 */
  75         uint32 program_page_addr;       /* 0x128 */
  76         uint32 copy_back_ext_addr;      /* 0x12c */
  77         uint32 copy_back_addr;          /* 0x130 */
  78         uint32 block_erase_ext_addr;    /* 0x134 */
  79         uint32 block_erase_addr;        /* 0x138 */
  80         uint32 inv_read_ext_addr;       /* 0x13c */
  81         uint32 inv_read_addr;           /* 0x140 */
  82         uint32 init_status;             /* 0x144 */
  83         uint32 onfi_status;             /* 0x148 */
  84         uint32 onfi_debug_data;         /* 0x14c */
  85         uint32 semaphore;               /* 0x150 */
  86         uint32 PAD[16];                 /* 0x154 ~ 0x190 */
  87
  88         uint32 flash_device_id;         /* 0x194 */
  89         uint32 flash_device_id_ext;     /* 0x198 */
  90         uint32 ll_rddata;               /* 0x19c */
  91         uint32 PAD[24];                 /* 0x1a0 ~ 0x1fc */
  92
  93         uint32 spare_area_read_ofs[16]; /* 0x200 ~ 0x23c */
  94         uint32 PAD[16];                 /* 0x240 ~ 0x27c */
  95
  96         uint32 spare_area_write_ofs[16];        /* 0x280 ~ 0x2bc */
  97         uint32 PAD[80];                 /* 0x2c0 ~ 0x3fc */
  98
  99         uint32 flash_cache[128];        /* 0x400~0x5fc */
 100         uint32 PAD[576];                /* 0x600 ~ 0xefc */
 101
 102         uint32 direct_read_rd_miss;     /* 0xf00 */
 103         uint32 block_erase_complete;    /* 0xf04 */
 104         uint32 copy_back_complete;      /* 0xf08 */
 105         uint32 program_page_complete;   /* 0xf0c */
 106         uint32 no_ctlr_ready;           /* 0xf10 */
 107         uint32 nand_rb_b;               /* 0xf14 */
 108         uint32 ecc_mips_uncorr;         /* 0xf18 */
 109         uint32 ecc_mips_corr;           /* 0xf1c */
 110 } nandregs_t;
 111
 112
 113 /* nand_cs_nand_select */
 114 #define NANDCSEL_NAND_WP                        0x20000000
 115 #define NANDCSEL_AUTO_ID_CFG                    0x40000000
 116
 117 /* nand_cmd_start commands */
 118 #define NANDCMD_NULL                            0x00000000
 119 #define NANDCMD_PAGE_RD                         0x01000000
 120 #define NANDCMD_SPARE_RD                        0x02000000
 121 #define NANDCMD_STATUS_RD                       0x03000000
 122 #define NANDCMD_PAGE_PROG                       0x04000000
 123 #define NANDCMD_SPARE_PROG                      0x05000000
 124 #define NANDCMD_COPY_BACK                       0x06000000
 125 #define NANDCMD_ID_RD                           0x07000000
 126 #define NANDCMD_BLOCK_ERASE                     0x08000000
 127 #define NANDCMD_FLASH_RESET                     0x09000000
 128 #define NANDCMD_LOCK                            0x0a000000
 129 #define NANDCMD_LOCK_DOWN                       0x0b000000
 130 #define NANDCMD_UNLOCK                          0x0c000000
 131 #define NANDCMD_LOCK_STATUS                     0x0d000000
 132 #define NANDCMD_PARAMETER_READ                  0x0e000000
 133 #define NANDCMD_PARAMETER_CHANGE_COL            0x0f000000
 134 #define NANDCMD_LOW_LEVEL_OP                    0x10000000
 135 #define NANDCMD_PAGE_READ_MULTI                 0x11000000
 136 #define NANDCMD_STATUS_READ_MULTI               0x12000000
 137 #define NANDCMD_OPCODE_MASK                     0x1f000000
 138
 139 /* nand_acc_control_cs0 */
 140 #define NANDAC_CS0_RD_ECC_EN                    0x80000000
 141 #define NANDAC_CS0_WR_ECC_EN                    0x40000000
 142 #define NANDAC_CS0_RD_ECC_BLK0_EN               0x20000000
 143 #define NANDAC_CS0_FAST_PGM_RDIN                0x10000000
 144 #define NANDAC_CS0_RD_ERASED_ECC_EN             0x08000000
 145 #define NANDAC_CS0_PARTIAL_PAGE_EN              0x04000000
 146 #define NANDAC_CS0_WR_PREEMPT_EN                0x02000000
 147 #define NANDAC_CS0_PAGE_HIT_EN                  0x01000000
 148 #define NANDAC_CS0_PREFETCH_EN                  0x00800000
 149 #define NANDAC_CS0_CACHE_MODE_EN                0x00400000
 150 #define NANDAC_CS0_CACHE_MODE_LAST_PAGE         0x00200000
 151 #define NANDAC_CS0_ECC_LEVEL_MASK               0x001f0000
 152 #define NANDAC_CS0_ECC_LEVEL_SHIFT              16
 153 #define NANDAC_CS0_SECTOR_SIZE_1K               0x00000080
 154 #define NANDAC_CS0_SPARE_AREA_SIZE              0x0000007f
 155
 156 /* nand_config_cs0 */
 157 #define NANDCF_CS0_CONFIG_LOCK                  0x80000000
 158 #define NANDCF_CS0_BLOCK_SIZE_MASK              0x70000000
 159 #define NANDCF_CS0_BLOCK_SIZE_SHIFT             28
 160 #define NANDCF_CS0_DEVICE_SIZE_MASK             0x0f000000
 161 #define NANDCF_CS0_DEVICE_SIZE_SHIFT            24
 162 #define NANDCF_CS0_DEVICE_WIDTH                 0x00800000
 163 #define NANDCF_CS0_PAGE_SIZE_MASK               0x00300000
 164 #define NANDCF_CS0_PAGE_SIZE_SHIFT              20
 165 #define NANDCF_CS0_FULL_ADDR_BYTES_MASK         0x00070000
 166 #define NANDCF_CS0_FULL_ADDR_BYTES_SHIFT        16
 167 #define NANDCF_CS0_COL_ADDR_BYTES_MASK          0x00007000
 168 #define NANDCF_CS0_COL_ADDR_BYTES_SHIFT         12
 169 #define NANDCF_CS0_BLK_ADDR_BYTES_MASK          0x00000700
 170 #define NANDCF_CS0_BLK_ADDR_BYTES_SHIFT         8
 171
 172 /* nand_intfc_status */
 173 #define NANDIST_CTRL_READY                      0x80000000
 174 #define NANDIST_FLASH_READY                     0x40000000
 175 #define NANDIST_CACHE_VALID                     0x20000000
 176 #define NANDIST_SPARE_VALID                     0x10000000
 177 #define NANDIST_ERASED                          0x08000000
 178 #define NANDIST_STATUS                          0x000000ff
 179 #define NANDIST_STATUS_FAIL                     0x00000001
 180
 181 /* cmd_ext_address */
 182 #define NANDCMD_CS_SEL_MASK                     0x00070000
 183 #define NANDCMD_CS_SEL_SHIFT                    16
 184 #define NANDCMD_EXT_ADDR_MASK                   0x0000ffff
 185
 186 /*
 187  * NAND IDM
 188  */
 189 /* Core specific control flags */
 190 #define NAND_APB_LITTLE_ENDIAN                  0x01000000
 191 #define NAND_RO_CTRL_READY                      0x00000001
 192
 193 #endif  /* _nand_core_h_ */