release/src-rt-6.x.4708/include/arminc.h

   1 /*
   2  * HND Run Time Environment for standalone ARM programs.
   3  *
   4  * Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id: arminc.h 341899 2012-06-29 04:06:38Z $
  19  */
  20
  21 #ifndef _ARMINC_H
  22 #define _ARMINC_H
  23
  24
  25 /* ARM defines */
  26
  27 #ifdef  _LANGUAGE_ASSEMBLY
  28
  29 /*
  30  * LEAF - declare leaf routine
  31  */
  32 #define LEAF(function)                          \
  33                 .section .text.function, "ax";  \
  34                 .global function;               \
  35                 .func   function;               \
  36 function:
  37
  38 #define THUMBLEAF(function)                     \
  39                 .section .text.function, "ax";  \
  40                 .global function;               \
  41                 .func   function;               \
  42                 .thumb;                         \
  43                 .thumb_func;                    \
  44 function:
  45
  46 /*
  47  * END - mark end of function
  48  */
  49 #define END(function)                           \
  50                 .ltorg;                         \
  51                 .endfunc;                       \
  52                 .size   function, . - function
  53
  54 #define DW(var, val)                    \
  55         .global var;                    \
  56         .type   var, %object;           \
  57         .size   var, 4;                 \
  58         .align  2;                      \
  59 var:    .word   val
  60
  61
  62 #define _ULCAST_
  63
  64 #else
  65
  66 /*
  67  * The following macros are especially useful for __asm__
  68  * inline assembler.
  69  */
  70 #ifndef __STR
  71 #define __STR(x) #x
  72 #endif
  73 #ifndef STR
  74 #define STR(x) __STR(x)
  75 #endif
  76
  77 #define _ULCAST_ (unsigned long)
  78
  79 #endif  /* _LANGUAGE_ASSEMBLY */
  80
  81
  82 #if defined(__ARM_ARCH_7M__)        /* Cortex-M3 */
  83
  84 /* Data Watchpoint and Trigger */
  85 #define CM3_DWT_CTRL            0xe0001000
  86 #define CM3_DWT_CYCCNT          0xe0001004
  87 #define CM3_DWT_CPICNT          0xe0001008
  88 #define CM3_DWT_EXCCNT          0xe000100c
  89 #define CM3_DWT_SLEEPCNT        0xe0001010
  90 #define CM3_DWT_LSUCNT          0xe0001014
  91 #define CM3_DWT_FOLDCNT         0xe0001018
  92 #define CM3_DWT_COMP0           0xe0001020
  93 #define CM3_DWT_MASK0           0xe0001024
  94 #define CM3_DWT_FUNCTION0       0xe0001028
  95 #define CM3_DWT_COMP1           0xe0001030
  96 #define CM3_DWT_MASK1           0xe0001034
  97 #define CM3_DWT_FUNCTION1       0xe0001038
  98 #define CM3_DWT_COMP2           0xe0001040
  99 #define CM3_DWT_MASK2           0xe0001044
 100 #define CM3_DWT_FUNCTION2       0xe0001048
 101 #define CM3_DWT_COMP3           0xe0001050
 102 #define CM3_DWT_MASK3           0xe0001054
 103 #define CM3_DWT_FUNCTION3       0xe0001058
 104
 105 #define CM3_DWT_FUNCTION_DISAB          0
 106 #define CM3_DWT_FUNCTION_WP_PCMATCH     4
 107 #define CM3_DWT_FUNCTION_WP_READ        5
 108 #define CM3_DWT_FUNCTION_WP_WRITE       6
 109 #define CM3_DWT_FUNCTION_WP_RDWR        7
 110
 111 #define CM3_NVIC_IC_TYPE        0xe000e004      /* Interrupt Control Type Reg */
 112 #define CM3_NVIC_TICK_CSR       0xe000e010      /* SysTick Control and Status Reg */
 113 #define CM3_NVIC_TICK_CSR_COUNTFLAG             0x10000
 114 #define CM3_NVIC_TICK_CSR_CLKSOURCE             0x4     /* Set for core clock, 0 for ext ref */
 115 #define CM3_NVIC_TICK_CSR_TICKINT               0x2     /* Set for intr on count going 1 => 0 */
 116 #define CM3_NVIC_TICK_CSR_ENABLE                0x1
 117 #define CM3_NVIC_TICK_RLDVAL    0xe000e014      /* SysTick Reload Value Reg */
 118 #define CM3_NVIC_TICK_CURVAL    0xe000e018      /* SysTick Current Value Reg */
 119 #define CM3_NVIC_TICK_CALVAL    0xe000e01c      /* SysTick Calibration Value Reg */
 120
 121 /* Interrupt enable/disable register */
 122 #define CM3_NVIC_IRQ_SET_EN0    0xe000e100      /* Irq 0 to 31 Set Enable Reg */
 123 #define CM3_NVIC_IRQ_SET_EN(n)  (0xe000e100 + (n) * 4)  /* Irq 0-31, 32-63, ..., 224-239 */
 124
 125 #define CM3_NVIC_IRQ_CLR_EN0    0xe000e180      /* Irq 0 to 31 Clear Enable Reg [...] */
 126 #define CM3_NVIC_IRQ_CLR_EN(n)  (0xe000e180 + (n) * 4)  /* Irq 0-31, 32-63, ..., 224-239 */
 127
 128 #define CM3_NVIC_IRQ_SET_PND0   0xe000e200      /* Irq 0 to 31 Set Pending Reg [...] */
 129 #define CM3_NVIC_IRQ_SET_PND(n) (0xe000e200 + (n) * 4)  /* Irq 0-31, 32-63, ..., 224-239 */
 130
 131 #define CM3_NVIC_IRQ_CLR_PND0   0xe000e280      /* Irq 0 to 31 Clear Pending Reg [...] */
 132 #define CM3_NVIC_IRQ_CLR_PND(n) (0xe000e280 + (n) * 4)  /* Irq 0-31, 32-63, ..., 224-239 */
 133
 134 #define CM3_NVIC_IRQ_ACT_BIT0   0xe000e300      /* Irq 0 to 31 Active Bit Reg [...] */
 135 #define CM3_NVIC_IRQ_ACT_BIT(n) (0xe000e300 + (n) * 4)  /* Irq 0-31, 32-63, ..., 224-239 */
 136
 137 #define CM3_NVIC_IRQ_PRIO0      0xe000e400      /* Irq 0 to 31 Priority Reg [...] */
 138 #define CM3_NVIC_IRQ_PRIO(n)    (0xe000e400 + (n) * 4)  /* Irq 0-31, 32-63, ..., 224-239 */
 139
 140 /* CPU control */
 141 #define CM3_CPUID               0xe000ed00
 142 #define CM3_INTCTLSTATE         0xe000ed04
 143 #define CM3_VTOFF               0xe000ed08      /* Vector Table Offset */
 144 #define CM3_SYSCTRL             0xe000ed10
 145 #define CM3_CFGCTRL             0xe000ed14
 146 #define CM3_CFGCTRL_UNALIGN_TRP         0x8
 147 #define CM3_CFGCTRL_DIV_0_TRP           0x10
 148 #define CM3_CFGCTRL_STKALIGN            0x200
 149
 150 #define CM3_PFR0                0xe000ed40
 151 #define CM3_PFR1                0xe000ed44
 152 #define CM3_DFR0                0xe000ed48
 153 #define CM3_AFR0                0xe000ed4c
 154 #define CM3_MMFR0               0xe000ed50
 155 #define CM3_MMFR1               0xe000ed54
 156 #define CM3_MMFR2               0xe000ed58
 157 #define CM3_MMFR3               0xe000ed5c
 158 #define CM3_ISAR0               0xe000ed60
 159 #define CM3_ISAR1               0xe000ed64
 160 #define CM3_ISAR2               0xe000ed68
 161 #define CM3_ISAR3               0xe000ed6c
 162 #define CM3_ISAR4               0xe000ed70
 163 #define CM3_ISAR5               0xe000ed74
 164
 165 #define CM3_MPUTYPE             0xe000ed90
 166 #define CM3_MPUCTRL             0xe000ed94
 167 #define CM3_REGNUM              0xe000ed98
 168 #define CM3_REGBAR              0xe000ed9c
 169 #define CM3_REGASZ              0xe000eda0
 170 #define CM3_AL1BAR              0xe000eda4
 171 #define CM3_AL1ASZ              0xe000eda8
 172 #define CM3_AL2BAR              0xe000edac
 173 #define CM3_AL2ASZ              0xe000edb0
 174 #define CM3_AL3BAR              0xe000edb4
 175 #define CM3_AL3ASZ              0xe000edb8
 176
 177 #define CM3_DBG_HCSR            0xe000edf0      /* Debug Halting Control and Status Reg */
 178 #define CM3_DBG_CRSR            0xe000edf4      /* Debug Core Register Selector Reg */
 179 #define CM3_DBG_CRDR            0xe000edf8      /* Debug Core Register Data Reg */
 180 #define CM3_DBG_EMCR            0xe000edfc      /* Debug Exception and Monitor Control Reg */
 181 #define CM3_DBG_EMCR_TRCENA             (1U << 24)
 182 #define CM3_DBG_EMCR_MON_EN             (1U << 16)
 183
 184 /* Trap types */
 185 #define TR_RST          1                       /* Reset */
 186 #define TR_NMI          2                       /* NMI */
 187 #define TR_FAULT        3                       /* Hard Fault */
 188 #define TR_MM           4                       /* Memory Management */
 189 #define TR_BUS          5                       /* Bus Fault */
 190 #define TR_USAGE        6                       /* Usage Fault */
 191 #define TR_SVC          11                      /* SVCall */
 192 #define TR_DMON         12                      /* Debug Monitor */
 193 #define TR_PENDSV       14                      /* PendSV */
 194 #define TR_SYSTICK      15                      /* SysTick */
 195 #define TR_ISR          16                      /* External Interrupts start here */
 196
 197 #define TR_BAD          256                     /* Bad trap: Not used by CM3 */
 198
 199 /* Offsets of automatically saved registers from sp upon trap */
 200 #define CM3_TROFF_R0    0
 201 #define CM3_TROFF_R1    4
 202 #define CM3_TROFF_R2    8
 203 #define CM3_TROFF_R3    12
 204 #define CM3_TROFF_R12   16
 205 #define CM3_TROFF_LR    20
 206 #define CM3_TROFF_PC    24
 207 #define CM3_TROFF_xPSR  28
 208
 209 #elif defined(__ARM_ARCH_7A__)    /* Cortex-A9 */
 210 /* Fields in cpsr */
 211 #define PS_USR          0x00000010              /* Mode: User */
 212 #define PS_FIQ          0x00000011              /* Mode: FIQ */
 213 #define PS_IRQ          0x00000012              /* Mode: IRQ */
 214 #define PS_SVC          0x00000013              /* Mode: Supervisor */
 215 #define PS_ABT          0x00000017              /* Mode: Abort */
 216 #define PS_UND          0x0000001b              /* Mode: Undefined */
 217 #define PS_SYS          0x0000001f              /* Mode: System */
 218 #define PS_MM           0x0000001f              /* Mode bits mask */
 219 #define PS_T            0x00000020              /* Thumb mode */
 220 #define PS_F            0x00000040              /* FIQ disable */
 221 #define PS_I            0x00000080              /* IRQ disable */
 222 #define PS_A            0x00000100              /* Imprecise abort */
 223 #define PS_E            0x00000200              /* Endianess */
 224 #define PS_IT72         0x0000fc00              /* IT[7:2] */
 225 #define PS_GE           0x000f0000              /* IT[7:2] */
 226 #define PS_J            0x01000000              /* Java state */
 227 #define PS_IT10         0x06000000              /* IT[1:0] */
 228 #define PS_Q            0x08000000              /* Sticky overflow */
 229 #define PS_V            0x10000000              /* Overflow cc */
 230 #define PS_C            0x20000000              /* Carry cc */
 231 #define PS_Z            0x40000000              /* Zero cc */
 232 #define PS_N            0x80000000              /* Negative cc */
 233
 234 /* Trap types */
 235 #define TR_RST          0                       /* Reset trap */
 236 #define TR_UND          1                       /* Indefined instruction trap */
 237 #define TR_SWI          2                       /* Software intrrupt */
 238 #define TR_IAB          3                       /* Instruction fetch abort */
 239 #define TR_DAB          4                       /* Data access abort */
 240 #define TR_BAD          5                       /* Bad trap: Not used by ARM */
 241 #define TR_IRQ          6                       /* Interrupt */
 242 #define TR_FIQ          7                       /* Fast interrupt */
 243
 244 /*
 245  * Memory segments (32bit kernel mode addresses)
 246  */
 247 #define PHYSADDR_MASK   0xffffffff
 248
 249 /*
 250  * Map an address to a certain kernel segment
 251  */
 252 #undef PHYSADDR
 253 #define PHYSADDR(a)     (_ULCAST_(a) & PHYSADDR_MASK)
 254 #else   /* !__ARM_ARCH_7M__ */
 255
 256 /* Fields in cpsr */
 257 #define PS_USR          0x00000010              /* Mode: User */
 258 #define PS_FIQ          0x00000011              /* Mode: FIQ */
 259 #define PS_IRQ          0x00000012              /* Mode: IRQ */
 260 #define PS_SVC          0x00000013              /* Mode: Supervisor */
 261 #define PS_ABT          0x00000017              /* Mode: Abort */
 262 #define PS_UND          0x0000001b              /* Mode: Undefined */
 263 #define PS_SYS          0x0000001f              /* Mode: System */
 264 #define PS_MM           0x0000001f              /* Mode bits mask */
 265 #define PS_T            0x00000020              /* Thumb mode */
 266 #define PS_F            0x00000040              /* FIQ disable */
 267 #define PS_I            0x00000080              /* IRQ disable */
 268 #define PS_A            0x00000100              /* Imprecise abort */
 269 #define PS_E            0x00000200              /* Endianess */
 270 #define PS_IT72         0x0000fc00              /* IT[7:2] */
 271 #define PS_GE           0x000f0000              /* IT[7:2] */
 272 #define PS_J            0x01000000              /* Java state */
 273 #define PS_IT10         0x06000000              /* IT[1:0] */
 274 #define PS_Q            0x08000000              /* Sticky overflow */
 275 #define PS_V            0x10000000              /* Overflow cc */
 276 #define PS_C            0x20000000              /* Carry cc */
 277 #define PS_Z            0x40000000              /* Zero cc */
 278 #define PS_N            0x80000000              /* Negative cc */
 279
 280 /* Trap types */
 281 #define TR_RST          0                       /* Reset trap */
 282 #define TR_UND          1                       /* Indefined instruction trap */
 283 #define TR_SWI          2                       /* Software intrrupt */
 284 #define TR_IAB          3                       /* Instruction fetch abort */
 285 #define TR_DAB          4                       /* Data access abort */
 286 #define TR_BAD          5                       /* Bad trap: Not used by ARM */
 287 #define TR_IRQ          6                       /* Interrupt */
 288 #define TR_FIQ          7                       /* Fast interrupt */
 289
 290 #ifdef BCMDBG_ARMRST
 291 #define TR_ARMRST       0xF                     /* Debug facility to trap Arm reset */
 292 #endif
 293
 294 /* used to fill an overlay region with nop's */
 295 #define NOP_UINT32      0x46c046c0
 296
 297
 298 #define mrc(cp, a, b, n)                                                \
 299 ({                                                                      \
 300         int __res;                                                      \
 301         __asm__ __volatile__("\tmrc\tp"STR(cp)", 0, %0, c"STR(a)", c"STR(b)", "STR(n) \
 302                                 :"=r" (__res));                         \
 303         __res;                                                          \
 304 })
 305
 306
 307 #endif  /* !__ARM_ARCH_7M__ */
 308
 309 /* Pieces of a CPU Id */
 310 #define CID_IMPL        0xff000000              /* Implementor: 0x41 for ARM Ltd. */
 311 #define CID_VARIANT     0x00f00000
 312 #define CID_ARCH        0x000f0000
 313 #define CID_PART        0x0000fff0
 314 #define CID_REV         0x0000000f
 315 #define CID_MASK        (CID_IMPL | CID_ARCH | CID_PART)
 316
 317 #endif  /* _ARMINC_H */