release/src-rt-6.x.4708/et/sys/etc.h

   1 /*
   2  * Common [OS-independent] header file for
   3  * Broadcom BCM47XX 10/100Mbps Ethernet Device Driver
   4  *
   5  * Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  14  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  16  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  17  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  * $Id: etc.h 352715 2012-08-23 19:50:14Z $
  20  */
  21
  22 #ifndef _etc_h_
  23 #define _etc_h_
  24
  25 #include <etioctl.h>
  26
  27 #define MAXMULTILIST    32
  28
  29 #ifndef ch_t
  30 #define ch_t void
  31 #endif
  32
  33 #define NUMTXQ          4
  34
  35 #define TXREC_THR       8
  36
  37 #if defined(__ECOS)
  38 #define IOCBUFSZ        4096
  39 #elif defined(__linux__)
  40 #define IOCBUFSZ        16384
  41 #else
  42 #define IOCBUFSZ        4096
  43 #endif
  44
  45 struct etc_info;        /* forward declaration */
  46 struct bcmstrbuf;       /* forward declaration */
  47
  48 /* each chip type supports a set of chip-type-specific ops */
  49 struct chops {
  50         bool (*id)(uint vendor, uint device);           /* return true if match */
  51         void *(*attach)(struct etc_info *etc, void *dev, void *regs);
  52         void (*detach)(ch_t *ch);                       /* free chip private state */
  53         void (*reset)(ch_t *ch);                        /* chip reset */
  54         void (*init)(ch_t *ch, uint options);           /* chip init */
  55         bool (*tx)(ch_t *ch, void *p);                  /* transmit frame */
  56         void *(*rx)(ch_t *ch);                          /* receive frame */
  57         void (*rxfill)(ch_t *ch);                       /* post dma rx buffers */
  58         int (*getintrevents)(ch_t *ch, bool in_isr);    /* return intr events */
  59         bool (*errors)(ch_t *ch);                       /* handle chip errors */
  60         void (*intrson)(ch_t *ch);                      /* enable chip interrupts */
  61         void (*intrsoff)(ch_t *ch);                     /* disable chip interrupts */
  62         void (*txreclaim)(ch_t *ch, bool all);          /* reclaim transmit resources */
  63         void (*rxreclaim)(ch_t *ch);                    /* reclaim receive resources */
  64         void (*statsupd)(ch_t *ch);                     /* update sw stat counters */
  65         void (*dumpmib)(ch_t *ch, struct bcmstrbuf *, bool clear);      /* get sw mib counters */
  66         void (*enablepme)(ch_t *ch);                    /* enable PME */
  67         void (*disablepme)(ch_t *ch);                   /* disable PME */
  68         void (*phyreset)(ch_t *ch, uint phyaddr);       /* reset phy */
  69         uint16 (*phyrd)(ch_t *ch, uint phyaddr, uint reg);      /* read phy register */
  70         void (*phywr)(ch_t *ch, uint phyaddr, uint reg, uint16 val);    /* write phy register */
  71         void (*dump)(ch_t *ch, struct bcmstrbuf *b);            /* debugging output */
  72         void (*longname)(ch_t *ch, char *buf, uint bufsize);    /* return descriptive name */
  73         void (*duplexupd)(ch_t *ch);                    /* keep mac duplex consistent */
  74 };
  75
  76 /*
  77  * "Common" os-independent software state structure.
  78  */
  79 typedef struct etc_info {
  80         void            *et;            /* pointer to os-specific private state */
  81         uint            unit;           /* device instance number */
  82         void            *osh;           /* pointer to os handler */
  83         bool            pktc;           /* packet chaining enabled or not */
  84         int             pktcbnd;        /* max # of packets to chain */
  85         void            *mib;           /* pointer to s/w maintained mib counters */
  86         bool            up;             /* interface up and running */
  87         bool            promisc;        /* promiscuous destination address */
  88         bool            qos;            /* QoS priority determination on rx */
  89         bool            loopbk;         /* loopback override mode */
  90
  91         int             forcespeed;     /* disable autonegotiation and force speed/duplex */
  92         uint            advertise;      /* control speed/duplex advertised caps */
  93         uint            advertise2;     /* control gige speed/duplex advertised caps */
  94         bool            needautoneg;    /* request restart autonegotiation */
  95         int             speed;          /* current speed: 10, 100 */
  96         int             duplex;         /* current duplex: 0=half, 1=full */
  97
  98         bool            piomode;        /* enable programmed io (!dma) */
  99         void            *pioactive;     /* points to pio packet being transmitted */
 100         volatile uint   *txavail[NUMTXQ];       /* dma: # tx descriptors available */
 101
 102         uint16          vendorid;       /* pci function vendor id */
 103         uint16          deviceid;       /* pci function device id */
 104         uint            chip;           /* chip number */
 105         uint            chiprev;        /* chip revision */
 106         uint            coreid;         /* core id */
 107         uint            corerev;        /* core revision */
 108
 109         bool            nicmode;        /* is this core using its own pci i/f */
 110
 111         struct chops    *chops;         /* pointer to chip-specific opsvec */
 112         void            *ch;            /* pointer to chip-specific state */
 113         void            *robo;          /* optional robo private data */
 114
 115         uint            txq_state;      /* tx queues state bits */
 116         uint            coreunit;       /* sb chips: chip enet instance # */
 117         uint            phyaddr;        /* sb chips: mdio 5-bit phy address */
 118         uint            mdcport;        /* sb chips: which mii to use (enet core #) to access phy */
 119
 120         struct ether_addr cur_etheraddr; /* our local ethernet address */
 121         struct ether_addr perm_etheraddr; /* original sprom local ethernet address */
 122
 123         struct ether_addr multicast[MAXMULTILIST];
 124         uint            nmulticast;
 125         bool            allmulti;       /* enable all multicasts */
 126
 127         bool            linkstate;      /* link integrity state */
 128         bool            pm_modechange;  /* true if mode change is to due pm */
 129
 130         uint32          now;            /* elapsed seconds */
 131
 132         uint32          boardflags;     /* board flags */
 133         uint32          txrec_thresh;   /* # of tx frames after which reclaim is done */
 134
 135         /* sw-maintained stat counters */
 136         uint32          txframes[NUMTXQ];       /* transmitted frames on each tx fifo */
 137         uint32          txframe;        /* transmitted frames */
 138         uint32          txbyte;         /* transmitted bytes */
 139         uint32          rxframe;        /* received frames */
 140         uint32          rxbyte;         /* received bytes */
 141         uint32          txerror;        /* total tx errors */
 142         uint32          txnobuf;        /* tx out-of-buffer errors */
 143         uint32          rxerror;        /* total rx errors */
 144         uint32          rxgiants;       /* total rx giant frames */
 145         uint32          rxnobuf;        /* rx out-of-buffer errors */
 146         uint32          reset;          /* reset count */
 147         uint32          dmade;          /* pci descriptor errors */
 148         uint32          dmada;          /* pci data errors */
 149         uint32          dmape;          /* descriptor protocol error */
 150         uint32          rxdmauflo;      /* receive descriptor underflow */
 151         uint32          rxoflo;         /* receive fifo overflow */
 152         uint32          txuflo;         /* transmit fifo underflow */
 153         uint32          rxoflodiscards; /* frames discarded during rx fifo overflow */
 154         uint32          rxbadlen;       /* 802.3 len field != read length */
 155         uint32          chained;        /* number of frames chained */
 156         uint32          unchained;      /* number of frames not chained */
 157         uint32          maxchainsz;     /* max chain size so far */
 158         uint32          currchainsz;    /* current chain size */
 159 #if defined(BCMDBG) && defined(PKTC)
 160         uint32          chainsz[PKTCBND];       /* chain size histo */
 161 #endif
 162 } etc_info_t;
 163
 164 /* interrupt event bitvec */
 165 #define INTR_TX         0x1
 166 #define INTR_RX         0x2
 167 #define INTR_ERROR      0x4
 168 #define INTR_TO         0x8
 169 #define INTR_NEW        0x10
 170
 171 /* forcespeed values */
 172 #define ET_AUTO         -1
 173 #define ET_10HALF       0
 174 #define ET_10FULL       1
 175 #define ET_100HALF      2
 176 #define ET_100FULL      3
 177 #define ET_1000HALF     4
 178 #define ET_1000FULL     5
 179 #define ET_2500FULL     6
 180
 181 /* init options */
 182 #define ET_INIT_FULL     0x1
 183 #define ET_INIT_INTRON   0x2
 184
 185 /* Specific init options for et_init */
 186 #define ET_INIT_DEF_OPTIONS   (ET_INIT_FULL | ET_INIT_INTRON)
 187 #define ET_INIT_INTROFF       (ET_INIT_FULL)
 188 #define ET_INIT_PARTIAL      (0)
 189
 190 /* macro to safely clear the UP flag */
 191 #define ET_FLAG_DOWN(x)   (*(x)->chops->intrsoff)((x)->ch);  \
 192                           (x)->up = FALSE;
 193
 194 /*
 195  * Least-common denominator rxbuf start-of-data offset:
 196  * Must be >= size of largest rxhdr
 197  * Must be 2-mod-4 aligned so IP is 0-mod-4
 198  */
 199 #define HWRXOFF         14
 200
 201 #define TC_BK           0       /* background traffic class */
 202 #define TC_BE           1       /* best effort traffic class */
 203 #define TC_CL           2       /* controlled load traffic class */
 204 #define TC_VO           3       /* voice traffic class */
 205 #define TC_NONE         -1      /* traffic class none */
 206
 207 #define RX_Q0           0       /* receive DMA queue */
 208 #define NUMRXQ          1       /* gmac has one rx queue */
 209
 210 #define TX_Q0           TC_BK   /* DMA txq 0 */
 211 #define TX_Q1           TC_BE   /* DMA txq 1 */
 212 #define TX_Q2           TC_CL   /* DMA txq 2 */
 213 #define TX_Q3           TC_VO   /* DMA txq 3 */
 214
 215 static inline uint32
 216 etc_up2tc(uint32 up)
 217 {
 218         extern uint32 up2tc[];
 219
 220         return (up2tc[up]);
 221 }
 222
 223 static inline uint32
 224 etc_priq(uint32 txq_state)
 225 {
 226         extern uint32 priq_selector[];
 227
 228         return (priq_selector[txq_state]);
 229 }
 230
 231 /* rx header flags bits */
 232 #define RXH_FLAGS(etc, rxh) (((etc)->coreid == GMAC_CORE_ID) ? \
 233         ((((bcmgmacrxh_t *)(rxh))->flags) & htol16(GRXF_CRC | GRXF_OVF | GRXF_OVERSIZE)) : \
 234         ((((bcmenetrxh_t *)(rxh))->flags) & htol16(RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)))
 235
 236 #define RXH_OVERSIZE(etc, rxh) (((etc)->coreid == GMAC_CORE_ID) ? \
 237         (ltoh16(((bcmgmacrxh_t *)(rxh))->flags) & GRXF_OVERSIZE) : FALSE)
 238
 239 #define RXH_CRC(etc, rxh) (((etc)->coreid == GMAC_CORE_ID) ? \
 240         (ltoh16(((bcmgmacrxh_t *)(rxh))->flags) & GRXF_CRC) : \
 241         (ltoh16(((bcmenetrxh_t *)(rxh))->flags) & RXF_CRC))
 242
 243 #define RXH_OVF(etc, rxh) (((etc)->coreid == GMAC_CORE_ID) ? \
 244         (ltoh16(((bcmgmacrxh_t *)(rxh))->flags) & GRXF_OVF) : \
 245         (ltoh16(((bcmenetrxh_t *)(rxh))->flags) & RXF_OV))
 246
 247 #define RXH_RXER(etc, rxh) (((etc)->coreid == GMAC_CORE_ID) ? \
 248         FALSE : (ltoh16(((bcmenetrxh_t *)(rxh))->flags) & RXF_RXER))
 249
 250 #define RXH_NO(etc, rxh) (((etc)->coreid == GMAC_CORE_ID) ? \
 251         FALSE : (ltoh16(((bcmenetrxh_t *)(rxh))->flags) & RXF_NO))
 252
 253 #ifdef  CFG_GMAC
 254 #define ET_GMAC(etc)    ((etc)->coreid == GMAC_CORE_ID)
 255 #else
 256 #define ET_GMAC(etc)    (0)
 257 #endif  /* CFG_GMAC */
 258
 259 /* exported prototypes */
 260 extern struct chops *etc_chipmatch(uint vendor, uint device);
 261 extern void *etc_attach(void *et, uint vendor, uint device, uint unit, void *dev, void *regsva);
 262 extern void etc_detach(etc_info_t *etc);
 263 extern void etc_reset(etc_info_t *etc);
 264 extern void etc_init(etc_info_t *etc, uint options);
 265 extern void etc_up(etc_info_t *etc);
 266 extern uint etc_down(etc_info_t *etc, int reset);
 267 extern int etc_ioctl(etc_info_t *etc, int cmd, void *arg);
 268 extern int etc_iovar(etc_info_t *etc, uint cmd, uint set, void *arg);
 269 extern void etc_promisc(etc_info_t *etc, uint on);
 270 extern void etc_qos(etc_info_t *etc, uint on);
 271 extern void etc_dump(etc_info_t *etc, struct bcmstrbuf *b);
 272 extern void etc_watchdog(etc_info_t *etc);
 273 extern uint etc_totlen(etc_info_t *etc, void *p);
 274 #ifdef ETROBO
 275 extern void *etc_bcm53115_war(etc_info_t *etc, void *p);
 276 #endif /* ETROBO */
 277
 278 #endif  /* _etc_h_ */