release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/include/sb1250_genbus.h

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  Generic Bus Constants                     File: sb1250_genbus.h
   5     *
   6     *  This module contains constants and macros useful for
   7     *  manipulating the SB1250's Generic Bus interface
   8     *
   9     *  SB1250 specification level:  User's manual 1/02/02
  10     *
  11     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  12     *
  13     *********************************************************************
  14     *
  15     *  Copyright 2000,2001,2002,2003
  16     *  Broadcom Corporation. All rights reserved.
  17     *
  18     *  This software is furnished under license and may be used and
  19     *  copied only in accordance with the following terms and
  20     *  conditions.  Subject to these conditions, you may download,
  21     *  copy, install, use, modify and distribute modified or unmodified
  22     *  copies of this software in source and/or binary form.  No title
  23     *  or ownership is transferred hereby.
  24     *
  25     *  1) Any source code used, modified or distributed must reproduce
  26     *     and retain this copyright notice and list of conditions
  27     *     as they appear in the source file.
  28     *
  29     *  2) No right is granted to use any trade name, trademark, or
  30     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  31     *     name may not be used to endorse or promote products derived
  32     *     from this software without the prior written permission of
  33     *     Broadcom Corporation.
  34     *
  35     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  36     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  37     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  39     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  40     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  41     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  42     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  43     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  44     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  45     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  46     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  47     *     THE POSSIBILITY OF SUCH DAMAGE.
  48     ********************************************************************* */
  49
  50
  51 #ifndef _SB1250_GENBUS_H
  52 #define _SB1250_GENBUS_H
  53
  54 #include "sb1250_defs.h"
  55
  56 /*
  57  * Generic Bus Region Configuration Registers (Table 11-4)
  58  */
  59
  60 #define S_IO_RDY_ACTIVE         0
  61 #define M_IO_RDY_ACTIVE         _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
  62
  63 #define S_IO_ENA_RDY            1
  64 #define M_IO_ENA_RDY            _SB_MAKEMASK1(S_IO_ENA_RDY)
  65
  66 #define S_IO_WIDTH_SEL          2
  67 #define M_IO_WIDTH_SEL          _SB_MAKEMASK(2,S_IO_WIDTH_SEL)
  68 #define K_IO_WIDTH_SEL_1        0
  69 #define K_IO_WIDTH_SEL_2        1
  70 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
  71 #define K_IO_WIDTH_SEL_1L       2
  72 #endif /* 1250 PASS2 || 112x PASS1 */
  73 #define K_IO_WIDTH_SEL_4        3
  74 #define V_IO_WIDTH_SEL(x)       _SB_MAKEVALUE(x,S_IO_WIDTH_SEL)
  75 #define G_IO_WIDTH_SEL(x)       _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL)
  76
  77 #define S_IO_PARITY_ENA         4
  78 #define M_IO_PARITY_ENA         _SB_MAKEMASK1(S_IO_PARITY_ENA)
  79 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
  80 #define S_IO_BURST_EN           5
  81 #define M_IO_BURST_EN           _SB_MAKEMASK1(S_IO_BURST_EN)
  82 #endif /* 1250 PASS2 || 112x PASS1 */
  83 #define S_IO_PARITY_ODD         6
  84 #define M_IO_PARITY_ODD         _SB_MAKEMASK1(S_IO_PARITY_ODD)
  85 #define S_IO_NONMUX             7
  86 #define M_IO_NONMUX             _SB_MAKEMASK1(S_IO_NONMUX)
  87
  88 #define S_IO_TIMEOUT            8
  89 #define M_IO_TIMEOUT            _SB_MAKEMASK(8,S_IO_TIMEOUT)
  90 #define V_IO_TIMEOUT(x)         _SB_MAKEVALUE(x,S_IO_TIMEOUT)
  91 #define G_IO_TIMEOUT(x)         _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT)
  92
  93 /*
  94  * Generic Bus Region Size register (Table 11-5)
  95  */
  96
  97 #define S_IO_MULT_SIZE          0
  98 #define M_IO_MULT_SIZE          _SB_MAKEMASK(12,S_IO_MULT_SIZE)
  99 #define V_IO_MULT_SIZE(x)       _SB_MAKEVALUE(x,S_IO_MULT_SIZE)
 100 #define G_IO_MULT_SIZE(x)       _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE)
 101
 102 #define S_IO_REGSIZE            16       /* # bits to shift size for this reg */
 103
 104 /*
 105  * Generic Bus Region Address (Table 11-6)
 106  */
 107
 108 #define S_IO_START_ADDR         0
 109 #define M_IO_START_ADDR         _SB_MAKEMASK(14,S_IO_START_ADDR)
 110 #define V_IO_START_ADDR(x)      _SB_MAKEVALUE(x,S_IO_START_ADDR)
 111 #define G_IO_START_ADDR(x)      _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR)
 112
 113 #define S_IO_ADDRBASE           16       /* # bits to shift addr for this reg */
 114
 115 /*
 116  * Generic Bus Region 0 Timing Registers (Table 11-7)
 117  */
 118
 119 #define S_IO_ALE_WIDTH          0
 120 #define M_IO_ALE_WIDTH          _SB_MAKEMASK(3,S_IO_ALE_WIDTH)
 121 #define V_IO_ALE_WIDTH(x)       _SB_MAKEVALUE(x,S_IO_ALE_WIDTH)
 122 #define G_IO_ALE_WIDTH(x)       _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH)
 123
 124 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 125 #define M_IO_EARLY_CS           _SB_MAKEMASK1(3)
 126 #endif /* 1250 PASS2 || 112x PASS1 */
 127
 128 #define S_IO_ALE_TO_CS          4
 129 #define M_IO_ALE_TO_CS          _SB_MAKEMASK(2,S_IO_ALE_TO_CS)
 130 #define V_IO_ALE_TO_CS(x)       _SB_MAKEVALUE(x,S_IO_ALE_TO_CS)
 131 #define G_IO_ALE_TO_CS(x)       _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS)
 132
 133 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 134 #define S_IO_BURST_WIDTH           _SB_MAKE64(6)
 135 #define M_IO_BURST_WIDTH           _SB_MAKEMASK(2,S_IO_BURST_WIDTH)
 136 #define V_IO_BURST_WIDTH(x)        _SB_MAKEVALUE(x,S_IO_BURST_WIDTH)
 137 #define G_IO_BURST_WIDTH(x)        _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH)
 138 #endif /* 1250 PASS2 || 112x PASS1 */
 139
 140 #define S_IO_CS_WIDTH           8
 141 #define M_IO_CS_WIDTH           _SB_MAKEMASK(5,S_IO_CS_WIDTH)
 142 #define V_IO_CS_WIDTH(x)        _SB_MAKEVALUE(x,S_IO_CS_WIDTH)
 143 #define G_IO_CS_WIDTH(x)        _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH)
 144
 145 #define S_IO_RDY_SMPLE          13
 146 #define M_IO_RDY_SMPLE          _SB_MAKEMASK(3,S_IO_RDY_SMPLE)
 147 #define V_IO_RDY_SMPLE(x)       _SB_MAKEVALUE(x,S_IO_RDY_SMPLE)
 148 #define G_IO_RDY_SMPLE(x)       _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE)
 149
 150
 151 /*
 152  * Generic Bus Timing 1 Registers (Table 11-8)
 153  */
 154
 155 #define S_IO_ALE_TO_WRITE       0
 156 #define M_IO_ALE_TO_WRITE       _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE)
 157 #define V_IO_ALE_TO_WRITE(x)    _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE)
 158 #define G_IO_ALE_TO_WRITE(x)    _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE)
 159
 160 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 161 #define M_IO_RDY_SYNC           _SB_MAKEMASK1(3)
 162 #endif /* 1250 PASS2 || 112x PASS1 */
 163
 164 #define S_IO_WRITE_WIDTH        4
 165 #define M_IO_WRITE_WIDTH        _SB_MAKEMASK(4,S_IO_WRITE_WIDTH)
 166 #define V_IO_WRITE_WIDTH(x)     _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH)
 167 #define G_IO_WRITE_WIDTH(x)     _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH)
 168
 169 #define S_IO_IDLE_CYCLE         8
 170 #define M_IO_IDLE_CYCLE         _SB_MAKEMASK(4,S_IO_IDLE_CYCLE)
 171 #define V_IO_IDLE_CYCLE(x)      _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE)
 172 #define G_IO_IDLE_CYCLE(x)      _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE)
 173
 174 #define S_IO_OE_TO_CS           12
 175 #define M_IO_OE_TO_CS           _SB_MAKEMASK(2,S_IO_OE_TO_CS)
 176 #define V_IO_OE_TO_CS(x)        _SB_MAKEVALUE(x,S_IO_OE_TO_CS)
 177 #define G_IO_OE_TO_CS(x)        _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS)
 178
 179 #define S_IO_CS_TO_OE           14
 180 #define M_IO_CS_TO_OE           _SB_MAKEMASK(2,S_IO_CS_TO_OE)
 181 #define V_IO_CS_TO_OE(x)        _SB_MAKEVALUE(x,S_IO_CS_TO_OE)
 182 #define G_IO_CS_TO_OE(x)        _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE)
 183
 184 /*
 185  * Generic Bus Interrupt Status Register (Table 11-9)
 186  */
 187
 188 #define M_IO_CS_ERR_INT         _SB_MAKEMASK(0,8)
 189 #define M_IO_CS0_ERR_INT        _SB_MAKEMASK1(0)
 190 #define M_IO_CS1_ERR_INT        _SB_MAKEMASK1(1)
 191 #define M_IO_CS2_ERR_INT        _SB_MAKEMASK1(2)
 192 #define M_IO_CS3_ERR_INT        _SB_MAKEMASK1(3)
 193 #define M_IO_CS4_ERR_INT        _SB_MAKEMASK1(4)
 194 #define M_IO_CS5_ERR_INT        _SB_MAKEMASK1(5)
 195 #define M_IO_CS6_ERR_INT        _SB_MAKEMASK1(6)
 196 #define M_IO_CS7_ERR_INT        _SB_MAKEMASK1(7)
 197
 198 #define M_IO_RD_PAR_INT         _SB_MAKEMASK1(9)
 199 #define M_IO_TIMEOUT_INT        _SB_MAKEMASK1(10)
 200 #define M_IO_ILL_ADDR_INT       _SB_MAKEMASK1(11)
 201 #define M_IO_MULT_CS_INT        _SB_MAKEMASK1(12)
 202 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 203 #define M_IO_COH_ERR            _SB_MAKEMASK1(14)
 204 #endif /* 1250 PASS2 || 112x PASS1 */
 205
 206 /*
 207  * PCMCIA configuration register (Table 12-6)
 208  */
 209
 210 #define M_PCMCIA_CFG_ATTRMEM    _SB_MAKEMASK1(0)
 211 #define M_PCMCIA_CFG_3VEN       _SB_MAKEMASK1(1)
 212 #define M_PCMCIA_CFG_5VEN       _SB_MAKEMASK1(2)
 213 #define M_PCMCIA_CFG_VPPEN      _SB_MAKEMASK1(3)
 214 #define M_PCMCIA_CFG_RESET      _SB_MAKEMASK1(4)
 215 #define M_PCMCIA_CFG_APWRONEN   _SB_MAKEMASK1(5)
 216 #define M_PCMCIA_CFG_CDMASK     _SB_MAKEMASK1(6)
 217 #define M_PCMCIA_CFG_WPMASK     _SB_MAKEMASK1(7)
 218 #define M_PCMCIA_CFG_RDYMASK    _SB_MAKEMASK1(8)
 219 #define M_PCMCIA_CFG_PWRCTL     _SB_MAKEMASK1(9)
 220
 221 /*
 222  * PCMCIA status register (Table 12-7)
 223  */
 224
 225 #define M_PCMCIA_STATUS_CD1     _SB_MAKEMASK1(0)
 226 #define M_PCMCIA_STATUS_CD2     _SB_MAKEMASK1(1)
 227 #define M_PCMCIA_STATUS_VS1     _SB_MAKEMASK1(2)
 228 #define M_PCMCIA_STATUS_VS2     _SB_MAKEMASK1(3)
 229 #define M_PCMCIA_STATUS_WP      _SB_MAKEMASK1(4)
 230 #define M_PCMCIA_STATUS_RDY     _SB_MAKEMASK1(5)
 231 #define M_PCMCIA_STATUS_3VEN    _SB_MAKEMASK1(6)
 232 #define M_PCMCIA_STATUS_5VEN    _SB_MAKEMASK1(7)
 233 #define M_PCMCIA_STATUS_CDCHG   _SB_MAKEMASK1(8)
 234 #define M_PCMCIA_STATUS_WPCHG   _SB_MAKEMASK1(9)
 235 #define M_PCMCIA_STATUS_RDYCHG  _SB_MAKEMASK1(10)
 236
 237 /*
 238  * GPIO Interrupt Type Register (table 13-3)
 239  */
 240
 241 #define K_GPIO_INTR_DISABLE     0
 242 #define K_GPIO_INTR_EDGE        1
 243 #define K_GPIO_INTR_LEVEL       2
 244 #define K_GPIO_INTR_SPLIT       3
 245
 246 #define S_GPIO_INTR_TYPEX(n)    (((n)/2)*2)
 247 #define M_GPIO_INTR_TYPEX(n)    _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n))
 248 #define V_GPIO_INTR_TYPEX(n,x)  _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n))
 249 #define G_GPIO_INTR_TYPEX(n,x)  _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n))
 250
 251 #define S_GPIO_INTR_TYPE0       0
 252 #define M_GPIO_INTR_TYPE0       _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0)
 253 #define V_GPIO_INTR_TYPE0(x)    _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0)
 254 #define G_GPIO_INTR_TYPE0(x)    _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0)
 255
 256 #define S_GPIO_INTR_TYPE2       2
 257 #define M_GPIO_INTR_TYPE2       _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2)
 258 #define V_GPIO_INTR_TYPE2(x)    _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2)
 259 #define G_GPIO_INTR_TYPE2(x)    _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2)
 260
 261 #define S_GPIO_INTR_TYPE4       4
 262 #define M_GPIO_INTR_TYPE4       _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4)
 263 #define V_GPIO_INTR_TYPE4(x)    _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4)
 264 #define G_GPIO_INTR_TYPE4(x)    _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4)
 265
 266 #define S_GPIO_INTR_TYPE6       6
 267 #define M_GPIO_INTR_TYPE6       _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6)
 268 #define V_GPIO_INTR_TYPE6(x)    _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6)
 269 #define G_GPIO_INTR_TYPE6(x)    _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6)
 270
 271 #define S_GPIO_INTR_TYPE8       8
 272 #define M_GPIO_INTR_TYPE8       _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8)
 273 #define V_GPIO_INTR_TYPE8(x)    _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8)
 274 #define G_GPIO_INTR_TYPE8(x)    _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8)
 275
 276 #define S_GPIO_INTR_TYPE10      10
 277 #define M_GPIO_INTR_TYPE10      _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10)
 278 #define V_GPIO_INTR_TYPE10(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10)
 279 #define G_GPIO_INTR_TYPE10(x)   _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10)
 280
 281 #define S_GPIO_INTR_TYPE12      12
 282 #define M_GPIO_INTR_TYPE12      _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12)
 283 #define V_GPIO_INTR_TYPE12(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12)
 284 #define G_GPIO_INTR_TYPE12(x)   _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12)
 285
 286 #define S_GPIO_INTR_TYPE14      14
 287 #define M_GPIO_INTR_TYPE14      _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14)
 288 #define V_GPIO_INTR_TYPE14(x)   _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14)
 289 #define G_GPIO_INTR_TYPE14(x)   _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14)
 290
 291
 292 #endif