release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/include/sb1250_draminit.h

   1 /*  *********************************************************************
   2     *  Broadcom Common Firmware Environment (CFE)
   3     *
   4     *  DRAM Initialization routine definitions  File: sb1250_draminit.h
   5     *
   6     *  This file contains constants and data structures specific to
   7     *  the operation of sb1250_draminit.c
   8     *
   9     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  10     *
  11     *********************************************************************
  12     *
  13     *  Copyright 2000,2001,2002,2003
  14     *  Broadcom Corporation. All rights reserved.
  15     *
  16     *  This software is furnished under license and may be used and
  17     *  copied only in accordance with the following terms and
  18     *  conditions.  Subject to these conditions, you may download,
  19     *  copy, install, use, modify and distribute modified or unmodified
  20     *  copies of this software in source and/or binary form.  No title
  21     *  or ownership is transferred hereby.
  22     *
  23     *  1) Any source code used, modified or distributed must reproduce
  24     *     and retain this copyright notice and list of conditions
  25     *     as they appear in the source file.
  26     *
  27     *  2) No right is granted to use any trade name, trademark, or
  28     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  29     *     name may not be used to endorse or promote products derived
  30     *     from this software without the prior written permission of
  31     *     Broadcom Corporation.
  32     *
  33     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  34     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  35     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  36     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  37     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  38     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  39     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  41     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  42     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  43     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  44     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  45     *     THE POSSIBILITY OF SUCH DAMAGE.
  46     ********************************************************************* */
  47
  48 #ifndef _SB1250_DEFS_H
  49 #include "sb1250_defs.h"                /* needed for _SB_MAKExx macros */
  50 #endif
  51
  52 #ifndef _SB1250_MC_H
  53 #include "sb1250_mc.h"                  /* memory controller constants */
  54 #endif
  55
  56
  57 /*  *********************************************************************
  58     *  DRAMINFO macros - used to construct the DRAM information
  59     *  table.  There are two flavors, for "C" and assembly.
  60     ********************************************************************* */
  61
  62
  63 /*
  64  * This macro generates a "decimals and tenths" hex value like those used
  65  * in an SPD.  'x' is the decimal portion and 't' is the tenths.  It's
  66  * sort of like a BCD value except 'x' can contain 0..15
  67  *
  68  * This macro needs to be used for the tCK parameter.
  69  *
  70  * For example, to specify 7.5, you could say DRT10(7,5)
  71  */
  72
  73 #define DRT10(x,t) (((x)<<4)|(t))
  74
  75 /*
  76  * This macro generates "decimals and quarters" like those used
  77  * in an SPD.  The 'q' parameter should be 0, 25, 50, or 75
  78  * This macro needs to be used by tRP, tRRD, rRCD, tRFC, adn tRC
  79  *
  80  * For example, to specify 20.25, you could say DRT4(20,25)
  81  */
  82
  83 #define DRT4(x,q) (((x)<<2)|((q)/25))
  84
  85
  86
  87 #ifdef __ASSEMBLER__
  88 #define DRAM_GLOBALS(chintlv) \
  89           .byte MCR_GLOBALS,chintlv,0,0,0,0,0,0,0,0,0,0 ;
  90 #define DRAM_CHAN_CFG(chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg) \
  91           .byte MCR_CHCFG,chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg,0,0,0 ;
  92 #define DRAM_CHAN_CFG2(chan,tMEMCLK,tROUNDTRIP,dramtype,pagepolicy,blksize,csintlv,ecc,flg) \
  93           .byte MCR_CHCFG,chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg,tROUNDTRIP,0,0 ;
  94 #define DRAM_CHAN_CLKCFG(addrskew,dqoskew,dqiskew,addrdrive,datadrive,clkdrive) \
  95           .byte MCR_CLKCFG,addrskew,dqoskew,dqiskew,addrdrive,datadrive,clkdrive,0,0,0,0,0 ;
  96 #define DRAM_CHAN_MANTIMING(tCK,rfsh,tval) \
  97           .byte MCR_MANTIMING,tCK,rfsh,0 ; \
  98           .byte (((tval) >> 56)&0xFF), (((tval) >> 48) & 0xFF) ; \
  99           .byte (((tval) >> 40)&0xFF), (((tval) >> 32) & 0xFF) ; \
 100           .byte (((tval) >> 24)&0xFF), (((tval) >> 16) & 0xFF) ; \
 101           .byte (((tval) >>  8)&0xFF), (((tval) >>  0) & 0xFF) ;
 102 #define DRAM_CS_TIMING(tCK,rfsh,caslatency,attributes,tRAS,tRP,tRRD,tRCD,tRFC,tRC) \
 103           .byte MCR_TIMING,tCK,rfsh,caslatency,attributes,tRAS,tRP,tRRD,tRCD,tRFC,tRC,0 ;
 104 #define DRAM_CS_GEOM(csel,rows,cols,banks) \
 105           .byte MCR_GEOM,csel,rows,cols,banks,0,0,0,0,0,0,0 ;
 106 #define DRAM_CS_SPD(csel,flags,chan,dev) \
 107           .byte MCR_SPD,csel,flags,chan,dev,0,0,0,0,0,0,0 ;
 108 #define DRAM_EOT \
 109           .byte MCR_EOT,0,0,0,0,0,0,0,0,0,0,0 ;
 110 #else
 111 #define DRAM_GLOBALS(chintlv) \
 112           {MCR_GLOBALS,chintlv,0,0,0,0,0,0,0,0,0,0}
 113 #define DRAM_CHAN_CFG(chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg) \
 114           {MCR_CHCFG,chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg,0,0,0}
 115 #define DRAM_CHAN_CFG2(chan,tMEMCLK,tROUNDTRIP,dramtype,pagepolicy,blksize,csintlv,ecc,flg) \
 116           {MCR_CHCFG,chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg,tROUNDTRIP,0,0}
 117 #define DRAM_CHAN_CLKCFG(addrskew,dqoskew,dqiskew,addrdrive,datadrive,clkdrive) \
 118           {MCR_CLKCFG,addrskew,dqoskew,dqiskew,addrdrive,datadrive,clkdrive,0,0,0,0,0}
 119 #define DRAM_CHAN_MANTIMING(tCK,rfsh,tval) \
 120           {MCR_MANTIMING,tCK,rfsh,0,  \
 121           (((tval) >> 56)&0xFF), (((tval) >> 48) & 0xFF),  \
 122           (((tval) >> 40)&0xFF), (((tval) >> 32) & 0xFF),  \
 123           (((tval) >> 24)&0xFF), (((tval) >> 16) & 0xFF),  \
 124           (((tval) >>  8)&0xFF), (((tval) >>  0) & 0xFF) }
 125 #define DRAM_CS_TIMING(tCK,rfsh,caslatency,attributes,tRAS,tRP,tRRD,tRCD,tRFC,tRC) \
 126           {MCR_TIMING,tCK,rfsh,caslatency,attributes,tRAS,tRP,tRRD,tRCD,tRFC,tRC,0}
 127 #define DRAM_CS_GEOM(csel,rows,cols,banks) \
 128           {MCR_GEOM,csel,rows,cols,banks,0,0,0,0,0,0,0}
 129 #define DRAM_CS_SPD(csel,flags,chan,dev) \
 130           {MCR_SPD,csel,flags,chan,dev,0,0,0,0,0,0,0}
 131 #define DRAM_EOT \
 132           {MCR_EOT,0,0,0,0,0,0,0,0,0,0,0}
 133 #endif
 134
 135
 136 #define MCR_GLOBALS     0
 137 #define MCR_CHCFG       1
 138 #define MCR_TIMING      2
 139 #define MCR_CLKCFG      3
 140 #define MCR_GEOM        4
 141 #define MCR_SPD         5
 142 #define MCR_MANTIMING   6
 143 #define MCR_EOT         0xFF
 144
 145 #ifndef __ASSEMBLER__
 146 typedef struct mc_initrec_s {
 147     uint8_t mcr_type;                   /* record type */
 148     uint8_t mcr_reserved1;              /* pad to 12 bytes */
 149     uint8_t mcr_reserved2;              /* pad to 12 bytes */
 150     uint8_t mcr_reserved3;              /* pad to 12 bytes */
 151     uint8_t mcr_reserved4;              /* pad to 12 bytes */
 152     uint8_t mcr_reserved5;              /* pad to 12 bytes */
 153     uint8_t mcr_reserved6;              /* pad to 12 bytes */
 154     uint8_t mcr_reserved7;              /* pad to 12 bytes */
 155     uint8_t mcr_reserved8;              /* pad to 12 bytes */
 156     uint8_t mcr_reserved9;              /* pad to 12 bytes */
 157     uint8_t mcr_reserved10;             /* pad to 12 bytes */
 158     uint8_t mcr_reserved11;             /* pad to 12 bytes */
 159 } mc_initrec_t;
 160
 161 typedef struct mc_globals_s {
 162     uint8_t gbl_type;
 163     uint8_t gbl_intlv_ch;               /* true to interleave channels */
 164     uint8_t gbl_reserved[10];           /* pad to 12 bytes */
 165 } mc_globals_t;
 166
 167 typedef struct mc_mantiming_s {
 168     uint8_t mtm_type;
 169     uint8_t mtm_tCK;
 170     uint8_t mtm_rfsh;
 171     uint8_t mtm_reserved;
 172     uint8_t mtm_timing[8];              /* one 64-bit word, as bytes */
 173 } mc_mantiming_t;
 174
 175 typedef struct mc_cfgdata_s {
 176     uint8_t cfg_type;
 177     uint8_t cfg_chan;
 178     uint8_t cfg_mintmemclk;
 179     uint8_t cfg_dramtype;
 180     uint8_t cfg_pagepolicy;
 181     uint8_t cfg_blksize;
 182     uint8_t cfg_intlv_cs;
 183     uint8_t cfg_ecc;
 184     uint8_t cfg_flags;
 185     uint8_t cfg_roundtrip;
 186     uint8_t cfg_reserved[2];
 187 } mc_cfgdata_t;
 188
 189 typedef struct mc_clkcfg_s {
 190     uint8_t clk_type;
 191     uint8_t clk_addrskew;
 192     uint8_t clk_dqoskew;
 193     uint8_t clk_dqiskew;
 194     uint8_t clk_addrdrive;
 195     uint8_t clk_datadrive;
 196     uint8_t clk_clkdrive;
 197     uint8_t clk_reserved[5];
 198 } mc_clkcfg_t;
 199
 200 typedef struct mc_timingdata_s {
 201     uint8_t tmg_type;                   /* record type */
 202     uint8_t tmg_tCK;                    /* tCK we should use */
 203     uint8_t tmg_rfsh;                   /* SPD[12] Refresh Rate */
 204     uint8_t tmg_caslatency;             /* SPD[18] CAS Latencies Supported (set only one bit) */
 205     uint8_t tmg_attributes;             /* SPD[21] Attributes */
 206     uint8_t tmg_tRAS;                   /* SPD[30] */
 207     uint8_t tmg_tRP;                    /* SPD[27] */
 208     uint8_t tmg_tRRD;                   /* SPD[28] */
 209     uint8_t tmg_tRCD;                   /* SPD[29] */
 210     uint8_t tmg_tRFC;                   /* SPD[42] */
 211     uint8_t tmg_tRC;                    /* SPD[41] */
 212     uint8_t tmg_reserved;               /* not used */
 213 } mc_timingdata_t;
 214
 215 typedef struct mc_geomdata_s {
 216     uint8_t geom_type;                  /* record type */
 217     uint8_t geom_csel;                  /* Chip Select number */
 218     uint8_t geom_rows;                  /* rows */
 219     uint8_t geom_cols;                  /* columns */
 220     uint8_t geom_banks;                 /* banks */
 221     uint8_t geom_reserved[7];           /* pad to 12 bytes */
 222 } mc_geomdata_t;
 223
 224 typedef struct mc_spddata_s {
 225     uint8_t spd_type;                   /* record type */
 226     uint8_t spd_csel;                   /* Chip Select number */
 227     uint8_t spd_flags;                  /* flags */
 228     uint8_t spd_smbuschan;              /* SMBus Channel */
 229     uint8_t spd_smbusdev;               /* SMBus device */
 230     uint8_t spd_reserved[7];            /* pad to 12 bytes */
 231 } mc_spddata_t;
 232
 233 typedef union draminittab_s {
 234     mc_initrec_t mcr;                   /* record with just header */
 235     mc_globals_t gbl;                   /* global data */
 236     mc_cfgdata_t cfg;                   /* channel configuration data */
 237     mc_clkcfg_t clk;                    /* clock configuration */
 238     mc_timingdata_t tmg;                /* timing data */
 239     mc_geomdata_t geom;                 /* geometry data */
 240     mc_spddata_t spd;                   /* SPD data */
 241     mc_mantiming_t mtm;                 /* manual timing */
 242     uint8_t raw[12];                    /* RAW data */
 243 } draminittab_t;
 244
 245 #endif
 246
 247
 248
 249 /*  *********************************************************************
 250     *  JEDEC constants (serial presence detect offsets and bit fields)
 251     ********************************************************************* */
 252
 253 #define JEDEC_SPD_MEMTYPE       2       /* memory type (sdram, ddr, etc.) */
 254 #define JEDEC_SPD_ROWS          3       /* row bits */
 255 #define JEDEC_SPD_COLS          4       /* column bits */
 256 #define JEDEC_SPD_SIDES         5       /* number of sides */
 257 #define JEDEC_SPD_WIDTH         6       /* and 7, bit width of device */
 258 #define JEDEC_SPD_BANKS         17      /* number of banks */
 259 #define JEDEC_SPD_DENSITY       31      /* module bank density */
 260
 261 #define JEDEC_SPD_tCK25         9       /* tCK @ CAS 2.5 */
 262 #define JEDEC_SPD_tCK20         23      /* tCK @ CAS 2.0 */
 263 #define JEDEC_SPD_tCK10         25      /* tCK @ CAS 1.0 */
 264 #define JEDEC_SPD_RFSH          12      /* refresh rate */
 265 #define JEDEC_SPD_CASLATENCIES  18      /* CAS Latencies supported */
 266 #define JEDEC_SPD_ATTRIBUTES    21      /* module attributes */
 267 #define JEDEC_SPD_tRAS          30      /* tRAS */
 268 #define JEDEC_SPD_tRP           27      /* tRP */
 269 #define JEDEC_SPD_tRRD          28      /* tRRD */
 270 #define JEDEC_SPD_tRCD          29      /* tRCD */
 271 #define JEDEC_SPD_tRFC          42      /* tRFC */
 272 #define JEDEC_SPD_tRC           41      /* tRC */
 273
 274 #define JEDEC_SPD_MAX           44      /* highest SPD value we will read */
 275
 276 #define JEDEC_MEMTYPE_DDRSDRAM  1
 277 #define JEDEC_MEMTYPE_DDRSDRAM2 7
 278 #define JEDEC_MEMTYPE_SDRAM     4
 279 #define SPD_MEMTYPE_FCRAM       8       /* CFE specific to support FCRAM dimms */
 280
 281 #define JEDEC_CASLAT_35         0x20
 282 #define JEDEC_CASLAT_30         0x10
 283 #define JEDEC_CASLAT_25         0x08
 284 #define JEDEC_CASLAT_20         0x04
 285 #define JEDEC_CASLAT_15         0x02
 286 #define JEDEC_CASLAT_10         0x01
 287
 288 #define JEDEC_ATTRIB_REG        0x02
 289
 290 #define JEDEC_RFSH_MASK         0x7F
 291 #define JEDEC_RFSH_64khz        0
 292 #define JEDEC_RFSH_256khz       1
 293 #define JEDEC_RFSH_128khz       2
 294 #define JEDEC_RFSH_32khz        3
 295 #define JEDEC_RFSH_16khz        4
 296 #define JEDEC_RFSH_8khz         5
 297
 298 /*  *********************************************************************
 299     *  Configuration parameter values and flag shorthands to improve
 300     *  readability of the tables.
 301     ********************************************************************* */
 302
 303
 304 #define CLOSED                  K_MC_CS_ATTR_CLOSED
 305 #define CASCHECK                K_MC_CS_ATTR_CASCHECK
 306 #define HINT                    K_MC_CS_ATTR_HINT
 307 #define OPEN                    K_MC_CS_ATTR_OPEN
 308
 309 #define JEDEC                   K_MC_DRAM_TYPE_JEDEC
 310 #define FCRAM                   K_MC_DRAM_TYPE_FCRAM
 311 #define SGRAM                   K_MC_DRAM_TYPE_SGRAM
 312 #define DRAM_TYPE_SPD   3
 313
 314 #define ECCENABLE       1       /* ECC enable DRAM_CHANCFG */
 315 #define ECCDISABLE      0
 316
 317 #define BLKSIZE32       32      /* Block size */
 318 #define BLKSIZE64       64
 319 #define BLKSIZE128      128
 320
 321 #define MCFLG_ECC_ENABLE 1     /* flags for channel configuration */
 322 #define MCFLG_BIGMEM    2
 323 #define MCFLG_FORCEREG  4
 324
 325 #define MC_CHAN0        0      /* shorthands for readability */
 326 #define MC_CHAN1        1
 327
 328 #define MC_NOPORTINTLV  0      /* Used in DRAM_GLOBALS() */
 329 #define MC_PORTINTLV    1
 330
 331 #define MC_CS0          0      /* shorthands for readability */
 332 #define MC_CS1          1
 333 #define MC_CS2          2
 334 #define MC_CS3          3
 335
 336 #define NOCSINTLV       0       /* Chip select interleave values */
 337 #define CSINTLV1        1
 338 #define CSINTLV2        2
 339
 340 /*
 341  * End
 342  */