1 /* *********************************************************************
2 * P6064 Board Support Package
4 * CPU initialization File: rm7000_cpuinit.S
6 * This module contains code to initialize the CPU cores.
8 * Note: all the routines in this module rely on registers only,
9 * since DRAM may not be active yet.
11 * Author: Mitch Lichtenberg (mpl@broadcom.com)
13 *********************************************************************
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
18 * This software is furnished under license and may be used and
19 * copied only in accordance with the following terms and
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22 * copies of this software in source and/or binary form. No title
23 * or ownership is transferred hereby.
25 * 1) Any source code used, modified or distributed must reproduce
26 * and retain this copyright notice and list of conditions
27 * as they appear in the source file.
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31 * name may not be used to endorse or promote products derived
32 * from this software without the prior written permission of
33 * Broadcom Corporation.
35 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
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37 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
38 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
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40 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
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48 ********************************************************************* */
51 #include "bsp_config.h"
58 /* *********************************************************************
60 ********************************************************************* */
63 /* *********************************************************************
64 * RM7000_ZERO_INT_REGS
66 * Zero all the CPU's integer registers *except* FP, which we're
67 * using within cpu_init to hold its return address.
73 * nothing - all registers (except ra/R31) zero
74 ********************************************************************* */
76 LEAF(RM7000_zero_int_regs)
116 /* note: do NOT zero k0/k1 here: it's used by VAPI exit. */
122 /* note: do NOT zero fp here */
126 END(RM7000_zero_int_regs)
129 /* *********************************************************************
130 * RM7000_ZERO_FP_REGS()
132 * Initialize the CP1 (floating-point) registers
139 ********************************************************************* */
141 LEAF(RM7000_zero_fp_regs)
143 mfc0 v0,C0_SR /* Get old SR_CU1 value */
144 or v1,v0,M_SR_CU1 /* Turn on coprocessor 1 */
145 or v1,v1,M_SR_FR /* in 32-register mode */
148 ssnop /* wait for mtc0 to finish */
156 cfc1 v1,$0 /* get FP impl register */
157 beq v1,zero,no_fp /* don't do this if no FP */
159 ctc1 zero,$31 /* Exception/status register */
161 dmtc1 zero,$f0 /* general data registers */
194 no_fp: mtc0 v0,C0_SR /* restore to original state */
197 END(RM7000_zero_fp_regs)
199 /* *********************************************************************
202 * Initialize CP0 registers for an RM7000 core
209 ********************************************************************* */
211 LEAF(RM7000_cp0_init)
214 mtc0 zero,C0_WATCHLO # Clear out the watch regs.
217 mfc0 v0,C0_SR # Get status register
218 and v0,M_SR_SR # preserve soft reset
219 or v0,M_SR_BEV # exceptions to boot vector
221 mtc0 zero,C0_CAUSE # must clear before writing SR
223 mtc0 v0,C0_SR # set up the status register
225 mfc0 v0,C0_CONFIG # get current CONFIG register
226 srl v0,v0,3 # strip out K0 bits
227 sll v0,v0,3 # k0 bits now zero
228 or v0,v0,K_CFG_K0COH_COHERENT # K0 is cacheable.
231 mtc0 zero,C0_WATCHLO,0 # Watch registers.
232 mtc0 zero,C0_WATCHHI,0
233 mtc0 zero,C0_WATCHLO,1
234 mtc0 zero,C0_WATCHHI,1
236 mtc0 zero,C0_TLBHI # TLB entry (high half)
239 # This is probably not the right init value for C0_COMPARE,
240 # but it seems to be necessary for the sim model right now.
247 # Initialize all the TLB entries to some invalid value
250 mtc0 zero,C0_TLBLO0 /* tlblo0 = invalid */
251 mtc0 zero,C0_TLBLO1 /* tlblo1 = invalid */
253 li t0,K1BASE /* tlbhi = impossible vpn */
254 li t1,(K_NTLBENTRIES-1) /* index */
260 addu t0,0x2000 /* inc vpn */
274 /* *********************************************************************
276 ********************************************************************* */