release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/p6064/include/rtc.h

   1 /*
   2  * p6032/rtc.h: PC-style real-time clock register definitions
   3  *
   4  * Copyright (c) 2000, Algorithmics Ltd.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the "Free MIPS" License Agreement, a copy of
   8  * which is available at:
   9  *
  10  *  http://www.algor.co.uk/ftp/pub/doc/freemips-license.txt
  11  *
  12  * You may not, however, modify or remove any part of this copyright
  13  * message if this program is redistributed or reused in whole or in
  14  * part.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * "Free MIPS" License for more details.
  20  */
  21
  22 /*
  23  * RTC Register locations
  24  */
  25 #define RTC_SEC         0x00    /* seconds */
  26 #define RTC_SECALRM     0x01    /* seconds alarm */
  27 #define RTC_MIN         0x02    /* minutes */
  28 #define RTC_MINALRM     0x03    /* minutes alarm */
  29 #define RTC_HRS         0x04    /* hours */
  30 #define RTC_HRSALRM     0x05    /* hours alarm */
  31 #define RTC_WDAY        0x06    /* week day */
  32 #define RTC_DAY         0x07    /* day of month */
  33 #define RTC_MONTH       0x08    /* month of year */
  34 #define RTC_YEAR        0x09    /* month of year */
  35 #define RTC_STATUSA     0x0a    /* status register A */
  36 #define  RTCSA_UIP       0x80   /* update in progress */
  37 #define  RTCSA_DVMASK    0x70   /* divisor select mask (see below) */
  38 #define  RTCSA_RSMASK    0x0f   /* interrupt rate select mask (see below) */
  39 #define RTC_STATUSB     0x0b    /* status register B */
  40 #define  RTCSB_UTI       0x80   /* update transfer inhibit */
  41 #define  RTCSB_PIE       0x40   /* periodic i/u enable */
  42 #define  RTCSB_AIE       0x20   /* alarm i/u enable */
  43 #define  RTCSB_UIE       0x10   /* update cycle i/u enable */
  44 #define  RTCSB_SQWE      0x08   /* square wave enable */
  45 #define  RTCSB_BINARY    0x04   /* data format (1=binary, 0=bcd) */
  46 #define  RTCSB_24HR      0x02   /* hour format (1=24 hour) */
  47 #define  RTCSB_DSE       0x01   /* daylight savings enable! */
  48 #define RTC_INTR        0x0c    /* status register C (R) interrupt source */
  49 #define  RTCIR_INTF      0x80   /* i/u output signal */
  50 #define  RTCIR_PF        0x40   /* periodic i/u */
  51 #define  RTCIR_AF        0x20   /* alarm i/u */
  52 #define  RTCIR_UF        0x10   /* update i/u */
  53 #define  RTCIR_32KE      0x04   /* enable 32kHz output */
  54 #define RTC_STATUSD     0x0d    /* status register D (R) Lost Power */
  55 #define  RTCSD_VRT       0x80   /* clock has valid backup power */
  56 #define RTC_CENTURY     0x0e    /* current century - increment in Dec 99 */
  57
  58 #define RTC_NTODREGS    (RTC_CENTURY+1)
  59
  60 #define RTC_NVSTART     RTC_NTODREGS
  61 #define RTC_NVSIZE      (128-RTC_NTODREGS)
  62 #define RTC_SIZE        (256-RTC_NTODREGS)
  63
  64 /*
  65  * Time base (divisor select) constants (Control register A)
  66  */
  67 #define RTC_OSC_ON      0x20    /* 32KHz crystal */
  68 #define RTC_OSC_32KHz   0x30    /* 32KHz crystal; 32KHz square wave */
  69 #define RTC_OSC_NONE    0x60    /* actually, both of these reset */
  70 #define RTC_OSC_RESET   0x70
  71 #define RTC_DV0_OSC_NONE 0x00   /* PC97307: bank0 oscillator disabled */
  72 #define RTC_DV0_OSC_ON  0x20    /* PC97307: bank1 oscillator enabled */
  73 #define RTC_DV1_OSC_ON  0x30    /* PC97307: bank2 oscillator enabled */
  74 #define RTC_DV2_OSC_ON  0x40    /* PC97307: bank3 oscillator enabled */
  75 #define RTC_RATE_MASK   0x0f    /* No periodic interrupt */
  76 #define RTC_RATE_NONE   0x00    /* No periodic interrupt */
  77 #define RTC_RATE_8192Hz 0x03    /* 122.070 us period */
  78 #define RTC_RATE_4096Hz 0x04    /* 244.141 us period */
  79 #define RTC_RATE_2048Hz 0x05    /* 488.281 us period */
  80 #define RTC_RATE_1024Hz 0x06    /* 976.562 us period */
  81 #define RTC_RATE_512Hz  0x07    /* 1.953125 ms period */
  82 #define RTC_RATE_256Hz  0x08    /* 3.90625 ms period */
  83 #define RTC_RATE_128Hz  0x09    /* 7.8125 ms period */
  84 #define RTC_RATE_64Hz   0x0a    /* 15.625 ms period */
  85 #define RTC_RATE_32Hz   0x0b    /* 31.25 ms period */
  86 #define RTC_RATE_16Hz   0x0c    /* 62.5 ms period */
  87 #define RTC_RATE_8Hz    0x0d    /* 125 ms period */
  88 #define RTC_RATE_4Hz    0x0e    /* 250 ms period */
  89 #define RTC_RATE_2Hz    0x0f    /* 500 ms period */
  90
  91 /* PC97037 specific definitions */
  92
  93 #define RTC_BANK1_CENTURY       0x48
  94 #define RTC_BANK1_URADDR        0x50
  95 #define RTC_BANK1_URDATA        0x53
  96
  97 #define RTC_BANK2_APCR1         0x40
  98 #define RTC_BANK2_APCR2         0x41
  99 #define RTC_BANK2_APCSR         0x42
 100 #define RTC_BANK2_WDAY_WAKEUP   0x43
 101 #define RTC_BANK2_DAY_WAKEUP    0x44
 102 #define RTC_BANK2_MONTH_WAKEUP  0x45
 103 #define RTC_BANK2_MONTH_YEAR    0x46
 104 #define RTC_BANK2_RAMLOCK       0x47
 105 #define RTC_BANK2_CENTURY_WAKEUP 0x48
 106
 107 #define APCR1_SWITCHOFFDELAY    0x02
 108 #define APCR1_LEVELPOR          0x04
 109 #define APCR1_CLEARPOR          0x08
 110 #define APCR1_MOAP              0x10
 111 #define APCR1_SOC               0x20
 112 #define APCR1_FAILSAFESTOP      0x40
 113 #define APCR1_POWERFAILURE      0x80
 114
 115 #ifndef __ASSEMBLER__
 116 unsigned int _rtc_get (int);
 117 unsigned int _rtc_set (int, unsigned int);
 118 unsigned int _rtc_bis (int, unsigned int);
 119 unsigned int _rtc_bic (int, unsigned int);
 120
 121 unsigned int _apc_get (int);
 122 unsigned int _apc_set (int, unsigned int);
 123 unsigned int _apc_bis (int, unsigned int);
 124 unsigned int _apc_bic (int, unsigned int);
 125 #endif