1 /* *********************************************************************
2 * SB1250 Board Support Package
4 * Board-specific initialization File: C3_INIT.S
6 * This module contains the assembly-language part of the init
7 * code for this board support package. The routine
8 * "board_earlyinit" lives here.
10 * Author: Mitch Lichtenberg (mpl@broadcom.com)
12 *********************************************************************
14 * Copyright 2000,2001,2002,2003
15 * Broadcom Corporation. All rights reserved.
17 * This software is furnished under license and may be used and
18 * copied only in accordance with the following terms and
19 * conditions. Subject to these conditions, you may download,
20 * copy, install, use, modify and distribute modified or unmodified
21 * copies of this software in source and/or binary form. No title
22 * or ownership is transferred hereby.
24 * 1) Any source code used, modified or distributed must reproduce
25 * and retain this copyright notice and list of conditions
26 * as they appear in the source file.
28 * 2) No right is granted to use any trade name, trademark, or
29 * logo of Broadcom Corporation. The "Broadcom Corporation"
30 * name may not be used to endorse or promote products derived
31 * from this software without the prior written permission of
32 * Broadcom Corporation.
34 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
35 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
36 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
37 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
38 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
39 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
41 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
42 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
43 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
44 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
45 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
46 * THE POSSIBILITY OF SUCH DAMAGE.
47 ********************************************************************* */
51 #include "sb1250_genbus.h"
52 #include "sb1250_uart.h"
53 #include "sb1250_regs.h"
54 #include "bsp_config.h"
56 #include "mipsmacros.h"
57 #include "sb1250_draminit.h"
61 /*#define _SERIAL_PORT_LEDS_*/
63 /* *********************************************************************
65 ********************************************************************* */
68 /* *********************************************************************
71 * Initialize board registers. This is the earliest
72 * time the BSP gets control. This routine cannot assume that
73 * memory is operational, and therefore all code in this routine
74 * must run from registers only. The $ra register must not
75 * be modified, as it contains the return address.
77 * This routine will be called from uncached space, before
78 * the caches are initialized. If you want to make
79 * subroutine calls from here, you must use the CALLKSEG1 macro.
81 * Among other things, this is where the GPIO registers get
82 * programmed to make on-board LEDs function, or other startup
83 * that has to be done before anything will work.
90 ********************************************************************* */
98 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
99 li t1,GPIO_INTERRUPT_MASK
103 # Turn off the diagnostic LED.
105 li t0,PHYS_TO_K1(A_GPIO_PIN_CLR)
106 li t1,M_GPIO_DEBUG_LED
110 # Set the PGM_L pin to '1' to allow programming via JTAG
113 li t0,PHYS_TO_K1(A_GPIO_PIN_SET)
114 li t1,M_GPIO_XPROG_X_PGM_L
122 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
123 li t1,GPIO_OUTPUT_MASK
129 # Configure the alternate boot ROM
132 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
134 li t1,ALT_BOOTROM_PHYS >> S_IO_ADDRBASE
135 sd t1,R_IO_EXT_START_ADDR(t0)
137 li t1,ALT_BOOTROM_SIZE-1
138 sd t1,R_IO_EXT_MULT_SIZE(t0)
140 li t1,ALT_BOOTROM_TIMING0
141 sd t1,R_IO_EXT_TIME_CFG0(t0)
143 li t1,ALT_BOOTROM_TIMING1
144 sd t1,R_IO_EXT_TIME_CFG1(t0)
146 li t1,ALT_BOOTROM_CONFIG
147 sd t1,R_IO_EXT_CFG(t0)
150 # Configure the Xilinx
153 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(XILINX_CS))
155 li t1,XILINX_PHYS >> S_IO_ADDRBASE
156 sd t1,R_IO_EXT_START_ADDR(t0)
159 sd t1,R_IO_EXT_MULT_SIZE(t0)
162 sd t1,R_IO_EXT_TIME_CFG0(t0)
165 sd t1,R_IO_EXT_TIME_CFG1(t0)
168 sd t1,R_IO_EXT_CFG(t0)
171 # Make sure that the mailbox register is cleared
174 li t0,PHYS_TO_K1(A_IMR_REGISTER(0,R_IMR_MAILBOX_CLR_CPU))
178 #ifdef _SERIAL_PORT_LEDS_
180 # Program the mode register for 8 bits/char, no parity
182 li t0,PHYS_TO_K1(A_DUART_MODE_REG_1_A)
183 li t1,V_DUART_BITS_PER_CHAR_8 | V_DUART_PARITY_MODE_NONE
186 # Program the mode register for 1 stop bit, ignore CTS
188 li t0,PHYS_TO_K1(A_DUART_MODE_REG_2_A)
189 li t1,M_DUART_STOP_BIT_LEN_1
192 # Program the baud rate to 115200
194 li t0,PHYS_TO_K1(A_DUART_CLK_SEL_A)
195 li t1,V_DUART_BAUD_RATE(115200)
198 # Dont use any interrupts
200 li t0,PHYS_TO_K1(A_DUART_IMR)
202 and t1,~M_DUART_IMR_ALL_A
205 # Enable sending and receiving
207 li t0,PHYS_TO_K1(A_DUART_CMD_A)
208 li t1,M_DUART_RX_EN | M_DUART_TX_EN
219 /* *********************************************************************
222 * Return the address of the DRAM information table
228 * v0 - DRAM info table, return 0 to use default table
229 ********************************************************************* */
235 # This board has soldered-down memory.
247 #if defined(_C3_) || defined(_C3H_) || defined(_SIM_C3_)
250 * C3: SGRAMs and SDRAMs
252 * This board has soldered-down memory.
255 DRAM_GLOBALS(MC_NOPORTINTLV) /* no port interleaving */
258 * 16MB on MC 0 (SGRAM)
259 * Micron MT46V2M32LG-65
261 * Minimum tMEMCLK: 8.0ns (125Mhz max freq)
263 * CS0 Geometry: 11 rows, 8 columns, 2 bankbits
265 * 128khz refresh, CAS Latency 3.0
266 * Timing (ns): tCK=7.50 tRAS=40 tRP=19.50 tRRD=13.0 tRCD=19.50 tRFC=66 tRC=59
268 * Clock Config: Addrskew 0x0F, DQOskew 0x08, DQIskew 0x08, addrdrive 0x07, datadrive 0x07, clockdrive 0x00
272 DRAM_CHAN_CFG(MC_CHAN0, DRT10(8,0), SGRAM, CASCHECK, BLKSIZE32, NOCSINTLV, CFG_DRAM_ECC, 0)
273 DRAM_CHAN_CLKCFG(0x0F, 0x08, 0x08, 0x07, 0x07, 0x00)
275 DRAM_CS_GEOM(MC_CS0, 11, 8, 2)
276 DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_128khz, JEDEC_CASLAT_30, 0, 40, DRT4(19,50) ,DRT4(13,0), DRT4(19,50), 66 , 59)
279 * 512MB on MC 1 (JEDEC SDRAM)
282 * Minimum tMEMCLK: 8.0ns (125Mhz max freq)
284 * CS0 Geometry : 13 rows, 10 columns, 2 bankbits
285 * CS1 Geometry : 13 rows, 10 columns, 2 bankbits
287 * 64khz refresh, CAS Latency 2.5
288 * Timing (ns): tCK=7.50 tRAS=45 tRP=20.0 tRRD=15.0 tRCD=20.0 tRFC=auto tRC=auto
290 * Clock Config: Default
294 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, NOCSINTLV, CFG_DRAM_ECC, 0)
295 DRAM_CHAN_CLKCFG(0x0F, 0x08, 0x08, 0x0F, 0x0F, 0x00)
297 DRAM_CS_GEOM(MC_CS0, 13, 10, 2)
298 DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0, 45, DRT4(20,0) ,DRT4(15,0), DRT4(20,0), 0, 0)
300 DRAM_CS_GEOM(MC_CS1, 13, 10, 2)
301 DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0, 45, DRT4(20,0) ,DRT4(15,0), DRT4(20,0), 0, 0)
309 * C3F: SGRAMs and FCRAMs
311 * This board has soldered-down memory.
314 DRAM_GLOBALS(MC_NOPORTINTLV) /* interleave not supported */
317 * 16MB on MC 0 (SGRAM)
318 * Micron MT46V2M32LG-65
320 * Minimum tMEMCLK: 8.0ns (125Mhz max freq)
322 * CS0 Geometry: 11 rows, 8 columns, 2 bankbits
324 * 128khz refresh, CAS Latency 3.0
325 * Timing (ns): tCK=7.50 tRAS=40 tRP=19.50 tRRD=13.0 tRCD=19.50 tRFC=66 tRC=59
327 * Clock Config: Addrskew 0x0F, DQOskew 0x08, DQIskew 0x08, addrdrive 0x07, datadrive 0x07, clockdrive 0x00
330 DRAM_CHAN_CFG(MC_CHAN0, DRT10(8,0), SGRAM, CASCHECK, BLKSIZE32, NOCSINTLV, CFG_DRAM_ECC, 0)
331 DRAM_CHAN_CLKCFG(0x0F, 0x08, 0x08, 0x07, 0x07, 0x00)
333 DRAM_CS_GEOM(MC_CS0, 11, 8, 2)
334 DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_128khz, JEDEC_CASLAT_30, 0, 40, DRT4(19,50) ,DRT4(13,0), DRT4(19,50), 66 , 59)
337 * 256MB on MC 1 (FCRAM)
338 * Toshiba TC59LM806BFT-22
340 * Minimum tMEMCLK: 8.0ns (125Mhz max freq)
342 * CS0 Geometry : 15 rows, 8 columns, 2 bankbits
344 * 128khz refresh, CAS Latency 3.0
345 * Timing (ns): tCK=6.50 tRAS=26 tRP=6.50 tRRD=13.0 tRCD=6.50 tRFC=97 tRC=auto
347 * Clock Config: Addrskew 0x08, DQOskew 0x08, DQIskew 0x08, addrdrive 0x07, datadrive 0x07, clockdrive 0x07
350 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), FCRAM, CLOSED, BLKSIZE32, NOCSINTLV, CFG_DRAM_ECC, 0)
351 DRAM_CHAN_CLKCFG(0x08,0x08,0x08,0x07,0x07,0x07)
353 DRAM_CS_GEOM(MC_CS0, 15, 8, 2)
354 DRAM_CS_TIMING(DRT10(6,5), JEDEC_RFSH_128khz, JEDEC_CASLAT_30, 0, 26, DRT4(6,50) ,DRT4(13,0), DRT4(6,50), 97 , 0)
358 #error "Board type not defined"
366 /* *********************************************************************
369 * Transmit a single character via UART A
372 * a0 - character to transmit (low-order 8 bits)
379 ********************************************************************* */
381 #ifdef _SERIAL_PORT_LEDS_
382 LEAF(board_uarta_txchar)
384 # Wait until there is space in the transmit buffer
386 1: li t0,PHYS_TO_K1(A_DUART_STATUS_A)
387 ld t1,(t0) # Get status bits
388 and t1,M_DUART_TX_RDY # test for ready
389 beq t1,0,1b # keep going till ready
391 # Okay, now send the character.
393 li t0,PHYS_TO_K1(A_DUART_TX_HOLD_A)
400 END(board_uarta_txchar)
403 /* *********************************************************************
406 * Set LEDs for boot-time progress indication. Not used if
407 * the board does not have progress LEDs. This routine
408 * must not call any other routines, since it may be invoked
409 * either from KSEG0 or KSEG1 and it may be invoked
410 * whether or not the icache is operational.
413 * a0 - LED value (8 bits per character, 4 characters)
420 ********************************************************************* */
425 #ifdef _SERIAL_PORT_LEDS_
430 bal board_uarta_txchar
434 bal board_uarta_txchar
436 bal board_uarta_txchar
438 bal board_uarta_txchar
440 bal board_uarta_txchar
443 bal board_uarta_txchar