release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm97115/include/dev_bcm4413.h

   1 /*
   2     EXTERNAL SOURCE RELEASE on 08/16/2001 2.34.0.2 - Subject to change without notice.
   3
   4 */
   5 /*
   6     Copyright 2001, Broadcom Corporation
   7     All Rights Reserved.
   8
   9     This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
  10     the contents of this file may not be disclosed to third parties, copied or
  11     duplicated in any form, in whole or in part, without the prior written
  12     permission of Broadcom Corporation.
  13
  14
  15 */
  16 /*
  17  * Hardware-specific definitions for
  18  * "Lassen" BCM44XX PCI 10/100 Mbit/s Ethernet chip.
  19  *
  20  * This is an "Epigram" PCI/DMA engine bolted onto the ISB
  21  * atop EMAC and EPHY cores from the BCM3352.
  22  *
  23  * Copyright(c) 2000 Broadcom Corporation
  24  *
  25  * $Id: dev_bcm4413.h 241205 2011-02-17 21:57:41Z $
  26  */
  27
  28 #ifndef _BCMENET_H
  29 #define _BCMENET_H
  30
  31 #include "lib_types.h"
  32
  33 #define BCMENET_NFILTERS        64              /* # ethernet address filter entries */
  34 #define BCMENET_MCHASHBASE      0x200           /* multicast hash filter base address */
  35 #define BCMENET_MCHASHSIZE      256             /* multicast hash filter size in bytes */
  36 #define BCMENET_MAX_DMA         4096            /* chip has 12 bits of DMA addressing */
  37
  38 /* power management wakeup pattern constants */
  39 #define BCMENET_NPMP            4               /* chip supports 4 wakeup patterns */
  40 #define BCMENET_PMPBASE         0x400           /* wakeup pattern base address */
  41 #define BCMENET_PMPSIZE         0x80            /* 128bytes each pattern */
  42 #define BCMENET_PMMBASE         0x600           /* wakeup mask base address */
  43 #define BCMENET_PMMSIZE         0x10            /* 128bits each mask */
  44
  45 /* cpp contortions to concatenate w/arg prescan */
  46 #define _PADLINE(line)  pad ## line
  47 #define _XSTR(line)     _PADLINE(line)
  48 #define PAD             _XSTR(__LINE__)
  49
  50 /*
  51  * EMAC MIB Registers
  52  */
  53 typedef volatile struct {
  54         uint32_t tx_good_octets;
  55         uint32_t tx_good_pkts;
  56         uint32_t tx_octets;
  57         uint32_t tx_pkts;
  58         uint32_t tx_broadcast_pkts;
  59         uint32_t tx_multicast_pkts;
  60         uint32_t tx_len_64;
  61         uint32_t tx_len_65_to_127;
  62         uint32_t tx_len_128_to_255;
  63         uint32_t tx_len_256_to_511;
  64         uint32_t tx_len_512_to_1023;
  65         uint32_t tx_len_1024_to_max;
  66         uint32_t tx_jabber_pkts;
  67         uint32_t tx_oversize_pkts;
  68         uint32_t tx_fragment_pkts;
  69         uint32_t tx_underruns;
  70         uint32_t tx_total_cols;
  71         uint32_t tx_single_cols;
  72         uint32_t tx_multiple_cols;
  73         uint32_t tx_excessive_cols;
  74         uint32_t tx_late_cols;
  75         uint32_t tx_defered;
  76         uint32_t tx_carrier_lost;
  77         uint32_t tx_pause_pkts;
  78         uint32_t PAD[8];
  79
  80         uint32_t rx_good_octets;
  81         uint32_t rx_good_pkts;
  82         uint32_t rx_octets;
  83         uint32_t rx_pkts;
  84         uint32_t rx_broadcast_pkts;
  85         uint32_t rx_multicast_pkts;
  86         uint32_t rx_len_64;
  87         uint32_t rx_len_65_to_127;
  88         uint32_t rx_len_128_to_255;
  89         uint32_t rx_len_256_to_511;
  90         uint32_t rx_len_512_to_1023;
  91         uint32_t rx_len_1024_to_max;
  92         uint32_t rx_jabber_pkts;
  93         uint32_t rx_oversize_pkts;
  94         uint32_t rx_fragment_pkts;
  95         uint32_t rx_missed_pkts;
  96         uint32_t rx_crc_align_errs;
  97         uint32_t rx_undersize;
  98         uint32_t rx_crc_errs;
  99         uint32_t rx_align_errs;
 100         uint32_t rx_symbol_errs;
 101         uint32_t rx_pause_pkts;
 102         uint32_t rx_nonpause_pkts;
 103 } bcmenetmib_t;
 104
 105 /*
 106  * Host Interface Registers
 107  */
 108 typedef volatile struct _bcmenetregs {
 109         /* Device and Power Control */
 110         uint32_t        devcontrol;
 111         uint32_t        devstatus;
 112         //uint32_t      PAD[2];
 113         uint32_t  compatcontrol;
 114         uint32_t  biststatus;
 115         uint32_t        wakeuplength;
 116         uint32_t        PAD[3];
 117
 118         /* Interrupt Control */
 119         uint32_t        intstatus;
 120         uint32_t        intmask;
 121         uint32_t        gptimer;
 122         uint32_t        PAD[23];
 123
 124         /* Ethernet MAC Address Filtering Control */
 125         uint32_t        enetaddrlower;
 126         uint32_t        enetaddrupper;
 127         uint32_t        enetftaddr;
 128         uint32_t        enetftdata;
 129         uint32_t        PAD[4];
 130
 131         /* Ethernet MAC Control */
 132         uint32_t        emaccontrol;
 133         uint32_t        emacflowcontrol;
 134
 135         /* GPIO Interface */
 136         uint32_t        gpiooutput;
 137         uint32_t        gpioouten;
 138         uint32_t        gpioinput;
 139         uint32_t        PAD;
 140
 141         /* Direct FIFO Interface */
 142         uint16_t        xmtfifocontrol;
 143         uint16_t        xmtfifodata;
 144         uint16_t        rcvfifocontrol;
 145         uint16_t        rcvfifodata;
 146         uint32_t        PAD[2];
 147
 148         /* CardBus Function Registers */
 149         uint32_t        funcevnt;
 150         uint32_t        funcevntmask;
 151         uint32_t        funcstate;
 152         uint32_t        funcforce;
 153
 154         uint32_t        PAD[8];
 155
 156         /* DMA Lazy Interrupt Control */
 157         uint32_t        intrecvlazy;
 158         uint32_t        PAD[31];
 159
 160         /* Shadow PCI config */
 161         uint16_t        pcicfg[64];
 162
 163         /* Transmit DMA engine */
 164         uint32_t        xmtcontrol;
 165         uint32_t        xmtaddr;
 166         uint32_t        xmtptr;
 167         uint32_t        xmtstatus;
 168
 169         /* Receive Dma engine */
 170         uint32_t        rcvcontrol;
 171         uint32_t        rcvaddr;
 172         uint32_t        rcvptr;
 173         uint32_t        rcvstatus;
 174         uint32_t        PAD[120];
 175
 176         /* EMAC Registers */
 177         uint32_t rxcontrol;
 178         uint32_t rxmaxlength;
 179         uint32_t txmaxlength;
 180         uint32_t PAD;
 181         uint32_t mdiocontrol;
 182         uint32_t mdiodata;
 183         uint32_t emacintmask;
 184         uint32_t emacintstatus;
 185         uint32_t camdatalo;
 186         uint32_t camdatahi;
 187         uint32_t camcontrol;
 188         uint32_t enetcontrol;
 189         uint32_t txcontrol;
 190         uint32_t txwatermark;
 191         uint32_t mibcontrol;
 192         uint32_t PAD[49];
 193
 194         /* EMAC MIB statistic counters */
 195         bcmenetmib_t    mib;
 196 } bcmenetregs_t;
 197
 198 /* device control */
 199 #define DC_RS           ((uint32_t)1 << 0)      /* emac reset */
 200 #define DC_XE           ((uint32_t)1 << 5)      /* transmit enable */
 201 #define DC_RE           ((uint32_t)1 << 6)      /* receive enable */
 202 #define DC_PM           ((uint32_t)1 << 7)      /* pattern filtering enable */
 203 #define DC_MD           ((uint32_t)1 << 8)      /* emac clock disable */
 204 #define DC_BS           ((uint32_t)1 << 11)     /* msi byte swap */
 205 #define DC_PD           ((uint32_t)1 << 14)     /* ephy clock disable */
 206 #define DC_PR           ((uint32_t)1 << 15)     /* ephy reset */
 207
 208 /* device status */
 209 #define DS_RI_MASK      0x1f                    /* revision id */
 210 #define DS_MM_MASK      0xe0                    /* MSI mode */
 211 #define DS_MM_SHIFT     5
 212 #define DS_MM           ((uint32_t)1 << 8)      /* msi mode (otherwise pci mode) */
 213 #define DS_SP           ((uint32_t)1 << 9)      /* serial prom present */
 214 #define DS_SL           ((uint32_t)1 << 10)     /* low-order 512 bits of sprom locked */
 215 #define DS_SS_MASK      0x1800                  /* sprom size */
 216 #define DS_SS_SHIFT     11
 217 #define DS_SS_1K        0x0800                  /*  1 kbit */
 218 #define DS_SS_4K        0x1000                  /*  4 kbit */
 219 #define DS_SS_16K       0x1800                  /* 16 kbit */
 220 #define DS_RR           ((uint32_t)1 << 15)     /* register read ready (4412) */
 221 #define DS_BO_MASK      0xffff0000              /* bond option id */
 222 #define DS_BO_SHIFT     16
 223
 224 #define DS_MM_PPC       0x0000                  /* 4412 msi subtype==PPC */
 225 #define DS_MM_ARM7T     ((uint32_t)1 << DS_MM_SHIFT)/* 4412 msi subtype == ARM7T */
 226 #define DS_MM_M68K      ((uint32_t)2 << DS_MM_SHIFT)/* 4412 msi subtype == M68K */
 227 #define DS_MM_GENASYNC  ((uint32_t)3 << DS_MM_SHIFT)/* 4412 msi subtype == Generic Async */
 228 #define DS_MM_GENSYNC   ((uint32_t)4 << DS_MM_SHIFT)/* 4412 msi subtype == Generic Sync */
 229 #define DS_MM_SH3       ((uint32_t)5 << DS_MM_SHIFT)/* 4412 msi subtype == Generic Sync */
 230
 231 /* wakeup length */
 232 #define WL_P0_MASK      0x7f                    /* pattern 0 */
 233 #define WL_D0           ((uint32_t)1 << 7)
 234 #define WL_P1_MASK      0x7f00                  /* pattern 1 */
 235 #define WL_P1_SHIFT     8
 236 #define WL_D1           ((uint32_t)1 << 15)
 237 #define WL_P2_MASK      0x7f0000                /* pattern 2 */
 238 #define WL_P2_SHIFT     16
 239 #define WL_D2           ((uint32_t)1 << 23)
 240 #define WL_P3_MASK      0x7f000000              /* pattern 3 */
 241 #define WL_P3_SHIFT     24
 242 #define WL_D3           ((uint32_t)1 << 31)
 243
 244 /* intstatus and intmask */
 245 #define I_TO            ((uint32_t)1 << 7)      /* general purpose timeout */
 246 #define I_PC            ((uint32_t)1 << 10)     /* pci descriptor error */
 247 #define I_PD            ((uint32_t)1 << 11)     /* pci data error */
 248 #define I_DE            ((uint32_t)1 << 12)     /* descriptor protocol error */
 249 #define I_RU            ((uint32_t)1 << 13)     /* receive descriptor underflow */
 250 #define I_RO            ((uint32_t)1 << 14)     /* receive fifo overflow */
 251 #define I_XU            ((uint32_t)1 << 15)     /* transmit fifo underflow */
 252 #define I_RI            ((uint32_t)1 << 16)     /* receive interrupt */
 253 #define I_XI            ((uint32_t)1 << 24)     /* transmit interrupt */
 254 #define I_EM            ((uint32_t)1 << 26)     /* emac interrupt */
 255
 256 /* emaccontrol */
 257 #define EMC_CG          ((uint32_t)1 << 0)      /* crc32 generation enable */
 258 #define EMC_CK          ((uint32_t)1 << 1)      /* clock source: 0=ephy 1=iline */
 259 #define EMC_PD          ((uint32_t)1 << 2)      /* ephy power down */
 260 #define EMC_PA          ((uint32_t)1 << 3)      /* ephy activity status */
 261 #define EMC_LED_MASK    0xe0                    /* ephy led config */
 262 #define EMC_GPIO_MASK   0xc000                  /* gpio pin config */
 263 #define EMC_GPIO_SHIFT  14
 264
 265 /* emacflowcontrol */
 266 #define EMF_RFH_MASK    0xff                    /* rx fifo hi water mark */
 267 #define EMF_PG          ((uint32_t)1 << 15)     /* enable pause frame generation */
 268
 269 /* gpio output/enable/input */
 270 #define GPIO_MASK       0x7ff                   /* output/enable/input */
 271
 272 /* transmit fifo control */
 273 #define XFC_BV_MASK     0x3                     /* bytes valid */
 274 #define XFC_LO          (1 << 0)                /* low byte valid */
 275 #define XFC_HI          (1 << 1)                /* high byte valid */
 276 #define XFC_BOTH        (XFC_HI | XFC_LO)       /* both bytes valid */
 277 #define XFC_EF          (1 << 2)                /* end of frame */
 278 #define XFC_FR          (1 << 3)                /* frame ready */
 279
 280 /* receive fifo control */
 281 #define RFC_FR          (1 << 0)                /* frame ready */
 282 #define RFC_DR          (1 << 1)                /* data ready */
 283
 284 /* funcevnt, funcevntmask, funcstate, and funcforce */
 285 #define F_RD            ((uint32_t)1 << 1)      /* card function ready */
 286 #define F_GW            ((uint32_t)1 << 4)      /* general wakeup */
 287 #define F_WU            ((uint32_t)1 << 14)     /* wakeup mask */
 288 #define F_IR            ((uint32_t)1 << 15)     /* interrupt request pending */
 289
 290 /* interrupt receive lazy */
 291 #define IRL_TO_MASK     0x00ffffff              /* timeout */
 292 #define IRL_FC_MASK     0xff000000              /* frame count */
 293 #define IRL_FC_SHIFT    24                      /* frame count */
 294
 295 /* transmit channel control */
 296 #define XC_XE           ((uint32_t)1 << 0)      /* transmit enable */
 297 #define XC_SE           ((uint32_t)1 << 1)      /* transmit suspend request */
 298 #define XC_LE           ((uint32_t)1 << 2)      /* dma loopback enable */
 299
 300 /* transmit descriptor table pointer */
 301 #define XP_LD_MASK      0xfff                   /* last valid descriptor */
 302
 303 /* transmit channel status */
 304 #define XS_CD_MASK      0x0fff                  /* current descriptor pointer */
 305 #define XS_XS_MASK      0xf000                  /* transmit state */
 306 #define XS_XS_SHIFT     12
 307 #define XS_XS_DISABLED  0x0000                  /* disabled */
 308 #define XS_XS_ACTIVE    0x1000                  /* active */
 309 #define XS_XS_IDLE      0x2000                  /* idle wait */
 310 #define XS_XS_STOPPED   0x3000                  /* stopped */
 311 #define XS_XS_SUSP      0x4000                  /* suspended */
 312 #define XS_XE_MASK      0xf0000                 /* transmit errors */
 313 #define XS_XE_SHIFT     16
 314 #define XS_XE_NOERR     0x00000                 /* no error */
 315 #define XS_XE_DPE       0x10000                 /* descriptor protocol error */
 316 #define XS_XE_DFU       0x20000                 /* data fifo underrun */
 317 #define XS_XE_PCIBR     0x30000                 /* pci bus error on buffer read */
 318 #define XS_XE_PCIDA     0x40000                 /* pci bus error on descriptor access */
 319
 320 /* receive channel control */
 321 #define RC_RE           ((uint32_t)1 << 0)      /* receive enable */
 322 #define RC_RO_MASK      0x7e                    /* receive frame offset */
 323 #define RC_RO_SHIFT     1
 324 #define RC_FM           ((uint32_t)1 << 8)      /* direct fifo receive mode */
 325
 326 /* receive descriptor table pointer */
 327 #define RP_LD_MASK      0xfff                   /* last valid descriptor */
 328
 329 /* receive channel status */
 330 #define RS_CD_MASK      0x0fff                  /* current descriptor pointer */
 331 #define RS_RS_MASK      0xf000                  /* receive state */
 332 #define RS_RS_SHIFT     12
 333 #define RS_RS_DISABLED  0x0000                  /* disabled */
 334 #define RS_RS_ACTIVE    0x1000                  /* active */
 335 #define RS_RS_IDLE      0x2000                  /* idle wait */
 336 #define RS_RS_STOPPED   0x3000                  /* reserved */
 337 #define RS_RE_MASK      0xf0000                 /* receive errors */
 338 #define RS_RE_SHIFT     16
 339 #define RS_RE_NOERR     0x00000                 /* no error */
 340 #define RS_RE_DPE       0x10000                 /* descriptor protocol error */
 341 #define RS_RE_DFO       0x20000                 /* data fifo overflow */
 342 #define RS_RE_PCIBW     0x30000                 /* pci bus error on buffer write */
 343 #define RS_RE_PCIDA     0x40000                 /* pci bus error on descriptor access */
 344
 345 /* emac receive control */
 346 #define ERC_DB          ((uint32_t)1 << 0)      /* disable broadcast */
 347 #define ERC_AM          ((uint32_t)1 << 1)      /* accept all multicast */
 348 #define ERC_RDT         ((uint32_t)1 << 2)      /* receive disable while transmitting */
 349 #define ERC_PE          ((uint32_t)1 << 3)      /* promiscuous enable */
 350 #define ERC_LE          ((uint32_t)1 << 4)      /* loopback enable */
 351 #define ERC_FE          ((uint32_t)1 << 5)      /* enable flow control */
 352 #define ERC_UF          ((uint32_t)1 << 6)      /* accept unicast flow control frame */
 353
 354 /* emac mdio control */
 355 #define MC_MF_MASK      0x7f                    /* mdc frequency */
 356 #define MC_PE           ((uint32_t)1 << 7)      /* mii preamble enable */
 357
 358 /* emac mdio data */
 359 #define MD_DATA_MASK    0xffff                  /* r/w data */
 360 #define MD_TA_MASK      0x30000                 /* turnaround value */
 361 #define MD_TA_SHIFT     16
 362 #define MD_TA_VALID     (2 << MD_TA_SHIFT)      /* valid ta */
 363 #define MD_RA_MASK      0x7c0000                /* register address */
 364 #define MD_RA_SHIFT     18
 365 #define MD_PMD_MASK     0xf800000               /* physical media device */
 366 #define MD_PMD_SHIFT    23
 367 #define MD_OP_MASK      0x30000000              /* opcode */
 368 #define MD_OP_SHIFT     28
 369 #define MD_OP_WRITE     (1 << MD_OP_SHIFT)      /* write op */
 370 #define MD_OP_READ      (2 << MD_OP_SHIFT)      /* read op */
 371 #define MD_SB_MASK      0xc0000000              /* start bits */
 372 #define MD_SB_SHIFT     30
 373 #define MD_SB_START     (0x1 << MD_SB_SHIFT)    /* start of frame */
 374
 375 /* emac intstatus and intmask */
 376 #define EI_MII          ((uint32_t)1 << 0)      /* mii mdio interrupt */
 377 #define EI_MIB          ((uint32_t)1 << 1)      /* mib interrupt */
 378 #define EI_FLOW         ((uint32_t)1 << 2)      /* flow control interrupt */
 379
 380 /* emac cam data high */
 381 #define CD_V            ((uint32_t)1 << 16)     /* valid bit */
 382
 383 /* emac cam control */
 384 #define CC_CE           ((uint32_t)1 << 0)      /* cam enable */
 385 #define CC_MS           ((uint32_t)1 << 1)      /* mask select */
 386 #define CC_RD           ((uint32_t)1 << 2)      /* read */
 387 #define CC_WR           ((uint32_t)1 << 3)      /* write */
 388 #define CC_INDEX_MASK   0x3f0000                /* index */
 389 #define CC_INDEX_SHIFT  16
 390 #define CC_CB           ((uint32_t)1 << 31)     /* cam busy */
 391
 392 /* emac ethernet control */
 393 #define EC_EE           ((uint32_t)1 << 0)      /* emac enable */
 394 #define EC_ED           ((uint32_t)1 << 1)      /* emac disable */
 395 #define EC_ES           ((uint32_t)1 << 2)      /* emac soft reset */
 396 #define EC_EP           ((uint32_t)1 << 3)      /* external phy select */
 397
 398 /* emac transmit control */
 399 #define EXC_FD          ((uint32_t)1 << 0)      /* full duplex */
 400 #define EXC_FM          ((uint32_t)1 << 1)      /* flowmode */
 401 #define EXC_SB          ((uint32_t)1 << 2)      /* single backoff enable */
 402 #define EXC_SS          ((uint32_t)1 << 3)      /* small slottime */
 403
 404 /* emac mib control */
 405 #define EMC_RZ          ((uint32_t)1 << 0)      /* autoclear on read */
 406
 407 /*
 408  * Transmit/Receive Ring Descriptor
 409  */
 410 typedef volatile struct {
 411         uint32_t        ctrl;           /* misc control bits & bufcount */
 412         uint32_t        addr;           /* data buffer address */
 413 } bcmenetdd_t;
 414
 415 #define CTRL_BC_MASK    0x1fff                  /* buffer byte count */
 416 #define CTRL_EOT        ((uint32_t)1 << 28)     /* end of descriptor table */
 417 #define CTRL_IOC        ((uint32_t)1 << 29)     /* interrupt on completion */
 418 #define CTRL_EOF        ((uint32_t)1 << 30)     /* end of frame */
 419 #define CTRL_SOF        ((uint32_t)1 << 31)     /* start of frame */
 420
 421 /*
 422  * Enet receive frame buffer header consists of
 423  * 16bits of frame length, followed by
 424  * 16bits of EMAC rx descriptor info, followed by 24bytes of
 425  * undefined data (where the iline rxhdr would be),
 426  * followed by the start of ethernet frame (ether_header).
 427  */
 428 typedef volatile struct {
 429         uint16_t        len;
 430         uint16_t        flags;
 431         uint8_t pad[24];
 432 } bcmenetrxhdr_t;
 433
 434 #define RXHDR_LEN       28
 435
 436 #define RXF_L           ((uint16_t)1 << 11)     /* last buffer in a frame */
 437 #define RXF_MISS        ((uint16_t)1 << 7)      /* received due to promisc mode */
 438 #define RXF_BRDCAST     ((uint16_t)1 << 6)      /* dest is broadcast address */
 439 #define RXF_MULT        ((uint16_t)1 << 5)      /* dest is multicast address */
 440 #define RXF_LG          ((uint16_t)1 << 4)      /* frame length > rxmaxlength */
 441 #define RXF_NO          ((uint16_t)1 << 3)      /* odd number of nibbles */
 442 #define RXF_RXER        ((uint16_t)1 << 2)      /* receive symbol error */
 443 #define RXF_CRC         ((uint16_t)1 << 1)      /* crc error */
 444 #define RXF_OV          ((uint16_t)1 << 0)      /* fifo overflow */
 445
 446
 447 #define barrier() __asm__ __volatile__("": : :"memory")
 448
 449 #define R_REG(r)        ((sizeof *(r) == sizeof (uint32_t))? \
 450         ((uint32_t)( *(&((uint16_t*)(r))[0]) | (*(&((uint16_t*)(r))[1]) << 16))) \
 451         : *(r))
 452 #define W_REG(r, v)     do { ((sizeof *(r) == sizeof (uint32_t))? \
 453         (*(&((uint16_t*)r)[0]) = ((v) & 0xffff), *(&((uint16_t*)r)[1]) = (((v) >> 16) & 0xffff)) \
 454         : (*(r) = (v))); barrier(); } while( 0 )
 455
 456
 457 #define AND_REG(r, v)   W_REG((r), (R_REG((r)) & (v)))
 458 #define OR_REG(r, v)    W_REG((r), (R_REG((r)) | (v)))
 459
 460
 461 #endif  /* _BCMENET_H */