release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm96345/include/6345_common.h

   1 /***********************************************************************/
   2 /*                                                                     */
   3 /*   MODULE: 6345_common.h                                             */
   4 /*   DATE:    96/12/19                                                 */
   5 /*   PURPOSE: Define addresses of major hardware components of         */
   6 /*            BCM6345                                                  */
   7 /*                                                                     */
   8 /*---------------------------------------------------------------------*/
   9 /*                                                                     */
  10 /*           Copyright 1991 - 1996, Integrated Systems, Inc.           */
  11 /*                      ALL RIGHTS RESERVED                            */
  12 /*                                                                     */
  13 /*   Permission is hereby granted to licensees of Integrated Systems,  */
  14 /*   Inc. products to use or abstract this computer program for the    */
  15 /*   sole purpose of implementing a product based on Integrated        */
  16 /*   Systems, Inc. products.   No other rights to reproduce, use,      */
  17 /*   or disseminate this computer program, whether in part or in       */
  18 /*   whole, are granted.                                               */
  19 /*                                                                     */
  20 /*   Integrated Systems, Inc. makes no representation or warranties    */
  21 /*   with respect to the performance of this computer program, and     */
  22 /*   specifically disclaims any responsibility for any damages,        */
  23 /*   special or consequential, connected with the use of this program. */
  24 /*                                                                     */
  25 /*---------------------------------------------------------------------*/
  26 /*                                                                     */
  27 /*                                                                     */
  28 /*                                                                     */
  29 /***********************************************************************/
  30 #ifndef __BCM6345_MAP_COMMON_H
  31 #define __BCM6345_MAP_COMMON_H
  32
  33 #if __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 /* matches isb_decoder.v */
  38 #define INTC_BASE     0xfffe0000    /* interrupts controller registers */
  39 #define BB_BASE       0xfffe0100    /* bus bridge registers */
  40 #define TIMR_BASE     0xfffe0200    /* timer registers */
  41 #define UART_BASE     0xfffe0300    /* uart registers */
  42 #define GPIO_BASE     0xfffe0400    /* gpio registers */
  43 #define EMAC_BASE     0xfffe1800    /* EMAC control registers */
  44 #define EBIC_BASE     0xfffe2000    /* EBI control registers */
  45 #define USB_BASE      0xfffe2100    /* USB controll registers */
  46 #define SDRAM_BASE    0xfffe2300    /* SDRAM control registers */
  47 #define DMA_BASE      0xfffe2800    /* DMA control registers */
  48
  49 /* DMA channel assignments */
  50 #define EMAC_RX_CHAN            1
  51 #define EMAC_TX_CHAN            2
  52 #define EBI_RX_CHAN             5
  53 #define EBI_TX_CHAN             6
  54 #define RESERVED_RX_CHAN        9
  55 #define RESERVED_TX_CHAN        10
  56 #define USB_BULK_RX_CHAN        13
  57 #define USB_BULK_TX_CHAN        14
  58 #define USB_ISO_RX_CHAN         15
  59 #define USB_ISO_TX_CHAN         16
  60 #define USB_CNTL_RX_CHAN        17
  61 #define USB_CNTL_TX_CHAN        18
  62
  63 /*
  64 #-----------------------------------------------------------------------*
  65 #                                                                       *
  66 #************************************************************************
  67 */
  68 #define SDR_INIT_CTL        0x00
  69     /* Control Bits */
  70 #define SDR_9BIT_COL        (1<<11)
  71 #define SDR_32BIT           (1<<10)
  72 #define SDR_PWR_DN          (1<<9)
  73 #define SDR_SELF_REF        (1<<8)
  74 #define SDR_SOFT_RST        (1<<7)
  75 #define SDR_64x32           (3<<4)
  76 #define SDR_128MEG          (2<<4)
  77 #define SDR_64MEG           (1<<4)
  78 #define SDR_16MEG           (0<<4)
  79 #define SDR_ENABLE          (1<<3)
  80 #define SDR_MRS_CMD         (1<<2)
  81 #define SDR_PRE_CMD         (1<<1)
  82 #define SDR_CBR_CMD         (1<<0)
  83
  84 #define SDR_CFG_REG         0x04
  85     /* Control Bits */
  86 #define SDR_FULL_PG         0x00
  87 #define SDR_BURST8          0x01
  88 #define SDR_BURST4          0x02
  89 #define SDR_BURST2          0x03
  90 #define SDR_FAST_MEM        (1<<2)
  91 #define SDR_SLOW_MEM        0x00
  92
  93 #define SDR_REF_CTL         0x08
  94     /* Control Bits */
  95 #define SDR_REF_EN          (1<<15)
  96
  97 #define SDR_MEM_BASE        0x0c
  98     /*  Control Bits */
  99 #define DRAM2MBSPC          0x00000000
 100 #define DRAM8MBSPC          0x00000001
 101 #define DRAM16MBSPC         0x00000002
 102 #define DRAM32MBSPC         0x00000003
 103 #define DRAM64MBSPC         0x00000004
 104
 105 #define DRAM2MEG            0x00000000  /*  See SDRAM config */
 106 #define DRAM8MEG            0x00000001  /*  See SDRAM config */
 107 #define DRAM16MEG           0x00000002  /*  See SDRAM config */
 108 #define DRAM32MEG           0x00000003  /*  See SDRAM config */
 109 #define DRAM64MEG           0x00000004  /*  See SDRAM config */
 110
 111 /*
 112 #-----------------------------------------------------------------------*
 113 #                                                                       *
 114 #************************************************************************
 115 */
 116 #define CS0BASE         0x00
 117 #define CS0CNTL         0x04
 118 #define CS1BASE         0x08
 119 #define CS1CNTL         0x0c
 120 #define CS2BASE         0x10
 121 #define CS2CNTL         0x14
 122 #define CS3BASE         0x18
 123 #define CS3CNTL         0x1c
 124 #define CS4BASE         0x20
 125 #define CS4CNTL         0x24
 126 #define CS5BASE         0x28
 127 #define CS5CNTL         0x2c
 128 #define CS6BASE         0x30
 129 #define CS6CNTL         0x34
 130 #define CS7BASE         0x38
 131 #define CS7CNTL         0x3c
 132 #define EBICONFIG       0x40
 133
 134 /*
 135 # CSxBASE settings
 136 #   Size in low 4 bits
 137 #   Base Address for match in upper 24 bits
 138 */
 139 #define EBI_SIZE_8K         0
 140 #define EBI_SIZE_16K        1
 141 #define EBI_SIZE_32K        2
 142 #define EBI_SIZE_64K        3
 143 #define EBI_SIZE_128K       4
 144 #define EBI_SIZE_256K       5
 145 #define EBI_SIZE_512K       6
 146 #define EBI_SIZE_1M         7
 147 #define EBI_SIZE_2M         8
 148 #define EBI_SIZE_4M         9
 149 #define EBI_SIZE_8M         10
 150 #define EBI_SIZE_16M        11
 151 #define EBI_SIZE_32M        12
 152 #define EBI_SIZE_64M        13
 153 #define EBI_SIZE_128M       14
 154 #define EBI_SIZE_256M       15
 155
 156 /* CSxCNTL settings */
 157 #define EBI_ENABLE          0x00000001  /* .. enable this range */
 158 #define EBI_WAIT_STATES     0x0000000e  /* .. mask for wait states */
 159 #define ZEROWT              0x00000000  /* ..  0 WS */
 160 #define ONEWT               0x00000002  /* ..  1 WS */
 161 #define TWOWT               0x00000004  /* ..  2 WS */
 162 #define THREEWT             0x00000006  /* ..  3 WS */
 163 #define FOURWT              0x00000008  /* ..  4 WS */
 164 #define FIVEWT              0x0000000a  /* ..  5 WS */
 165 #define SIXWT               0x0000000c  /* ..  6 WS */
 166 #define SEVENWT             0x0000000e  /* ..  7 WS */
 167 #define EBI_WORD_WIDE       0x00000010  /* .. 16-bit peripheral, else 8 */
 168 #define EBI_POLARITY        0x00000040  /* .. set to invert chip select polarity */
 169 #define EBI_TS_TA_MODE      0x00000080  /* .. use TS/TA mode */
 170 #define EBI_TS_SEL          0x00000100  /* .. drive tsize, not bs_b */
 171 #define EBI_FIFO            0x00000200  /* .. enable fifo */
 172 #define EBI_RE              0x00000400  /* .. Reverse Endian */
 173
 174 /* EBICONFIG settings */
 175 #define EBI_MASTER_ENABLE   0x80000000  /* allow external masters */
 176 #define EBI_EXT_MAST_PRIO   0x40000000  /* maximize ext master priority */
 177 #define EBI_CTRL_ENABLE     0x20000000
 178 #define EBI_TA_ENABLE       0x10000000
 179
 180 #define BRGEN            0x80   /* Control register bit defs */
 181 #define TXEN             0x40
 182 #define RXEN             0x20
 183 #define LOOPBK           0x10
 184 #define TXPARITYEN       0x08
 185 #define TXPARITYEVEN     0x04
 186 #define RXPARITYEN       0x02
 187 #define RXPARITYEVEN     0x01
 188 #define XMITBREAK        0x40
 189 #define BITS5SYM         0x00
 190 #define BITS6SYM         0x10
 191 #define BITS7SYM         0x20
 192 #define BITS8SYM         0x30
 193 #define BAUD115200       0x0a
 194 #define ONESTOP          0x07
 195 #define TWOSTOP          0x0f
 196 #define TX4              0x40
 197 #define RX4              0x04
 198 #define RSTTXFIFOS       0x80
 199 #define RSTRXFIFOS       0x40
 200 #define DELTAIP          0x0001
 201 #define TXUNDERR         0x0002
 202 #define TXOVFERR         0x0004
 203 #define TXFIFOTHOLD      0x0008
 204 #define TXREADLATCH      0x0010
 205 #define TXFIFOEMT        0x0020
 206 #define RXUNDERR         0x0040
 207 #define RXOVFERR         0x0080
 208 #define RXTIMEOUT        0x0100
 209 #define RXFIFOFULL       0x0200
 210 #define RXFIFOTHOLD      0x0400
 211 #define RXFIFONE         0x0800
 212 #define RXFRAMERR        0x1000
 213 #define RXPARERR         0x2000
 214 #define RXBRK            0x4000
 215
 216 #define RXIRQS           0x7fc0
 217 #define TXIRQS           0x003e
 218
 219 #define CPU_CLK_EN       0x0001
 220 #define UART_CLK_EN      0x0008
 221
 222 #define BLKEN            06
 223
 224 #define FMSEL_MASK      0xf0000000      // 31:28
 225 #define FMSEL_SHFT      28
 226 #define FM_HI_GEAR      0x08000000      // 27
 227 #define FMCLKSEL        0x04000000      // 26
 228 #define FMDIV_MASK      0x03000000      // 25:24
 229 #define FMDIV_SHFT      24
 230 #define FBDIV_MASK      0x00f00000      // 23:20
 231 #define FBDIV_SHFT      20
 232 #define FB_SEL          0x00010000      // 16
 233 #define FU2SEL_MASK     0x0000f000      // 15:12
 234 #define FU2SEL_SHFT     12
 235 #define FU1SEL_MASK     0x00000f00      // 11:8
 236 #define FU1SEL_SHFT     8
 237 #define FU1PRS_MASK     0x000000e0      // 7:5
 238 #define FU1PRS_SHFT     5
 239 #define FU1POS_MASK     0x00000018      // 4:3
 240 #define FU1POS_SHFT     3
 241 #define SOFT_RESET      0x00000001
 242
 243 #define FMSEL            0x08
 244
 245 #define UART0CONTROL     0x01
 246 #define UART0CONFIG      0x02
 247 #define UART0RXTIMEOUT   0x03
 248 #define UART0BAUD        0x04
 249 #define UART0FIFOCFG     0x0a
 250 #define UART0INTMASK     0x10
 251 #define UART0INTSTAT     0x12
 252 #define UART0DATA        0x17
 253
 254 #define GPIOTBUSSEL      0x03
 255 #define GPIODIR          0x06
 256 #define GPIOLED          0x09
 257 #define GPIOIO           0x0a
 258 #define GPIOUARTCTL      0x0c
 259
 260 /*Defines below show which bit enables which UART signals */
 261 #define RI1_EN          0x0001
 262 #define CTS1_EN         0x0002
 263 #define DCD1_EN         0x0004
 264 #define DSR1_EN         0x0008
 265 #define DTR1_EN         0x0010
 266 #define RTS1_EN         0x0020
 267 #define DO1_EN          0x0040
 268 #define DI1_EN          0x0080
 269 #define RI0_EN          0x0100
 270 #define CTS0_EN         0x0200
 271 #define DCD0_EN         0x0400
 272 #define DSR0_EN         0x0800
 273 #define DTR0_EN         0x1000
 274 #define RTS0_EN         0x2000
 275
 276 #if __cplusplus
 277 }
 278 #endif
 279
 280 #endif