release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm947xx/src/bcm947xx_pci_machdep.c

   1 /* PCI config support for emulated PCI devices (SI cores) only */
   2 /*
   3  * Machine-specific functions for PCI autoconfiguration.
   4  *
   5  * Copyright (c) 2000-2001, Algorithmics Ltd.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the "Free MIPS" License Agreement, a copy of
   9  * which is available at:
  10  *
  11  *  http://www.algor.co.uk/ftp/pub/doc/freemips-license.txt
  12  *
  13  * You may not, however, modify or remove any part of this copyright
  14  * message if this program is redistributed or reused in whole or in
  15  * part.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * "Free MIPS" License for more details.
  21  */
  22
  23 #include "cfe_pci.h"
  24 #include "pcivar.h"
  25 #include "pcireg.h"
  26 #include "pci_internal.h"
  27
  28 #include <typedefs.h>
  29 #include <bcmutils.h>
  30 #include <hndsoc.h>
  31 #include <siutils.h>
  32 #include <hndpci.h>
  33
  34 /* default PCI mem regions in PCI space */
  35 #define PCI_MEM_SPACE_BASE      SI_PCI_DMA
  36 #define PCI_MEM_SPACE_SIZE      SI_PCI_DMA_SZ
  37
  38 const cons_t pci_optnames[] = {
  39     {"verbose",PCI_FLG_VERBOSE},
  40     {NULL,0}
  41 };
  42
  43 static struct pci_bus _pci_bus[1] = {
  44     {
  45         0,              /* minimum grant */
  46         255,            /* maximum latency */
  47         0,              /* devsel time = fast */
  48         0,              /* we don't support fast back-to-back */
  49         0,              /* we don't support prefetch */
  50         0,              /* we don't support 66 MHz */
  51         0,              /* we don't support 64 bits */
  52         4000000,        /* bandwidth: in 0.25us cycles / sec */
  53         1               /* initially one device on bus (i.e. us) */
  54     }
  55 };
  56 static int _pci_nbus = 1;
  57
  58 static si_t *sih = NULL;
  59
  60 extern int _pciverbose;
  61
  62 /* The following functions provide for device-specific setup required
  63    during configuration.  There is nothing host-specific about them,
  64    and it would be better to do the packaging and registration in a
  65    more modular way. */
  66
  67 int
  68 pci_nextbus(int port)
  69 {
  70         return -1;
  71 }
  72
  73 int
  74 pci_maxbus(int port)
  75 {
  76         return _pci_nbus - 1;
  77 }
  78
  79 struct pci_bus *
  80 pci_businfo(int port, int bus)
  81 {
  82         return bus < _pci_nbus ? &_pci_bus[bus] : NULL;
  83 }
  84
  85 pcireg_t
  86 pci_minmemaddr(int port)
  87 {
  88         return PCI_MEM_SPACE_BASE;
  89 }
  90
  91 pcireg_t
  92 pci_maxmemaddr(int port)
  93 {
  94         return pci_minmemaddr(port) + PCI_MEM_SPACE_SIZE;
  95 }
  96
  97 pcireg_t
  98 pci_minioaddr(int port)
  99 {
 100         return 0;
 101 }
 102
 103 pcireg_t
 104 pci_maxioaddr(int port)
 105 {
 106         return 0;
 107 }
 108
 109 /*
 110  * Called to initialise the bridge at the beginning of time
 111  */
 112 int
 113 pci_hwinit(int port, pci_flags_t flags)
 114 {
 115         /* attach to backplane */
 116         if (!(sih = si_kattach(SI_OSH)))
 117                 return -1;
 118
 119         /* emulate PCI devices */
 120         hndpci_init_cores(sih);
 121         return 0;
 122 }
 123
 124
 125 /*
 126  * Called to reinitialise the bridge after we've scanned each PCI device
 127  * and know what is possible.
 128  */
 129 void
 130 pci_hwreinit(int port, pci_flags_t flags)
 131 {
 132 }
 133
 134 void
 135 pci_flush(void)
 136 {
 137 }
 138
 139 pcitag_t
 140 pci_make_tag(int port, int bus, int device, int function)
 141 {
 142         return (bus << 16) | (device << 11) | (function << 8);
 143 }
 144
 145 void
 146 pci_break_tag(pcitag_t tag, int *portp, int *busp, int *devicep, int *functionp)
 147 {
 148         if (portp) *portp = 0;
 149         if (busp) *busp = (tag >> 16) & 0xff;
 150         if (devicep) *devicep = (tag >> 11) & 0x1f;
 151         if (functionp) *functionp = (tag >> 8) & 0x07;
 152 }
 153
 154 int
 155 pci_canscan(pcitag_t tag)
 156 {
 157         int bus;
 158
 159         pci_break_tag(tag, NULL, &bus, NULL, NULL);
 160
 161         return bus == 0;
 162 }
 163
 164 pcireg_t
 165 pci_conf_read(pcitag_t tag, int reg)
 166 {
 167         int bus, device, function;
 168         pcireg_t data;
 169
 170         pci_break_tag(tag, NULL, &bus, &device, &function);
 171
 172         if (hndpci_read_config(sih, (uint32_t)bus, (uint32_t)device,
 173                                (uint32_t)function, (uint32_t)reg,
 174                                (void *)&data, sizeof(pcireg_t)))
 175                 data = 0xffffffff;
 176
 177         return data;
 178 }
 179
 180
 181 void
 182 pci_conf_write(pcitag_t tag, int reg, pcireg_t data)
 183 {
 184         int bus, device, function;
 185
 186         pci_break_tag(tag, NULL, &bus, &device, &function);
 187
 188         hndpci_write_config(sih, (uint32_t)bus, (uint32_t)device,
 189                             (uint32_t)function, (uint32_t)reg,
 190                             (void *)&data, sizeof(pcireg_t));
 191 }
 192
 193 int
 194 pci_conf_write_acked(pcitag_t tag, int reg, pcireg_t data)
 195 {
 196         pci_conf_write(tag, reg, data);
 197         return 1;
 198 }
 199
 200 pcireg_t
 201 pci_conf_read16(pcitag_t tag, int reg)
 202 {
 203         int bus, device, function;
 204         uint16_t data;
 205
 206         pci_break_tag(tag, NULL, &bus, &device, &function);
 207
 208         if (hndpci_read_config(sih, (uint32_t)bus, (uint32_t)device,
 209                                (uint32_t)function, (uint32_t)reg,
 210                                (void *)&data, sizeof(data)))
 211                 data = 0xffff;
 212
 213         return data;
 214 }
 215
 216 void
 217 pci_conf_write16(pcitag_t tag, int reg, pcireg_t data)
 218 {
 219         int bus, device, function;
 220         uint16_t tmp = (uint16_t)data;
 221
 222         pci_break_tag(tag, NULL, &bus, &device, &function);
 223
 224         hndpci_write_config(sih, (uint32_t)bus, (uint32_t)device,
 225                             (uint32_t)function, (uint32_t)reg,
 226                             (void *)&tmp, sizeof(tmp));
 227 }
 228
 229 int
 230 pci_map_io(pcitag_t tag, int reg, pci_endian_t endian, phys_addr_t *pap)
 231 {
 232         return -1;
 233 }
 234
 235 int
 236 pci_map_mem(pcitag_t tag, int reg, pci_endian_t endian, phys_addr_t *pap)
 237 {
 238         pcireg_t address;
 239         phys_addr_t pa;
 240
 241         if (reg == PCI_MAPREG_ROM) {
 242                 /* expansion ROM */
 243                 address = pci_conf_read(tag, reg);
 244                 if (!(address & PCI_MAPREG_ROM)) {
 245                         pci_tagprintf(tag, "pci_map_mem: attempt to map missing rom\n");
 246                         return -1;
 247                 }
 248                 pa = address & PCI_MAPREG_ROM_ADDR_MASK;
 249         }
 250         else {
 251                 if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) {
 252                         if (_pciverbose >= 1)
 253                                 pci_tagprintf(tag, "pci_map_mem: bad request\n");
 254                         return -1;
 255                 }
 256
 257                 address = pci_conf_read(tag, reg);
 258                 if ((address & PCI_MAPREG_TYPE_IO) != 0) {
 259                         if (_pciverbose >= 1)
 260                                 pci_tagprintf(tag, "pci_map_mem: attempt to memory map an I/O region\n");
 261                         return -1;
 262                 }
 263
 264                 switch (address & PCI_MAPREG_MEM_TYPE_MASK) {
 265                 case PCI_MAPREG_MEM_TYPE_32BIT:
 266                 case PCI_MAPREG_MEM_TYPE_32BIT_1M:
 267                         break;
 268                 case PCI_MAPREG_MEM_TYPE_64BIT:
 269                         if (_pciverbose >= 1)
 270                                 pci_tagprintf (tag, "pci_map_mem: attempt to map 64-bit region tag=0x%X @ addr=%X\n", tag, address);
 271                         break;
 272                 default:
 273                         if (_pciverbose >= 1)
 274                                 pci_tagprintf (tag, "pci_map_mem: reserved mapping type\n");
 275                         return -1;
 276                 }
 277                 pa = address & PCI_MAPREG_MEM_ADDR_MASK;
 278         }
 279
 280         if (_pciverbose >= 1)
 281                 pci_tagprintf (tag, "pci_map_mem: addr=0x%X pa=0x%X\n", address, pa);
 282
 283         *pap = pa;
 284         return 0;
 285 }
 286
 287 int
 288 pci_probe_tag(pcitag_t tag)
 289 {
 290         pcireg_t data;
 291
 292         if (!pci_canscan(tag))
 293                 return 0;
 294
 295         data = pci_conf_read(tag,PCI_ID_REG);
 296         if ((data == 0) || (data == 0xffffffff))
 297                 return 0;
 298
 299         return 1;
 300 }
 301
 302 int
 303 pci_map_window(phys_addr_t va,
 304                unsigned int offset, unsigned int len,
 305                int l2ca, int endian)
 306 {
 307         return -1;
 308 }
 309
 310 int
 311 pci_unmap_window(unsigned int offset, unsigned int len)
 312 {
 313         return -1;
 314 }
 315
 316 int
 317 pci_device_preset(pcitag_t tag)
 318 {
 319         return -1;
 320 }
 321
 322 void
 323 pci_device_setup(pcitag_t tag)
 324 {
 325 }
 326
 327 /* Called for each bridge after configuring the secondary bus, to allow
 328    device-specific initialization. */
 329 void
 330 pci_bridge_setup(pcitag_t tag, pci_flags_t flags)
 331 {
 332 }
 333
 334 /* The base shift of a slot or device on the motherboard. */
 335 uint8_t
 336 pci_int_shift_0(pcitag_t tag)
 337 {
 338         return 0;
 339 }
 340
 341 uint8_t
 342 pci_int_map_0(pcitag_t tag)
 343 {
 344         return 0;
 345 }
 346
 347 uint8_t
 348 pci_int_line(uint8_t pci_int)
 349 {
 350         return 0;
 351 }