release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm91125e/include/bcm91125e.h

   1 /*  *********************************************************************
   2     *  SB1125 Board Support Package
   3     *
   4     *  BCM91125E Board definitions      File: bcm91125e.h
   5     *
   6     *  This file contains I/O, chip select, and GPIO assignments
   7     *  for the BCM91125e checkout board.
   8     *
   9     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  10     *           Binh Vo (binh@broadcom.com)
  11     *
  12     *********************************************************************
  13     *
  14     *  Copyright 2000,2001,2002,2003
  15     *  Broadcom Corporation. All rights reserved.
  16     *
  17     *  This software is furnished under license and may be used and
  18     *  copied only in accordance with the following terms and
  19     *  conditions.  Subject to these conditions, you may download,
  20     *  copy, install, use, modify and distribute modified or unmodified
  21     *  copies of this software in source and/or binary form.  No title
  22     *  or ownership is transferred hereby.
  23     *
  24     *  1) Any source code used, modified or distributed must reproduce
  25     *     and retain this copyright notice and list of conditions
  26     *     as they appear in the source file.
  27     *
  28     *  2) No right is granted to use any trade name, trademark, or
  29     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  30     *     name may not be used to endorse or promote products derived
  31     *     from this software without the prior written permission of
  32     *     Broadcom Corporation.
  33     *
  34     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  35     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  36     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  37     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  38     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  39     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  40     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  41     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  42     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  43     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  44     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  45     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  46     *     THE POSSIBILITY OF SUCH DAMAGE.
  47     ********************************************************************* */
  48
  49
  50 /*
  51  * I/O Address assignments for the bcm91125c board
  52  *
  53  * Summary of address map:
  54  *
  55  * Address         Size   CSel    Description
  56  * --------------- ----   ------  --------------------------------
  57  * 0x1FC00000      2MB     CS0    Boot ROM
  58  * 0x1EC00000      16MB    CS1    Alternate boot ROM
  59  *                         CS2    Unused
  60  *                         CS3    Unused
  61  *                         CS4    Unused
  62  *                         CS5    Unused
  63  * 0x1D0A0000      64KB    CS6    LED dsplay
  64  *                         CS7    Unused
  65  *
  66  * GPIO assignments
  67  *
  68  * GPIO#    Direction   Description
  69  * -------  ---------   ------------------------------------------
  70  * GPIO0    Output      Debug LED
  71  * GPIO1    N/A         Not used, routed to daughter card
  72  * GPIO2    N/A         Not used, routed to daughter card
  73  * GPIO3    N/A         Not used, routed to daughter card
  74  * GPIO4    N/A         Not used, routed to daughter card
  75  * GPIO5    N/A         Not used, routed to daughter card
  76  * GPIO6    N/A         Not used, routed to daughter card
  77  * GPIO7    N/A         Not used, routed to daughter card
  78  * GPIO8    N/A         Not used, routed to daughter card
  79  * GPIO9    N/A         Not used, routed to daughter card
  80  * GPIO10   N/A         Not used, routed to daughter card
  81  * GPIO11   N/A         Not used, routed to daughter card
  82  * GPIO12   N/A         Not used, routed to daughter card
  83  * GPIO13   N/A         Not used, routed to daughter card
  84  * GPIO14   N/A         Not used, routed to daughter card
  85  * GPIO15   N/A         Not used, routed to daughter card
  86  */
  87
  88 /*  *********************************************************************
  89     *  Macros
  90     ********************************************************************* */
  91
  92 #define MB (1024*1024)
  93 #define K64 65536
  94 #define NUM64K(x) (((x)+(K64-1))/K64)
  95
  96
  97 /*  *********************************************************************
  98     *  GPIO pins
  99     ********************************************************************* */
 100
 101 #define GPIO_DEBUG_LED          0
 102
 103 #define M_GPIO_DEBUG_LED        _SB_MAKEMASK1(GPIO_DEBUG_LED)
 104
 105 #define GPIO_OUTPUT_MASK (M_GPIO_DEBUG_LED)
 106 #define GPIO_INTERRUPT_MASK (0)
 107
 108 /*  *********************************************************************
 109     *  Generic Bus
 110     ********************************************************************* */
 111
 112 #define BOOTROM_CS              0
 113 #define BOOTROM_PHYS            0x1FC00000      /* address of boot ROM (CS0) */
 114 #define BOOTROM_SIZE            NUM64K(2*MB)    /* size of boot ROM */
 115 #define BOOTROM_TIMING0         V_IO_ALE_WIDTH(4) | \
 116                                 V_IO_ALE_TO_CS(2) | \
 117                                 V_IO_CS_WIDTH(24) | \
 118                                 V_IO_RDY_SMPLE(1)
 119 #define BOOTROM_TIMING1         V_IO_ALE_TO_WRITE(7) | \
 120                                 V_IO_WRITE_WIDTH(7) | \
 121                                 V_IO_IDLE_CYCLE(6) | \
 122                                 V_IO_CS_TO_OE(0) | \
 123                                 V_IO_OE_TO_CS(0)
 124 #define BOOTROM_CONFIG          V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 125
 126 #define ALT_BOOTROM_CS          1
 127 #define ALT_BOOTROM_PHYS        0x1EC00000      /* address of alternate boot ROM (CS1) */
 128 #define ALT_BOOTROM_SIZE        NUM64K(16*MB)   /* size of alternate boot ROM */
 129 #define ALT_BOOTROM_TIMING0     V_IO_ALE_WIDTH(4) | \
 130                                 V_IO_ALE_TO_CS(2) | \
 131                                 V_IO_CS_WIDTH(24) | \
 132                                 V_IO_RDY_SMPLE(1)
 133 #define ALT_BOOTROM_TIMING1     V_IO_ALE_TO_WRITE(7) | \
 134                                 V_IO_WRITE_WIDTH(7) | \
 135                                 V_IO_IDLE_CYCLE(6) | \
 136                                 V_IO_CS_TO_OE(0) | \
 137                                 V_IO_OE_TO_CS(0)
 138 #define ALT_BOOTROM_CONFIG      V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 139
 140 /*
 141  * LEDs:  non-multiplexed, byte width, no parity, no ack
 142  */
 143 #define LEDS_CS                 6
 144 #define LEDS_PHYS               0x1D0A0000
 145 #define LEDS_SIZE               NUM64K(4)
 146 #define LEDS_TIMING0            V_IO_ALE_WIDTH(4) | \
 147                                 V_IO_ALE_TO_CS(2) | \
 148                                 V_IO_CS_WIDTH(13) | \
 149                                 V_IO_RDY_SMPLE(1)
 150 #define LEDS_TIMING1            V_IO_ALE_TO_WRITE(2) | \
 151                                 V_IO_WRITE_WIDTH(8) | \
 152                                 V_IO_IDLE_CYCLE(6) | \
 153                                 V_IO_CS_TO_OE(0) | \
 154                                 V_IO_OE_TO_CS(0)
 155 #define LEDS_CONFIG             V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 156
 157
 158
 159 /*  *********************************************************************
 160     *  SMBus Devices
 161     ********************************************************************* */
 162
 163 #define TEMPSENSOR_SMBUS_CHAN   0
 164 #define TEMPSENSOR_SMBUS_DEV    0x2A
 165 #define BIGEEPROM0_SMBUS_CHAN   0
 166 #define BIGEEPROM0_SMBUS_DEV    0x50
 167 #define BIGEEPROM1_SMBUS_CHAN   1
 168 #define BIGEEPROM1_SMBUS_DEV    0x50
 169
 170 #define M41T81_SMBUS_CHAN       1
 171 #define M41T81_SMBUS_DEV        0x68
 172
 173 #define SPDEEPROM_SMBUS_CHAN    0
 174 #define SPDEEPROM_SMBUS_DEV     0x54