release/src-rt-6.x.4708/cfe/cfe/arch/arm/board/bcm947xx/include/ddr40_variant.h

   1 /*
   2  * Description: This module defines global parameters for this type of ddr phy
   3  *
   4  * Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id:$
  19  */
  20
  21 #ifndef DDR40_TOP_MODULE_NAME
  22 #define DDR40_TOP_MODULE_NAME ddr40_phy_top_32_fc_40lp
  23 #define DDR40_PACKAGE_TYPE fc
  24
  25 #define DDR40_PROCESS_TYPE 40lp
  26
  27 #define DDR40_PACKAGE_TYPE_IS_FC
  28
  29 #ifndef DDR40_PROCESS_TYPE_IS_40LP
  30 #define DDR40_PROCESS_TYPE_IS_40LP
  31 #endif
  32
  33 #define DDR40_DQ_WIDTH 32
  34 #define DDR40_DQ_BYTES (DDR40_DQ_WIDTH/8)
  35
  36 #ifndef DDR40_WIDTH_IS_32
  37 #define DDR40_WIDTH_IS_32
  38 #endif
  39
  40 #undef DDR40_WIDTH_IS_32
  41
  42 #define DDR40_PROCESS_DETAIL tsmc40lp_M1_4Mx_1Mz_1UTRDL
  43
  44 /* feature list */
  45 #define DDR40_INCLUDE_AUX_PINS
  46 #define DDR40_FIX_RD_DATA_DLY_MINMAX
  47
  48 #define DDR40_CALIB_40LP_POST_DIV_FIX
  49 #define DDR40_USE_MEMC_DDR_SCAN_CLK
  50 #define DDR40_MAX_MIN_MIN_VDL_SCAN_CAPTURE
  51
  52 #define DDR40_PHYBIST_AUX_MASK_FIX
  53 #define DDR40_DDR3_CALIB_RESET_FIX
  54 #define DDR40_INCLUDE_NO_DQS_RD
  55 #define DDR40_USE_STANDBY_EXIT_PIN
  56
  57 #define DDR40_CLEAN_RST_N_FIX
  58 #define DDR40_USE_WIDE_DYN_VDL_EN
  59 #define DDR40_FIX_WR_ADDR_BUG
  60 #define DDR40_FIX_S2_EXIT_BUGS
  61 #define DDR40_INCLUDE_VDDO_CK
  62 #define DDR40_FIX_FREEZE_CKE_OFF
  63 #define DDR40_INCLUDE_MPR_MODE
  64 #define DDR40_INCLUDE_SINGLE_CYC
  65 #define DDR40_VTT_HANG_QUICK_FIX
  66 #define DDR40_EXPANDED_REVID
  67 #define DDR40_CC_AUTO_INIT_2ND_RESYNC_FIX
  68
  69 #define DDR40_CAL_RD_DATA_DLY_FIX
  70
  71 #endif /* DDR40_TOP_MODULE_NAME */