release/src-rt-6.x.4708/cfe/cfe/arch/arm/board/bcm947xx/include/ddr40_phy_init.h

   1 /*
   2 ** Copyright 2000, 2001  Broadcom Corporation
   3 ** All Rights Reserved
   4 **
   5 ** No portions of this material may be reproduced in any form
   6 ** without the written permission of:
   7 **
   8 **   Broadcom Corporation
   9 **   5300 California Avenue
  10 **   Irvine, California 92617
  11 **
  12 ** All information contained in this document is Broadcom
  13 ** Corporation company private proprietary, and trade secret.
  14 **
  15 ** ----------------------------------------------------------
  16 **
  17 **
  18 **
  19 *  $Id:: ddr40_phy_init.h 1758 2012-08-17 15:14:03Z gennady       $:
  20 *  $Rev::file =  : Global SVN Revision = 1780                     $:
  21 **
  22 */
  23
  24 #ifndef __DDR40_PHY_INIT_H__
  25 #define __DDR40_PHY_INIT_H__
  26
  27 #include <ddr40_phy_custom.h>
  28
  29 /*  !!!  VALUES ARE IMPORTANT, DO NOT CHANGE !!! */
  30 #define DDR40_PHY_PARAM_TESTMODE          0x00000004
  31 #define DDR40_PHY_PARAM_SKIP_PLL_VDL      0x00000008
  32 #define DDR40_PHY_PARAM_USE_VTT           0x00000100
  33 #define DDR40_PHY_PARAM_DIS_ODT           0x00000200
  34 #define DDR40_PHY_PARAM_DIS_DQS_ODT       0x00000400
  35 #define DDR40_PHY_PARAM_ODT_EARLY         0x00000800
  36 #define DDR40_PHY_PARAM_ODT_LATE          0x00001000
  37 #define DDR40_PHY_PARAM_AUTO_IDDQ_VALID   0x00100000
  38 #define DDR40_PHY_PARAM_AUTO_IDDQ_CMD     0x00200000
  39 #define DDR40_PHY_PARAM_AUTO_RXENB_VALID  0x00400000
  40 #define DDR40_PHY_PARAM_AUTO_RXENB_CMD    0x00800000
  41 #define DDR40_PHY_PARAM_ALLOW_VDL_NO_LOCK 0x40000000
  42 #define DDR40_PHY_PARAM_SKIP_RD_EN_ADJUST 0x80000000
  43 #define DDR40_PHY_PARAM_ADDR_CTL_ADJUST_0 0x00010000
  44 #define DDR40_PHY_PARAM_ADDR_CTL_ADJUST_1 0x00020000
  45 #define DDR40_PHY_PARAM_MAX_ZQ            0x00080000
  46 #define DDR40_PHY_PARAM_VDDO_VOLT_0       0x01000000
  47 #define DDR40_PHY_PARAM_VDDO_VOLT_1       0x02000000
  48 #define DDR40_PHY_PARAM_LONG_PREAMBLE     0x04000000
  49
  50 #define DDR40_PHY_RETURN_OK                0
  51 #define DDR40_PHY_RETURN_VDL_CALIB_NOLOCK  1
  52 #define DDR40_PHY_RETURN_RDEN_CALIB_NOLOCK 2
  53 #define DDR40_PHY_RETURN_STEP_CALIB_FAIL   3
  54 #define DDR40_PHY_RETURN_ZQ_CALIB_FAIL     4
  55 #define DDR40_PHY_RETURN_PLL_NOLOCK        0x110
  56 #define DDR40_PHY_RETURN_VDL_CALIB_FAIL    0x120
  57 #define DDR40_PHY_RETURN_RDEN_CALIB_FAIL   0x140
  58
  59 #define DDR40_PHY_DEFAULT_STEP_SIZE   13 /* ps */
  60
  61 /* main entry point */
  62 FUNC_PROTOTYPE_PREFIX uint32_t ddr40_phy_init(
  63         uint32_t ddr_clk, uint32_t params, int ddr_type, uint32_t * wire_dly,
  64         uint32_t connect, uint32_t override, ddr40_addr_t offset) FUNC_PROTOTYPE_SUFFIX;
  65
  66 /* other functions */
  67 FUNC_PROTOTYPE_PREFIX uint32_t ddr40_phy_setup_pll(
  68         uint32_t speed, ddr40_addr_t offset) FUNC_PROTOTYPE_SUFFIX;
  69 FUNC_PROTOTYPE_PREFIX void ddr40_phy_addr_ctl_adjust(
  70         uint32_t total_steps, ddr40_addr_t offset) FUNC_PROTOTYPE_SUFFIX;
  71
  72 #ifdef SV_SIM
  73 FUNC_PROTOTYPE_PREFIX void ddr40_phy_force_tmode(
  74         ddr40_addr_t offset) FUNC_PROTOTYPE_SUFFIX;
  75 FUNC_PROTOTYPE_PREFIX void ddr40_phy_rd_en_adjust(
  76         uint32_t total_steps0, uint32_t total_steps1, uint32_t rd_en_byte_mode,
  77         ddr40_addr_t offset, uint32_t wl_offset) FUNC_PROTOTYPE_SUFFIX;
  78 #ifdef DDR40_INCLUDE_ECC
  79 FUNC_PROTOTYPE_PREFIX void ddr40_phy_ecc_rd_en_adjust(
  80         uint32_t total_steps0, uint32_t rd_en_byte_mode,
  81         ddr40_addr_t offset) FUNC_PROTOTYPE_SUFFIX;
  82 #endif
  83 #endif /* SV_SIM */
  84
  85 FUNC_PROTOTYPE_PREFIX uint32_t ddr40_phy_vdl_normal(
  86         uint32_t vdl_no_lock, ddr40_addr_t offset) FUNC_PROTOTYPE_SUFFIX;
  87 FUNC_PROTOTYPE_PREFIX void ddr40_phy_vtt_on(
  88         uint32_t connect, uint32_t override, ddr40_addr_t offset) FUNC_PROTOTYPE_SUFFIX;
  89 FUNC_PROTOTYPE_PREFIX uint32_t ddr40_phy_calib_zq(
  90         uint32_t params, ddr40_addr_t offset) FUNC_PROTOTYPE_SUFFIX;
  91 FUNC_PROTOTYPE_PREFIX void ddr40_phy_rdly_odt(
  92         uint32_t speed, uint32_t params, ddr40_addr_t offset) FUNC_PROTOTYPE_SUFFIX;
  93 FUNC_PROTOTYPE_PREFIX void ddr40_phy_ddr3_misc(
  94         uint32_t speed, uint32_t params, ddr40_addr_t offset) FUNC_PROTOTYPE_SUFFIX;
  95 FUNC_PROTOTYPE_PREFIX void ddr40_phy_ddr2_misc(
  96         uint32_t speed, uint32_t params, ddr40_addr_t offset) FUNC_PROTOTYPE_SUFFIX;
  97 FUNC_PROTOTYPE_PREFIX void ddr40_phy_set_autoidle(
  98         uint32_t params, ddr40_addr_t offset) FUNC_PROTOTYPE_SUFFIX;
  99
 100 #define ddr40_phy_rd_en_calib(args...)
 101
 102 #define  DDR40_PHY_SVN_REVISION  2701  /* DO  NOT CHANGE ! */
 103
 104 #endif /* __DDR40_PHY_INIT_H__ */
 105
 106
 107 /*
 108 **
 109 ** $Log: $
 110 **
 111 */