release/src-rt/linux/linux-2.6/arch/mips/mm/cache.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 - 2003, 07 by Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2007 MIPS Technologies, Inc.
   8  */
   9 #include <linux/init.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/sched.h>
  13 #include <linux/mm.h>
  14
  15 #include <asm/cacheflush.h>
  16 #include <asm/processor.h>
  17 #include <asm/cpu.h>
  18 #include <asm/cpu-features.h>
  19
  20 /* Cache operations. */
  21 void (*flush_cache_all)(void);
  22 void (*__flush_cache_all)(void);
  23 void (*flush_cache_mm)(struct mm_struct *mm);
  24 void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
  25         unsigned long end);
  26 void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
  27         unsigned long pfn);
  28 void (*flush_icache_range)(unsigned long start, unsigned long end);
  29
  30 /* MIPS specific cache operations */
  31 void (*flush_cache_sigtramp)(unsigned long addr);
  32 void (*local_flush_data_cache_page)(void * addr);
  33 void (*flush_data_cache_page)(unsigned long addr);
  34 void (*flush_icache_all)(void);
  35
  36 EXPORT_SYMBOL_GPL(local_flush_data_cache_page);
  37 EXPORT_SYMBOL(flush_data_cache_page);
  38
  39 #ifdef CONFIG_DMA_NONCOHERENT
  40
  41 /* DMA cache operations. */
  42 void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
  43 void (*_dma_cache_wback)(unsigned long start, unsigned long size);
  44 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
  45
  46 EXPORT_SYMBOL(_dma_cache_wback_inv);
  47 EXPORT_SYMBOL(_dma_cache_wback);
  48 EXPORT_SYMBOL(_dma_cache_inv);
  49
  50 #endif /* CONFIG_DMA_NONCOHERENT */
  51
  52 /*
  53  * We could optimize the case where the cache argument is not BCACHE but
  54  * that seems very atypical use ...
  55  */
  56 asmlinkage int sys_cacheflush(unsigned long addr,
  57         unsigned long bytes, unsigned int cache)
  58 {
  59         struct vm_area_struct* vma;
  60
  61         if (bytes == 0)
  62                 return 0;
  63         if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes))
  64                 return -EFAULT;
  65
  66         if (cache & DCACHE)
  67         {
  68                 vma = find_vma(current->mm, (unsigned long) addr);
  69                 if (vma) {
  70                         flush_cache_range(vma,(unsigned long)addr,((unsigned long)addr) + bytes);
  71                 }
  72                 else {
  73                         __flush_cache_all();
  74                 }
  75         }
  76         if (cache & ICACHE)
  77         {
  78                 flush_icache_range(addr, addr + bytes);
  79         }
  80
  81         return 0;
  82 }
  83
  84 void *kmap_atomic_page_address(struct page *page);
  85
  86 void __flush_dcache_page(struct page *page)
  87 {
  88         unsigned long addr;
  89
  90         if (PageHighMem(page)) {
  91                 addr = (unsigned long) kmap_atomic_page_address(page);
  92                 if (addr) {
  93                         flush_data_cache_page(addr);
  94                         return;
  95                 }
  96         }
  97
  98         /*
  99          * We could delay the flush for the !page_mapping case too.  But that
 100          * case is for exec env/arg pages and those are %99 certainly going to
 101          * get faulted into the tlb (and thus flushed) anyways.
 102          */
 103         addr = (unsigned long) page_address(page);
 104         if (addr)
 105                 flush_data_cache_page(addr);
 106 }
 107
 108 EXPORT_SYMBOL(__flush_dcache_page);
 109
 110 void __flush_anon_page(struct page *page, unsigned long vmaddr)
 111 {
 112         unsigned long addr = (unsigned long) page_address(page);
 113
 114         if (pages_do_alias(addr, vmaddr)) {
 115                 if (page_mapped(page) && !Page_dcache_dirty(page)) {
 116                         void *kaddr;
 117
 118                         kaddr = kmap_coherent(page, vmaddr);
 119                         flush_data_cache_page((unsigned long)kaddr);
 120                         kunmap_coherent();
 121                 } else
 122                         flush_data_cache_page(addr);
 123         }
 124 }
 125
 126 EXPORT_SYMBOL(__flush_anon_page);
 127
 128 void __update_cache(struct vm_area_struct *vma, unsigned long address,
 129         pte_t pte)
 130 {
 131         struct page *page;
 132         unsigned long pfn, addr;
 133         int exec = (vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc;
 134
 135         pfn = pte_pfn(pte);
 136         if (unlikely(!pfn_valid(pfn)))
 137                 return;
 138         page = pfn_to_page(pfn);
 139         if (page_mapping(page))
 140         {
 141                 addr = (unsigned long) page_address(page);
 142                 if (exec || pages_do_alias(addr, address & PAGE_MASK))
 143                         if (addr)
 144                                 flush_data_cache_page(addr);
 145         }
 146 }
 147
 148 static char cache_panic[] __cpuinitdata =
 149         "Yeee, unsupported cache architecture.";
 150
 151 void __init cpu_early_probe_cache(void)
 152 {
 153         if (cpu_has_4k_cache) {
 154                 extern void __weak r4k_probe_cache(void);
 155
 156                 return r4k_probe_cache();
 157         }
 158 }
 159
 160 void __cpuinit cpu_cache_init(void)
 161 {
 162         if (cpu_has_3k_cache) {
 163                 extern void __weak r3k_cache_init(void);
 164
 165                 r3k_cache_init();
 166                 return;
 167         }
 168         if (cpu_has_6k_cache) {
 169                 extern void __weak r6k_cache_init(void);
 170
 171                 r6k_cache_init();
 172                 return;
 173         }
 174         if (cpu_has_4k_cache) {
 175                 extern void __weak r4k_cache_init(void);
 176
 177                 r4k_cache_init();
 178                 return;
 179         }
 180         if (cpu_has_8k_cache) {
 181                 extern void __weak r8k_cache_init(void);
 182
 183                 r8k_cache_init();
 184                 return;
 185         }
 186         if (cpu_has_tx39_cache) {
 187                 extern void __weak tx39_cache_init(void);
 188
 189                 tx39_cache_init();
 190                 return;
 191         }
 192         if (cpu_has_sb1_cache) {
 193                 extern void __weak sb1_cache_init(void);
 194
 195                 sb1_cache_init();
 196                 return;
 197         }
 198
 199         panic(cache_panic);
 200 }