release/src-rt/linux/linux-2.6/arch/mips/brcm-boards/bcm947xx/time.c

   1 /*
   2  * Copyright (C) 2008, Broadcom Corporation
   3  * All Rights Reserved.
   4  *
   5  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   6  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   7  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
   8  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
   9  *
  10  * $Id: time.c,v 1.9 2009/07/17 06:23:12 Exp $
  11  */
  12 #include <linux/config.h>
  13 #include <linux/init.h>
  14 #include <linux/kernel.h>
  15 #include <linux/sched.h>
  16 #include <linux/serial_reg.h>
  17 #include <linux/interrupt.h>
  18 #include <asm/addrspace.h>
  19 #include <asm/io.h>
  20 #include <asm/time.h>
  21
  22 #include <typedefs.h>
  23 #include <osl.h>
  24 #include <bcmutils.h>
  25 #include <bcmnvram.h>
  26 #include <hndsoc.h>
  27 #include <sbchipc.h>
  28 #include <siutils.h>
  29 #include <hndmips.h>
  30 #include <mipsinc.h>
  31 #include <hndcpu.h>
  32 #include <bcmdevs.h>
  33
  34 /* Global SB handle */
  35 extern si_t *bcm947xx_sih;
  36 extern spinlock_t bcm947xx_sih_lock;
  37
  38 /* Convenience */
  39 #define sih bcm947xx_sih
  40 #define sih_lock bcm947xx_sih_lock
  41
  42 #define WATCHDOG_MIN    3000    /* milliseconds */
  43 extern int panic_timeout;
  44 static int watchdog = 0;
  45 extern int bcm947xx_cpu_clk; //Tomato RAF features
  46
  47 #ifndef CONFIG_HWSIM
  48 static u8 *mcr = NULL;
  49 #endif /* CONFIG_HWSIM */
  50
  51 void __init
  52 bcm947xx_time_init(void)
  53 {
  54         unsigned int hz;
  55         char cn[8];
  56
  57         /*
  58          * Use deterministic values for initial counter interrupt
  59          * so that calibrate delay avoids encountering a counter wrap.
  60          */
  61         write_c0_count(0);
  62         write_c0_compare(0xffff);
  63
  64         /* 5354 could run both on 200 & 240 Mhz -- use nvram setting */
  65         if (sih->chip == BCM5354_CHIP_ID && nvram_match("clkfreq", "200"))
  66                 hz = 200000000;
  67         else
  68         if (!(hz = si_cpu_clock(sih)))
  69                 hz = 100000000;
  70
  71         bcm_chipname(sih->chip, cn, 8);
  72         printk("CPU: BCM%s rev %d pkg %d at %d MHz\n", cn, sih->chiprev, sih->chippkg,
  73                (hz + 500000) / 1000000);
  74         bcm947xx_cpu_clk = (hz + 500000) / 1000000; //Tomato RAF feature
  75
  76         /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
  77         if (sih->chip == BCM5354_CHIP_ID &&
  78                 strncmp(nvram_safe_get("hardware_version"), "WL520G", 6) == 0)
  79                 mips_hpt_frequency = 100000000; // Fix WL520GUGC clock
  80         else
  81                 mips_hpt_frequency = hz / 2;
  82
  83         /* Set watchdog interval in ms */
  84         watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
  85
  86         /* Ensure at least WATCHDOG_MIN */
  87         if ((watchdog > 0) && (watchdog < WATCHDOG_MIN))
  88                 watchdog = WATCHDOG_MIN;
  89
  90         /* Set panic timeout in seconds */
  91         panic_timeout = watchdog / 1000;
  92 }
  93
  94 #ifdef CONFIG_HND_BMIPS3300_PROF
  95 extern bool hndprofiling;
  96 #ifdef CONFIG_MIPS64
  97 typedef u_int64_t sbprof_pc;
  98 #else
  99 typedef u_int32_t sbprof_pc;
 100 #endif
 101 extern void sbprof_cpu_intr(sbprof_pc restartpc);
 102 #endif  /* CONFIG_HND_BMIPS3300_PROF */
 103
 104 static irqreturn_t
 105 bcm947xx_timer_interrupt(int irq, void *dev_id)
 106 {
 107 #ifdef CONFIG_HND_BMIPS3300_PROF
 108         /*
 109          * Are there any ExcCode or other mean(s) to determine what has caused
 110          * the timer interrupt? For now simply stop the normal timer proc if
 111          * count register is less than compare register.
 112          */
 113         if (hndprofiling) {
 114                 sbprof_cpu_intr(read_c0_epc() +
 115                                 ((read_c0_cause() >> (CAUSEB_BD - 2)) & 4));
 116                 if (read_c0_count() < read_c0_compare())
 117                         return (IRQ_HANDLED);
 118         }
 119 #endif  /* CONFIG_HND_BMIPS3300_PROF */
 120
 121         /* Generic MIPS timer code */
 122         timer_interrupt(irq, dev_id);
 123
 124         /* Set the watchdog timer to reset after the specified number of ms */
 125         if (watchdog > 0) {
 126                 if (((si_t *)sih)->chip == BCM5354_CHIP_ID)
 127                         si_watchdog(sih, WATCHDOG_CLOCK_5354 / 1000 * watchdog);
 128                 else
 129                         si_watchdog_ms(sih, watchdog);
 130         }
 131
 132 #ifdef  CONFIG_HWSIM
 133         (*((int *)0xa0000f1c))++;
 134 #else
 135         /* Blink one of the LEDs in the external UART */
 136         if (mcr && !(jiffies % (HZ/2)))
 137                 writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
 138 #endif
 139
 140         return (IRQ_HANDLED);
 141 }
 142
 143 static struct irqaction bcm947xx_timer_irqaction = {
 144         bcm947xx_timer_interrupt,
 145         IRQF_DISABLED,
 146         { { 0 } },
 147         "timer",
 148         NULL,
 149         NULL,
 150         0,
 151         NULL
 152 };
 153
 154 void __init
 155 plat_timer_setup(struct irqaction *irq)
 156 {
 157         /* Enable the timer interrupt */
 158         setup_irq(7, &bcm947xx_timer_irqaction);
 159 }
 160
 161 #define CFE_UPDATE 1            // added by Chen-I for mac/regulation update
 162
 163 #ifdef CFE_UPDATE
 164 void bcm947xx_watchdog_disable(void)
 165 {
 166         watchdog=0;
 167         si_watchdog(sih, 0);
 168 }
 169 #endif
 170