?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
K2.6 patches and update.
[tomato.git] / release / src-rt / bcm57xx / sys / tigon3.c
blobe5544ee52e8440fb2522cc52b0405c0521e1cdf0
1 /******************************************************************************/
2 /* */
3 /* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 - 2005 Broadcom */
4 /* Corporation. */
5 /* All rights reserved. */
6 /* */
7 /* This program is free software; you can redistribute it and/or modify */
8 /* it under the terms of the GNU General Public License as published by */
9 /* the Free Software Foundation, located in the file LICENSE. */
10 /* */
11 /* History: */
12 /******************************************************************************/
13
14 /* $Id: tigon3.c,v 1.15 2008-02-22 22:46:19 Exp $ */
15
16 #include "mm.h"
17 #include "bcmdevs.h"
18 #include "bcmutils.h"
19 #include "siutils.h"
20 #include "bcmrobo.h"
21
22 /******************************************************************************/
23 /* Local functions. */
24 /******************************************************************************/
25
26 LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice);
27 LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice);
28
29 static LM_STATUS LM_InitBcm540xPhy(PLM_DEVICE_BLOCK pDevice);
30 static LM_VOID LM_PhyTapPowerMgmt(LM_DEVICE_BLOCK *pDevice);
31
32 LM_VOID LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice);
33 LM_VOID LM_ServiceTxInterrupt(PLM_DEVICE_BLOCK pDevice);
34
35 static LM_STATUS LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice);
36 static LM_UINT32 GetPhyAdFlowCntrlSettings(PLM_DEVICE_BLOCK pDevice);
37 STATIC LM_STATUS LM_SetFlowControl(PLM_DEVICE_BLOCK pDevice,
38 LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd);
39 #ifdef INCLUDE_TBI_SUPPORT
40 STATIC LM_STATUS LM_SetupFiberPhy(PLM_DEVICE_BLOCK pDevice);
41 STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice);
42 #endif
43 STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice);
44 STATIC LM_VOID LM_SetEthWireSpeed(LM_DEVICE_BLOCK *pDevice);
45 STATIC LM_STATUS LM_PhyAdvertiseAll(LM_DEVICE_BLOCK *pDevice);
46 STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid);
47 LM_VOID LM_SwitchVaux(PLM_DEVICE_BLOCK pDevice, PLM_DEVICE_BLOCK pDevice2);
48 STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
49 LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize);
50 STATIC LM_STATUS LM_DisableChip(PLM_DEVICE_BLOCK pDevice);
51 STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice);
52 STATIC LM_STATUS LM_DisableFW(PLM_DEVICE_BLOCK pDevice);
53 STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
54 PT3_SND_BD pSendBd);
55 STATIC LM_VOID LM_WritePreResetSignatures(LM_DEVICE_BLOCK *pDevice,
56 LM_RESET_TYPE Mode);
57 STATIC LM_VOID LM_WritePostResetSignatures(LM_DEVICE_BLOCK *pDevice,
58 LM_RESET_TYPE Mode);
59 STATIC LM_VOID LM_WriteLegacySignatures(LM_DEVICE_BLOCK *pDevice,
60 LM_RESET_TYPE Mode);
61 STATIC void LM_GetPhyId(LM_DEVICE_BLOCK *pDevice);
62
63 /******************************************************************************/
64 /* External functions. */
65 /******************************************************************************/
66
67 LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice);
68 #ifdef INCLUDE_TCP_SEG_SUPPORT
69 LM_STATUS LM_LoadStkOffLdFirmware(PLM_DEVICE_BLOCK pDevice);
70 LM_UINT32 LM_GetStkOffLdFirmwareSize(PLM_DEVICE_BLOCK pDevice);
71 #endif
72
73 LM_UINT32
74 LM_RegRd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
75 {
76 #ifdef PCIX_TARGET_WORKAROUND
77 if (pDevice->Flags & UNDI_FIX_FLAG)
78 {
79 return (LM_RegRdInd(pDevice, Register));
80 }
81 else
82 #endif
83 {
84 return (REG_RD_OFFSET(pDevice, Register));
85 }
86 }
87
88 /* Mainly used to flush posted write before delaying */
89 LM_VOID
90 LM_RegRdBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
91 {
92 LM_UINT32 dummy;
93
94 #ifdef PCIX_TARGET_WORKAROUND
95 if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG)
96 {
97 return;
98 }
99 else
100 #endif
101 {
102 if (pDevice->Flags & REG_RD_BACK_FLAG)
103 return;
104
105 dummy = REG_RD_OFFSET(pDevice, Register);
106 }
107 }
108
109 LM_VOID
110 LM_RegWr(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32,
111 LM_UINT32 ReadBack)
112 {
113 #ifdef PCIX_TARGET_WORKAROUND
114 if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG)
115 {
116 LM_RegWrInd(pDevice, Register, Value32);
117 }
118 else
119 #endif
120 {
121 LM_UINT32 dummy;
122
123 REG_WR_OFFSET(pDevice, Register, Value32);
124 if (ReadBack && (pDevice->Flags & REG_RD_BACK_FLAG))
125 {
126 dummy = REG_RD_OFFSET(pDevice, Register);
127 }
128 }
129 }
130
131 /******************************************************************************/
132 /* Description: */
133 /* */
134 /* Return: */
135 /******************************************************************************/
136 LM_UINT32
137 LM_RegRdInd(
138 PLM_DEVICE_BLOCK pDevice,
139 LM_UINT32 Register) {
140 LM_UINT32 Value32;
141
142 MM_ACQUIRE_UNDI_LOCK(pDevice);
143 MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
144 MM_ReadConfig32(pDevice, T3_PCI_REG_DATA_REG, &Value32);
145 MM_RELEASE_UNDI_LOCK(pDevice);
146
147 return MM_SWAP_LE32(Value32);
148 } /* LM_RegRdInd */
149
150
151
152 /******************************************************************************/
153 /* Description: */
154 /* */
155 /* Return: */
156 /******************************************************************************/
157 LM_VOID
158 LM_RegWrInd(
159 PLM_DEVICE_BLOCK pDevice,
160 LM_UINT32 Register,
161 LM_UINT32 Value32) {
162
163 MM_ACQUIRE_UNDI_LOCK(pDevice);
164 MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
165 MM_WriteConfig32(pDevice, T3_PCI_REG_DATA_REG, MM_SWAP_LE32(Value32));
166 MM_RELEASE_UNDI_LOCK(pDevice);
167 } /* LM_RegWrInd */
168
169
170
171 /******************************************************************************/
172 /* Description: */
173 /* */
174 /* Return: */
175 /******************************************************************************/
176 LM_UINT32
177 LM_MemRdInd(
178 PLM_DEVICE_BLOCK pDevice,
179 LM_UINT32 MemAddr) {
180 LM_UINT32 Value32;
181
182 MM_ACQUIRE_UNDI_LOCK(pDevice);
183 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
184 MM_ReadConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);
185 MM_RELEASE_UNDI_LOCK(pDevice);
186
187 return MM_SWAP_LE32(Value32);
188 } /* LM_MemRdInd */
189
190
191
192 /******************************************************************************/
193 /* Description: */
194 /* */
195 /* Return: */
196 /******************************************************************************/
197 LM_VOID
198 LM_MemWrInd(
199 PLM_DEVICE_BLOCK pDevice,
200 LM_UINT32 MemAddr,
201 LM_UINT32 Value32) {
202 MM_ACQUIRE_UNDI_LOCK(pDevice);
203 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
204 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, MM_SWAP_LE32(Value32));
205 MM_RELEASE_UNDI_LOCK(pDevice);
206 } /* LM_MemWrInd */
207
208
209 /******************************************************************************/
210 /* Description: */
211 /* */
212 /* Return: */
213 /******************************************************************************/
214 LM_STATUS
215 LM_QueueRxPackets(
216 PLM_DEVICE_BLOCK pDevice) {
217 LM_STATUS Lmstatus;
218 PLM_PACKET pPacket;
219 PT3_RCV_BD pRcvBd = 0;
220 LM_UINT32 StdBdAdded = 0;
221 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
222 LM_UINT32 JumboBdAdded = 0;
223 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
224 LM_UINT32 ConIdx, Idx;
225 LM_UINT32 Diff = 0;
226
227 Lmstatus = LM_STATUS_SUCCESS;
228
229 if (pDevice->Flags & RX_BD_LIMIT_64_FLAG)
230 {
231 ConIdx = pDevice->pStatusBlkVirt->RcvStdConIdx;
232 Diff = (pDevice->RxStdProdIdx - ConIdx) &
233 T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
234 if (Diff >= 56)
235 {
236 if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container))
237 {
238 pDevice->QueueAgain = TRUE;
239 }
240 return LM_STATUS_SUCCESS;
241 }
242 }
243
244 pDevice->QueueAgain = FALSE;
245
246 pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
247 while(pPacket) {
248 switch(pPacket->u.Rx.RcvProdRing) {
249 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
250 case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
251 /* Initialize the buffer descriptor. */
252 Idx = pDevice->RxJumboProdIdx;
253 pRcvBd = &pDevice->pRxJumboBdVirt[Idx];
254
255 pPacket->u.Rx.RcvRingProdIdx = Idx;
256 pDevice->RxJumboRing[Idx] = pPacket;
257 /* Update the producer index. */
258 pDevice->RxJumboProdIdx = (Idx + 1) &
259 T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
260
261 JumboBdAdded++;
262 break;
263 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
264
265 case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
266 /* Initialize the buffer descriptor. */
267 Idx = pDevice->RxStdProdIdx;
268 pRcvBd = &pDevice->pRxStdBdVirt[Idx];
269
270 pPacket->u.Rx.RcvRingProdIdx = Idx;
271 pDevice->RxStdRing[Idx] = pPacket;
272 /* Update the producer index. */
273 pDevice->RxStdProdIdx = (Idx + 1) &
274 T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
275
276 StdBdAdded++;
277 break;
278
279 case T3_UNKNOWN_RCV_PROD_RING:
280 default:
281 Lmstatus = LM_STATUS_FAILURE;
282 break;
283 } /* switch */
284
285 /* Bail out if there is any error. */
286 if(Lmstatus != LM_STATUS_SUCCESS)
287 {
288 break;
289 }
290
291 /* Initialize the receive buffer pointer */
292 MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr);
293
294 /* The opaque field may point to an offset from a fix addr. */
295 pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) -
296 MM_UINT_PTR(pDevice->pPacketDescBase));
297
298 if ((pDevice->Flags & RX_BD_LIMIT_64_FLAG) &&
299 ((Diff + StdBdAdded) >= 63))
300 {
301 if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container))
302 {
303 pDevice->QueueAgain = TRUE;
304 }
305 break;
306 }
307 pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
308 } /* while */
309
310 MM_WMB();
311 /* Update the procedure index. */
312 if(StdBdAdded)
313 {
314 MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low,
315 pDevice->RxStdProdIdx);
316 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
317 {
318 MB_REG_RD(pDevice, Mailbox.RcvStdProdIdx.Low);
319 }
320 }
321 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
322 if(JumboBdAdded)
323 {
324 MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low,
325 pDevice->RxJumboProdIdx);
326 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
327 {
328 MB_REG_RD(pDevice, Mailbox.RcvJumboProdIdx.Low);
329 }
330 }
331 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
332
333 return Lmstatus;
334 } /* LM_QueueRxPackets */
335
336
337
338
339 #define EEPROM_CMD_TIMEOUT 100000
340 #define NVRAM_CMD_TIMEOUT 100000
341
342
343 /******************************************************************************/
344 /* Description: */
345 /* */
346 /* Return: */
347 /******************************************************************************/
348 STATIC LM_STATUS LM_NVRAM_AcquireLock( PLM_DEVICE_BLOCK pDevice )
349 {
350 LM_UINT i;
351 LM_UINT32 value32;
352 LM_STATUS status;
353
354 status = LM_STATUS_SUCCESS;
355
356 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
357 if (pDevice->Flags & SB_CORE_FLAG)
358 return status;
359
360 /* Request access to the flash interface. */
361 REG_WR( pDevice, Nvram.SwArb, SW_ARB_REQ_SET1 );
362
363 /*
364 * The worst case wait time for Nvram arbitration
365 * using serial eprom is about 45 msec on a 5704
366 * with the other channel loading boot code.
367 */
368 for( i = 0; i < NVRAM_CMD_TIMEOUT; i++ )
369 {
370 value32 = REG_RD( pDevice, Nvram.SwArb );
371 if( value32 & SW_ARB_GNT1 )
372 {
373 break;
374 }
375 MM_Wait(20);
376 }
377
378
379 return status;
380 } /* LM_NVRAM_AcquireLock */
381
382
383
384 /******************************************************************************/
385 /* Description: */
386 /* */
387 /* Return: */
388 /******************************************************************************/
389 STATIC LM_STATUS LM_NVRAM_ReleaseLock( PLM_DEVICE_BLOCK pDevice )
390 {
391 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
392 if (pDevice->Flags & SB_CORE_FLAG)
393 return LM_STATUS_SUCCESS;
394
395 /* Relinquish nvram interface. */
396 REG_WR( pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1 );
397 REG_RD_BACK( pDevice, Nvram.SwArb );
398
399 return LM_STATUS_SUCCESS;
400 } /* LM_NVRAM_ReleaseLock */
401
402
403
404 /******************************************************************************/
405 /* Description: */
406 /* */
407 /* Return: */
408 /******************************************************************************/
409 STATIC LM_STATUS
410 LM_EEPROM_ExecuteCommand( PLM_DEVICE_BLOCK pDevice, LM_UINT32 cmd )
411 {
412 LM_UINT32 i;
413 LM_UINT32 value32;
414 LM_STATUS status;
415
416 status = LM_STATUS_SUCCESS;
417
418 REG_WR( pDevice, Grc.EepromAddr, cmd );
419
420 for( i = 0; i < EEPROM_CMD_TIMEOUT; i++ )
421 {
422 value32 = REG_RD( pDevice, Grc.EepromAddr );
423 if( value32 & SEEPROM_ADDR_COMPLETE )
424 {
425 break;
426 }
427 MM_Wait(20);
428 }
429
430 if( i == EEPROM_CMD_TIMEOUT )
431 {
432 B57_ERR(("EEPROM command (0x%x) timed out!\n", cmd));
433 status = LM_STATUS_FAILURE;
434 }
435
436 return status;
437 } /* LM_EEPROM_ExecuteCommand */
438
439
440
441 /******************************************************************************/
442 /* Description: */
443 /* */
444 /* Return: */
445 /******************************************************************************/
446 STATIC LM_STATUS
447 LM_NVRAM_ExecuteCommand( PLM_DEVICE_BLOCK pDevice, LM_UINT32 cmd )
448 {
449 LM_UINT32 i;
450 LM_UINT32 value32;
451 LM_STATUS status;
452
453 status = LM_STATUS_SUCCESS;
454
455 REG_WR( pDevice, Nvram.Cmd, cmd );
456 REG_RD_BACK( pDevice, Nvram.Cmd );
457 MM_Wait(10);
458
459 /* Wait for the command to complete. */
460 for( i = 0; i < NVRAM_CMD_TIMEOUT; i++ )
461 {
462 value32 = REG_RD( pDevice, Nvram.Cmd );
463 if( value32 & NVRAM_CMD_DONE )
464 {
465 break;
466 }
467 MM_Wait(1);
468 }
469
470 if( i == NVRAM_CMD_TIMEOUT )
471 {
472 B57_ERR(("NVRAM command (0x%x) timed out!\n", cmd));
473 status = LM_STATUS_FAILURE;
474 }
475
476 return status;
477 } /* LM_NVRAM_ExecuteCommand */
478
479
480
481 /******************************************************************************/
482 /* Description: */
483 /* */
484 /* Return: */
485 /******************************************************************************/
486 STATIC LM_STATUS
487 LM_EEPROM_Read_UINT32( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
488 LM_UINT32 * data )
489 {
490 LM_UINT32 value32;
491 LM_UINT32 Addr;
492 LM_UINT32 Dev;
493 LM_STATUS status;
494
495 Dev = offset / pDevice->flashinfo.chipsize;
496 Addr = offset % pDevice->flashinfo.chipsize;
497
498 value32 = REG_RD( pDevice, Grc.EepromAddr );
499 value32 &= ~(SEEPROM_ADDR_DEV_ID_MASK | SEEPROM_ADDR_ADDRESS_MASK |
500 SEEPROM_ADDR_RW_MASK);
501 value32 |= SEEPROM_ADDR_DEV_ID(Dev) | SEEPROM_ADDR_ADDRESS(Addr) |
502 SEEPROM_ADDR_START | SEEPROM_ADDR_READ;
503
504 status = LM_EEPROM_ExecuteCommand( pDevice, value32 );
505 if( status == LM_STATUS_SUCCESS )
506 {
507 value32 = REG_RD( pDevice, Grc.EepromData );
508
509 /* The endianess of the eeprom and flash interface is different */
510 *data = MM_SWAP_LE32( value32 );
511 }
512
513 return status;
514 } /* LM_EEPROM_Read_UINT32 */
515
516
517
518 /******************************************************************************/
519 /* Description: */
520 /* */
521 /* Return: */
522 /******************************************************************************/
523 STATIC LM_STATUS
524 LM_NVRAM_Read_UINT32( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
525 LM_UINT32 * data )
526 {
527 LM_UINT32 physaddr;
528 LM_UINT32 ctrlreg;
529 LM_UINT32 value32;
530 LM_STATUS status;
531
532 if( pDevice->flashinfo.jedecnum == JEDEC_ATMEL &&
533 pDevice->flashinfo.buffered == TRUE )
534 {
535 /*
536 * One supported flash part has 9 address bits to address a
537 * particular page and another 9 address bits to address a
538 * particular byte within that page.
539 */
540 LM_UINT32 pagenmbr;
541
542 pagenmbr = offset / pDevice->flashinfo.pagesize;
543 pagenmbr = pagenmbr << ATMEL_AT45DB0X1B_PAGE_POS;
544
545 physaddr = pagenmbr + (offset % pDevice->flashinfo.pagesize);
546 }
547 else
548 {
549 physaddr = offset;
550 }
551
552 REG_WR( pDevice, Nvram.Addr, physaddr );
553
554 ctrlreg = NVRAM_CMD_DONE | NVRAM_CMD_DO_IT |
555 NVRAM_CMD_LAST | NVRAM_CMD_FIRST | NVRAM_CMD_RD;
556
557 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
558 if( status == LM_STATUS_SUCCESS )
559 {
560 value32 = REG_RD( pDevice, Nvram.ReadData );
561
562 /*
563 * Data is swapped so that the byte stream is the same
564 * in big and little endian systems. Caller will do
565 * additional swapping depending on how it wants to
566 * look at the data.
567 */
568 *data = MM_SWAP_BE32( value32 );
569 }
570
571 return status;
572 } /* LM_NVRAM_Read_UINT32 */
573
574
575 /******************************************************************************/
576 /* Description: */
577 /* */
578 /* Return: */
579 /******************************************************************************/
580 STATIC LM_VOID
581 LM_EEPROM_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
582 {
583 LM_UINT32 cursize;
584 LM_UINT32 value32;
585 LM_STATUS status;
586
587 /*
588 * Initialize the chipsize to the largest EEPROM size we support.
589 * This will intentionally restrict our sizing operations to the
590 * first EEPROM chip.
591 */
592 pDevice->flashinfo.chipsize = ATMEL_AT24C512_CHIP_SIZE;
593
594 value32 = 0;
595
596 /* If anything fails, use the smallest chip as the default chip size. */
597 cursize = ATMEL_AT24C64_CHIP_SIZE;
598
599 status = LM_NvramRead(pDevice, 0, &value32);
600 if( status != LM_STATUS_SUCCESS )
601 {
602 goto done;
603 }
604
605 value32 = MM_SWAP_BE32(value32);
606 if( value32 != 0x669955aa )
607 {
608 goto done;
609 }
610
611 /*
612 * Size the chip by reading offsets at increasing powers of two.
613 * When we encounter our validation signature, we know the addressing
614 * has wrapped around, and thus have our chip size.
615 */
616 while( cursize < ATMEL_AT24C64_CHIP_SIZE )
617 {
618 status = LM_NvramRead(pDevice, cursize, &value32);
619 if( status != LM_STATUS_SUCCESS )
620 {
621 cursize = ATMEL_AT24C64_CHIP_SIZE;
622 break;
623 }
624
625 value32 = MM_SWAP_BE32(value32);
626 if( value32 == 0x669955aa )
627 {
628 break;
629 }
630 cursize <<= 1;
631 }
632
633 done:
634
635 *size = cursize;
636 pDevice->flashinfo.pagesize = cursize;
637
638
639 } /* LM_EEPROM_ReadSize */
640
641 /******************************************************************************/
642 /* Description: */
643 /* */
644 /* Return: */
645 /******************************************************************************/
646 STATIC LM_STATUS
647 LM_FLASH_Atmel_Buffered_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
648 {
649 LM_UINT32 config3;
650 LM_UINT32 value32;
651 LM_STATUS status;
652
653 /* Temporarily replace the read command with a "read ID" command. */
654 config3 = REG_RD( pDevice, Nvram.Config3 );
655 value32 = config3 & ~NVRAM_READ_COMMAND(NVRAM_COMMAND_MASK);
656 value32 |= NVRAM_READ_COMMAND(0x57);
657 REG_WR( pDevice, Nvram.Config3, value32 );
658
659 REG_WR( pDevice, Nvram.Addr, 0x0 );
660
661 status = LM_NVRAM_Read_UINT32(pDevice, 0x0, &value32);
662
663 /* Restore the original read command. */
664 REG_WR( pDevice, Nvram.Config3, config3 );
665 if( status == LM_STATUS_SUCCESS )
666 {
667 switch( value32 & 0x3c )
668 {
669 case 0x0c:
670 *size = (1 * (1<<20))/8;
671 break;
672 case 0x14:
673 *size = (2 * (1<<20))/8;
674 break;
675 case 0x1c:
676 *size = (4 * (1<<20))/8;
677 break;
678 case 0x24:
679 *size = (8 * (1<<20))/8;
680 break;
681 }
682 }
683
684 return status;
685 } /* LM_FLASH_Atmel_Buffered_ReadSize */
686
687
688
689 /******************************************************************************/
690 /* Description: */
691 /* */
692 /* Return: */
693 /******************************************************************************/
694 STATIC LM_STATUS
695 LM_FLASH_ST_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
696 {
697 LM_STATUS status;
698 LM_UINT32 i;
699 LM_UINT32 ctrlreg;
700 LM_UINT32 value32;
701 LM_UINT32 config1;
702
703 /* We need to get the size through pass-thru mode. */
704 config1 = REG_RD( pDevice, Nvram.Config1 );
705 value32 = config1 | FLASH_PASS_THRU_MODE;
706 REG_WR( pDevice, Nvram.Config1, value32 );
707
708 /* Issue the "read ID" command. */
709 REG_WR( pDevice, Nvram.WriteData, 0x9f );
710
711 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_FIRST | NVRAM_CMD_WR;
712 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
713 if( status == LM_STATUS_FAILURE )
714 {
715 goto done;
716 }
717
718 /* Read in the "read ID" response. */
719 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
720
721 /* Discard the first three bytes. */
722 for( i = 0; i < 2; i++ )
723 {
724 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
725 if( status == LM_STATUS_FAILURE )
726 {
727 goto done;
728 }
729
730 value32 = REG_RD(pDevice, Nvram.ReadData);
731 }
732
733 ctrlreg |= NVRAM_CMD_LAST;
734
735 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
736 if( status == LM_STATUS_SUCCESS )
737 {
738 value32 = REG_RD(pDevice, Nvram.ReadData) & 0xff;
739 switch( value32 )
740 {
741 case 0x11:
742 *size = (1 * (1<<20)) / 8;
743 break;
744 case 0x12:
745 *size = (2 * (1<<20)) / 8;
746 break;
747 case 0x13:
748 *size = (4 * (1<<20)) / 8;
749 break;
750 case 0x14:
751 *size = (8 * (1<<20)) / 8;
752 break;
753 }
754 }
755
756 done:
757
758 /* Restore the previous flash mode. */
759 REG_WR( pDevice, Nvram.Config1, config1 );
760
761 return status;
762 } /* LM_FLASH_ST_ReadSize */
763
764
765
766 /******************************************************************************/
767 /* Description: */
768 /* */
769 /* Return: */
770 /******************************************************************************/
771 STATIC LM_STATUS
772 LM_FLASH_Saifun_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
773 {
774 LM_UINT32 config3;
775 LM_UINT32 value32;
776 LM_STATUS status;
777
778 /* Temporarily replace the read command with a "read ID" command. */
779 config3 = REG_RD( pDevice, Nvram.Config3 );
780 value32 = config3 & ~NVRAM_READ_COMMAND(NVRAM_COMMAND_MASK);
781 value32 |= NVRAM_READ_COMMAND(0xab);
782 REG_WR( pDevice, Nvram.Config3, value32 );
783
784 REG_WR( pDevice, Nvram.Addr, 0x0 );
785
786 status = LM_NVRAM_Read_UINT32(pDevice, 0x0, &value32);
787
788 /* Restore the original read command. */
789 REG_WR( pDevice, Nvram.Config3, config3 );
790
791 if( status == LM_STATUS_SUCCESS )
792 {
793 switch( value32 & 0xff )
794 {
795 case 0x05:
796 *size = (512 * (1<<10)/8);
797 break;
798 case 0x10:
799 *size = (1 * (1<<20)/8);
800 break;
801 case 0x11:
802 *size = (2 * (1<<20)/8);
803 break;
804 }
805 }
806
807 return status;
808 } /* LM_FLASH_Saifun_ReadSize */
809
810
811
812 /******************************************************************************/
813 /* Description: */
814 /* */
815 /* Return: */
816 /******************************************************************************/
817 STATIC LM_STATUS
818 LM_FLASH_ReadSize( PLM_DEVICE_BLOCK pDevice, LM_UINT32 * size )
819 {
820 LM_UINT32 value32;
821 LM_STATUS status;
822
823 status = LM_NVRAM_AcquireLock( pDevice );
824 if( status == LM_STATUS_FAILURE )
825 {
826 return status;
827 }
828
829 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
830 {
831 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
832 {
833 value32 = REG_RD( pDevice, Nvram.NvmAccess );
834 value32 |= NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE;
835 REG_WR( pDevice, Nvram.NvmAccess, value32 );
836 }
837 }
838
839 switch( pDevice->flashinfo.jedecnum )
840 {
841 case JEDEC_ST:
842 status = LM_FLASH_ST_ReadSize( pDevice, size );
843 break;
844 case JEDEC_ATMEL:
845 if( pDevice->flashinfo.buffered == TRUE )
846 {
847 status = LM_FLASH_Atmel_Buffered_ReadSize( pDevice, size );
848 }
849 else
850 {
851 status = LM_STATUS_FAILURE;
852 }
853 break;
854 case JEDEC_SAIFUN:
855 status = LM_FLASH_Saifun_ReadSize( pDevice, size );
856 break;
857 case JEDEC_SST:
858 default:
859 status = LM_STATUS_FAILURE;
860 }
861
862 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
863 {
864 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
865 {
866 value32 = REG_RD( pDevice, Nvram.NvmAccess );
867 value32 &= ~(NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
868 REG_WR( pDevice, Nvram.NvmAccess, value32 );
869 }
870 }
871
872 LM_NVRAM_ReleaseLock( pDevice );
873
874 return status;
875 } /* LM_FLASH_ReadSize */
876
877 STATIC LM_VOID LM_NVRAM_Detect_570X( PLM_DEVICE_BLOCK pDevice )
878 {
879 LM_UINT32 value32;
880
881 value32 = REG_RD(pDevice, Nvram.Config1);
882
883 if( (value32 & FLASH_INTERFACE_ENABLE) == 0 )
884 {
885 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
886 }
887 else
888 {
889 /*
890 * 5705 and older products do not have bits 24 and 25 defined.
891 * If we've gotten here, then we can guarantee the flash is
892 * an Atmel AT45DB011DB.
893 */
894 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
895 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
896 pDevice->flashinfo.pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
897 pDevice->flashinfo.buffered = TRUE;
898 }
899 } /* LM_NVRAM_Detect_570X */
900
901 STATIC LM_VOID LM_NVRAM_Detect_5750( PLM_DEVICE_BLOCK pDevice )
902 {
903 LM_UINT32 value32;
904
905 value32 = REG_RD(pDevice, Nvram.Config1);
906
907 if( (value32 & FLASH_INTERFACE_ENABLE) == 0 )
908 {
909 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
910 return;
911 }
912
913 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
914
915 switch( value32 & FLASH_PART_5750_TYPEMASK )
916 {
917 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
918 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
919 pDevice->flashinfo.pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
920 pDevice->flashinfo.buffered = TRUE;
921 break;
922 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
923 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
924 pDevice->flashinfo.pagesize = ATMEL_AT25F512_PAGE_SIZE;
925 pDevice->flashinfo.buffered = FALSE;
926 break;
927 case FLASH_VENDOR_ST:
928 pDevice->flashinfo.jedecnum = JEDEC_ST;
929 pDevice->flashinfo.pagesize = ST_M45PEX0_PAGE_SIZE;
930 pDevice->flashinfo.buffered = TRUE;
931 break;
932 case FLASH_VENDOR_SAIFUN:
933 pDevice->flashinfo.jedecnum = JEDEC_SAIFUN;
934 pDevice->flashinfo.pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
935 pDevice->flashinfo.buffered = FALSE;
936 break;
937 case FLASH_VENDOR_SST_SMALL:
938 case FLASH_VENDOR_SST_LARGE:
939 pDevice->flashinfo.jedecnum = JEDEC_SST;
940 pDevice->flashinfo.pagesize = SST_25VF0X0_PAGE_SIZE;
941 pDevice->flashinfo.buffered = FALSE;
942 break;
943 default:
944 B57_ERR(("bcm5700 : Unknown NVRAM type.\n"));
945 pDevice->flashinfo.jedecnum = 0;
946 pDevice->flashinfo.romtype = 0;
947 pDevice->flashinfo.buffered = FALSE;
948 pDevice->flashinfo.pagesize = 0;
949 }
950 } /* LM_NVRAM_Detect_5750 */
951
952 STATIC LM_VOID LM_NVRAM_Detect_5752( PLM_DEVICE_BLOCK pDevice )
953 {
954 LM_BOOL supported;
955 LM_UINT32 value32;
956
957 supported = FALSE;
958
959 value32 = REG_RD(pDevice, Nvram.Config1);
960
961 if(value32 & BIT_27)
962 pDevice->Flags |= PROTECTED_NVRAM_FLAG;
963
964 switch( value32 & FLASH_PART_5752_TYPEMASK )
965 {
966 case FLASH_PART_5752_EEPROM_ATMEL_64K:
967 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
968 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
969 pDevice->flashinfo.buffered = FALSE;
970 pDevice->flashinfo.chipsize = (64 * (1<<10)/8);
971 supported = TRUE;
972 break;
973
974 case FLASH_PART_5752_EEPROM_ATMEL_376K:
975 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
976 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
977 pDevice->flashinfo.buffered = FALSE;
978 pDevice->flashinfo.chipsize = (512 * (1<<10)/8);
979 supported = TRUE;
980 break;
981
982 case FLASH_PART_5752_FLASH_ATMEL_AT45DB041:
983 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
984 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
985 pDevice->flashinfo.buffered = TRUE;
986 pDevice->flashinfo.chipsize = (4 * (1<<20)) / 8;
987 supported = TRUE;
988 break;
989
990 case FLASH_PART_5752_FLASH_ATMEL_AT25F512:
991 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
992 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
993 pDevice->flashinfo.buffered = FALSE;
994 pDevice->flashinfo.chipsize = (512 * (1<<10)/8);
995 supported = TRUE;
996 break;
997
998 case FLASH_PART_5752_FLASH_ST_M25P10A:
999 pDevice->flashinfo.jedecnum = JEDEC_ST;
1000 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1001 pDevice->flashinfo.buffered = TRUE;
1002 pDevice->flashinfo.chipsize = (1 * (1<<20)) / 8;
1003 supported = TRUE;
1004 break;
1005 case FLASH_PART_5752_FLASH_ST_M25P05A:
1006 pDevice->flashinfo.jedecnum = JEDEC_ST;
1007 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1008 pDevice->flashinfo.buffered = TRUE;
1009 pDevice->flashinfo.chipsize = (512 * (1<<10)/8);
1010 supported = TRUE;
1011 break;
1012
1013 case FLASH_PART_5752_FLASH_ST_M45PE10:
1014 pDevice->flashinfo.jedecnum = JEDEC_ST;
1015 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1016 pDevice->flashinfo.buffered = TRUE;
1017 pDevice->flashinfo.chipsize = (1 * (1<<20)) / 8;
1018 supported = TRUE;
1019 break;
1020
1021 case FLASH_PART_5752_FLASH_ST_M45PE20:
1022 pDevice->flashinfo.jedecnum = JEDEC_ST;
1023 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1024 pDevice->flashinfo.buffered = TRUE;
1025 pDevice->flashinfo.chipsize = (2 * (1<<20)) / 8;
1026 supported = TRUE;
1027 break;
1028
1029 case FLASH_PART_5752_FLASH_ST_M45PE40:
1030 pDevice->flashinfo.jedecnum = JEDEC_ST;
1031 pDevice->flashinfo.romtype = ROM_TYPE_FLASH;
1032 pDevice->flashinfo.buffered = TRUE;
1033 pDevice->flashinfo.chipsize = (4 * (1<<20)) / 8;
1034 supported = TRUE;
1035 break;
1036 default:
1037 B57_ERR(("bcm5700 : Unknown NVRAM type.\n"));
1038 }
1039
1040 if( pDevice->flashinfo.romtype == ROM_TYPE_FLASH )
1041 {
1042 switch( value32 & FLASH_PART_5752_PAGEMASK )
1043 {
1044 case FLASH_PART_5752_PAGE_SIZE_256B:
1045 pDevice->flashinfo.pagesize = 256;
1046 break;
1047 case FLASH_PART_5752_PAGE_SIZE_512B:
1048 pDevice->flashinfo.pagesize = 512;
1049 break;
1050 case FLASH_PART_5752_PAGE_SIZE_1K:
1051 pDevice->flashinfo.pagesize = 1024;
1052 break;
1053 case FLASH_PART_5752_PAGE_SIZE_2K:
1054 pDevice->flashinfo.pagesize = 2048;
1055 break;
1056 case FLASH_PART_5752_PAGE_SIZE_4K:
1057 pDevice->flashinfo.pagesize = 4096;
1058 break;
1059 case FLASH_PART_5752_PAGE_SIZE_264B:
1060 pDevice->flashinfo.pagesize = 264;
1061 break;
1062 default:
1063 B57_ERR(("bcm5700 : Unknown NVRAM page size.\n"));
1064 supported = FALSE;
1065 }
1066 }
1067
1068 if( supported != TRUE )
1069 {
1070 B57_ERR(("Flash type unsupported!!!\n"));
1071 pDevice->flashinfo.jedecnum = 0;
1072 pDevice->flashinfo.romtype = 0;
1073 pDevice->flashinfo.buffered = FALSE;
1074 pDevice->flashinfo.pagesize = 0;
1075 }
1076
1077
1078 } /* LM_NVRAM_Detect_5752 */
1079
1080
1081 /******************************************************************************/
1082 /* Description: */
1083 /* */
1084 /* Return: */
1085 /******************************************************************************/
1086 STATIC LM_VOID LM_NVRAM_Init( PLM_DEVICE_BLOCK pDevice )
1087 {
1088 LM_UINT32 Value32;
1089
1090 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
1091 if (pDevice->Flags & SB_CORE_FLAG)
1092 return;
1093
1094 pDevice->NvramSize = 0;
1095
1096 /* Intialize clock period and state machine. */
1097 Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) |
1098 SEEPROM_ADDR_FSM_RESET;
1099 REG_WR(pDevice, Grc.EepromAddr, Value32);
1100 REG_RD_BACK(pDevice, Grc.EepromAddr);
1101
1102 MM_Wait(100);
1103
1104 /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
1105 Value32 = REG_RD(pDevice, Grc.LocalCtrl);
1106 REG_WR(pDevice, Grc.LocalCtrl, Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
1107
1108 switch( T3_ASIC_REV(pDevice->ChipRevId) )
1109 {
1110 case T3_ASIC_REV_5700:
1111 case T3_ASIC_REV_5701:
1112 pDevice->flashinfo.romtype = ROM_TYPE_EEPROM;
1113 break;
1114 case T3_ASIC_REV_5752:
1115 LM_NVRAM_Detect_5752(pDevice);
1116 break;
1117 case T3_ASIC_REV_5714_A0:
1118 case T3_ASIC_REV_5780:
1119 case T3_ASIC_REV_5714:
1120 case T3_ASIC_REV_5750:
1121 LM_NVRAM_Detect_5750(pDevice);
1122 break;
1123 default:
1124 LM_NVRAM_Detect_570X(pDevice);
1125 }
1126
1127 /* Set the 5701 compatibility mode if we are using EEPROM. */
1128 if( T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
1129 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701 &&
1130 pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1131 {
1132 Value32 = REG_RD(pDevice, Nvram.Config1);
1133
1134 if( T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1135 {
1136 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1137 {
1138 REG_WR(pDevice, Nvram.NvmAccess,
1139 REG_RD(pDevice, Nvram.NvmAccess) | ACCESS_EN);
1140 }
1141 }
1142
1143 /* Use the new interface to read EEPROM. */
1144 Value32 &= ~FLASH_COMPAT_BYPASS;
1145
1146 REG_WR(pDevice, Nvram.Config1, Value32);
1147
1148 if( T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1149 {
1150 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1151 {
1152 REG_WR(pDevice, Nvram.NvmAccess,
1153 REG_RD(pDevice, Nvram.NvmAccess) & ~ACCESS_EN);
1154 }
1155 }
1156 }
1157
1158 if( !(T3_ASIC_5752(pDevice->ChipRevId)) )
1159 {
1160 if( pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1161 {
1162 /* The only EEPROM we support is an ATMEL */
1163 pDevice->flashinfo.jedecnum = JEDEC_ATMEL;
1164 pDevice->flashinfo.pagesize = 0;
1165 pDevice->flashinfo.buffered = FALSE;
1166
1167 LM_EEPROM_ReadSize( pDevice, &pDevice->flashinfo.chipsize );
1168 }
1169 else
1170 {
1171 LM_FLASH_ReadSize( pDevice, &pDevice->flashinfo.chipsize );
1172 pDevice->Flags |= FLASH_DETECTED_FLAG;
1173 }
1174 }
1175
1176 pDevice->NvramSize = pDevice->flashinfo.chipsize;
1177
1178 B57_INFO(("*nvram:size=0x%x jnum=0x%x page=0x%x buff=0x%x \n",
1179 pDevice->NvramSize, pDevice->flashinfo.jedecnum,
1180 pDevice->flashinfo.pagesize, pDevice->flashinfo.buffered));
1181
1182 } /* LM_NVRAM_Init */
1183
1184
1185
1186 /******************************************************************************/
1187 /* Description: */
1188 /* */
1189 /* Return: */
1190 /******************************************************************************/
1191 LM_STATUS
1192 LM_NvramRead( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset, LM_UINT32 * data )
1193 {
1194 LM_UINT32 value32;
1195 LM_STATUS status;
1196
1197 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
1198 if (pDevice->Flags & SB_CORE_FLAG) {
1199 *data = 0xffffffff;
1200 return LM_STATUS_FAILURE;
1201 }
1202
1203 if( offset >= pDevice->flashinfo.chipsize )
1204 {
1205 return LM_STATUS_FAILURE;
1206 }
1207
1208 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
1209 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 )
1210 {
1211 status = LM_EEPROM_Read_UINT32( pDevice, offset, data );
1212 }
1213 else
1214 {
1215 status = LM_NVRAM_AcquireLock( pDevice );
1216 if( status == LM_STATUS_FAILURE )
1217 {
1218 return status;
1219 }
1220
1221 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1222 {
1223 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1224 {
1225 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1226 value32 |= NVRAM_ACCESS_ENABLE;
1227 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1228 }
1229 }
1230
1231 status = LM_NVRAM_Read_UINT32(pDevice, offset, data);
1232
1233 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1234 {
1235 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1236 {
1237 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1238 value32 &= ~NVRAM_ACCESS_ENABLE;
1239 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1240 }
1241 }
1242
1243 LM_NVRAM_ReleaseLock( pDevice );
1244 }
1245
1246 return status;
1247 } /* LM_NvramRead */
1248
1249
1250
1251 #ifdef ETHTOOL_SEEPROM
1252
1253 /******************************************************************************/
1254 /* Description: */
1255 /* */
1256 /* Return: */
1257 /******************************************************************************/
1258 STATIC LM_STATUS
1259 LM_NVRAM_ReadBlock(PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1260 LM_UINT8 *data, LM_UINT32 size)
1261 {
1262 LM_STATUS status;
1263 LM_UINT32 value32;
1264 LM_UINT32 bytecnt;
1265 LM_UINT8 * srcptr;
1266
1267 status = LM_STATUS_SUCCESS;
1268
1269 while( size > 0 )
1270 {
1271 /* Make sure the read is word aligned. */
1272 value32 = offset & 0x3;
1273 if( value32 )
1274 {
1275 bytecnt = sizeof(LM_UINT32) - value32;
1276 offset -= value32;
1277 srcptr = (LM_UINT8 *)(&value32) + value32;
1278 }
1279 else
1280 {
1281 bytecnt = sizeof(LM_UINT32);
1282 srcptr = (LM_UINT8 *)(&value32);
1283 }
1284
1285 if( bytecnt > size )
1286 {
1287 bytecnt = size;
1288 }
1289
1290 if( T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
1291 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701 )
1292 {
1293 status = LM_NVRAM_Read_UINT32( pDevice, offset, &value32 );
1294 }
1295 else
1296 {
1297 status = LM_EEPROM_Read_UINT32( pDevice, offset, &value32 );
1298 }
1299
1300 if( status != LM_STATUS_SUCCESS )
1301 {
1302 break;
1303 }
1304
1305 memcpy( data, srcptr, bytecnt );
1306
1307 offset += sizeof(LM_UINT32);
1308 data += bytecnt;
1309 size -= bytecnt;
1310 }
1311
1312 return status;
1313 } /* LM_NVRAM_ReadBlock */
1314
1315 /******************************************************************************/
1316 /* Description: */
1317 /* */
1318 /* Return: */
1319 /******************************************************************************/
1320 STATIC LM_STATUS
1321 LM_EEPROM_WriteBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1322 LM_UINT8 * data, LM_UINT32 size )
1323 {
1324 LM_UINT8 * dstptr;
1325 LM_UINT32 value32;
1326 LM_UINT32 bytecnt;
1327 LM_UINT32 subword1;
1328 LM_UINT32 subword2;
1329 LM_UINT32 Addr;
1330 LM_UINT32 Dev;
1331 LM_STATUS status;
1332
1333 if( offset > pDevice->flashinfo.chipsize )
1334 {
1335 return LM_STATUS_FAILURE;
1336 }
1337
1338 status = LM_STATUS_SUCCESS;
1339
1340 if( size == 0 )
1341 {
1342 return status;
1343 }
1344
1345 if( offset & 0x3 )
1346 {
1347 /*
1348 * If our initial offset does not fall on a word boundary, we
1349 * have to do a read / modify / write to preserve the
1350 * preceding bits we are not interested in.
1351 */
1352 status = LM_EEPROM_Read_UINT32(pDevice, offset & ~0x3, &subword1);
1353 if( status == LM_STATUS_FAILURE )
1354 {
1355 return status;
1356 }
1357 }
1358
1359 if( (offset + size) & 0x3 )
1360 {
1361 /*
1362 * Likewise, if our ending offset does not fall on a word
1363 * boundary, we have to do a read / modify / write to
1364 * preserve the trailing bits we are not interested in.
1365 */
1366 status = LM_EEPROM_Read_UINT32( pDevice, (offset + size) & ~0x3,
1367 &subword2 );
1368 if( status == LM_STATUS_FAILURE )
1369 {
1370 return status;
1371 }
1372 }
1373
1374 /* Enable EEPROM write. */
1375 if( pDevice->Flags & EEPROM_WP_FLAG )
1376 {
1377 REG_WR( pDevice, Grc.LocalCtrl,
1378 pDevice->GrcLocalCtrl | GRC_MISC_LOCAL_CTRL_GPIO_OE1 );
1379 REG_RD_BACK( pDevice, Grc.LocalCtrl );
1380 MM_Wait(40);
1381
1382 value32 = REG_RD( pDevice, Grc.LocalCtrl );
1383 if( value32 & GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 )
1384 {
1385 return LM_STATUS_FAILURE;
1386 }
1387 }
1388
1389 while( size > 0 )
1390 {
1391 value32 = offset & 0x3;
1392 if( value32 )
1393 {
1394 /*
1395 * We have to read / modify / write the data to
1396 * preserve the flash contents preceding the offset.
1397 */
1398 offset &= ~0x3;
1399
1400 dstptr = ((LM_UINT8 *)(&value32)) + value32;
1401 bytecnt = sizeof(LM_UINT32) - value32;
1402 value32 = subword1;
1403 }
1404 else if( size < sizeof(LM_UINT32) )
1405 {
1406 dstptr = (LM_UINT8 *)(&value32);
1407 bytecnt = size;
1408 value32 = subword2;
1409 }
1410 else
1411 {
1412 dstptr = (LM_UINT8 *)(&value32);
1413 bytecnt = sizeof(LM_UINT32);
1414 }
1415
1416 if( size < bytecnt )
1417 {
1418 bytecnt = size;
1419 }
1420
1421 memcpy( dstptr, (void *)data, bytecnt );
1422
1423 data += bytecnt;
1424 size -= bytecnt;
1425
1426 /*
1427 * Swap the data so that the byte stream will be
1428 * written the same in little and big endian systems.
1429 */
1430 value32 = MM_SWAP_LE32(value32);
1431
1432 /* Set the write value to the eeprom */
1433 REG_WR( pDevice, Grc.EepromData, value32 );
1434
1435 Dev = offset / pDevice->flashinfo.chipsize;
1436 Addr = offset % pDevice->flashinfo.chipsize;
1437
1438 value32 = REG_RD( pDevice, Grc.EepromAddr );
1439 value32 &= ~(SEEPROM_ADDR_DEV_ID_MASK | SEEPROM_ADDR_ADDRESS_MASK |
1440 SEEPROM_ADDR_RW_MASK);
1441 value32 |= SEEPROM_ADDR_DEV_ID(Dev) | SEEPROM_ADDR_ADDRESS(Addr) |
1442 SEEPROM_ADDR_START | SEEPROM_ADDR_WRITE;
1443
1444 status = LM_EEPROM_ExecuteCommand( pDevice, value32 );
1445 if( status != LM_STATUS_SUCCESS )
1446 {
1447 break;
1448 }
1449
1450 offset += sizeof(LM_UINT32);
1451 }
1452
1453 /* Write-protect EEPROM. */
1454 if( pDevice->Flags & EEPROM_WP_FLAG )
1455 {
1456 REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
1457 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
1458 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
1459 REG_RD_BACK(pDevice, Grc.LocalCtrl);
1460 MM_Wait(40);
1461 }
1462
1463 return status;
1464 } /* LM_EEPROM_WriteBlock */
1465
1466
1467
1468 /******************************************************************************/
1469 /* Description: */
1470 /* */
1471 /* Return: */
1472 /******************************************************************************/
1473 STATIC LM_STATUS
1474 LM_NVRAM_WriteBlockUnBuffered( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1475 LM_UINT8 * data, LM_UINT32 size )
1476 {
1477 LM_UINT i;
1478 LM_STATUS status;
1479 LM_UINT32 tgtoff;
1480 LM_UINT32 value32;
1481 LM_UINT32 ctrlreg;
1482 LM_UINT32 pagesize;
1483 LM_UINT32 pagemask;
1484 LM_UINT32 physaddr;
1485
1486 /* Cache the pagesize. */
1487 pagesize = pDevice->flashinfo.pagesize;
1488
1489 if( pDevice->flashinfo.jedecnum == JEDEC_SAIFUN )
1490 {
1491 /* Config2 = 0x500d8 */
1492 /* Config3 = 0x3840253 */
1493 /* Write1 = 0xaf000400 */
1494
1495 /* Configure the erase command to be "page erase". */
1496 /* Configure the status command to be "read status register". */
1497 value32 = REG_RD( pDevice, Nvram.Config2 );
1498 value32 &= ~(NVRAM_STATUS_COMMAND( NVRAM_COMMAND_MASK ) |
1499 NVRAM_ERASE_COMMAND( NVRAM_COMMAND_MASK ));
1500 value32 |= NVRAM_STATUS_COMMAND( SAIFUN_SA25F0XX_READ_STATUS_CMD ) |
1501 NVRAM_ERASE_COMMAND( SAIFUN_SA25F0XX_PAGE_ERASE_CMD );
1502 REG_WR( pDevice, Nvram.Config2, value32 );
1503
1504 /* Configure the write command to be "page write". */
1505 value32 = REG_RD( pDevice, Nvram.Config3 );
1506 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1507 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( SAIFUN_SA25F0XX_PAGE_WRITE_CMD );
1508 REG_WR( pDevice, Nvram.Config3, value32 );
1509
1510 /* Make sure the "write enable" command is correct. */
1511 value32 = REG_RD( pDevice, Nvram.Write1 );
1512 value32 &= ~NVRAM_WRITE1_WRENA_CMD( NVRAM_COMMAND_MASK );
1513 value32 |= NVRAM_WRITE1_WRENA_CMD( SAIFUN_SA25F0XX_WRENA_CMD );
1514 REG_WR( pDevice, Nvram.Write1, value32 );
1515
1516 pagemask = SAIFUN_SA25F0XX_PAGE_MASK;
1517 }
1518 else
1519 {
1520 /* Unsupported flash type */
1521 return LM_STATUS_FAILURE;
1522 }
1523
1524 if( size == 0 )
1525 {
1526 status = LM_STATUS_SUCCESS;
1527 goto done;
1528 }
1529
1530 while( size > 0 )
1531 {
1532 /* Align the offset to a page boundary. */
1533 physaddr = offset & ~pagemask;
1534
1535 status = LM_NVRAM_ReadBlock( pDevice, physaddr,
1536 pDevice->flashbuffer,
1537 pagesize );
1538 if( status == LM_STATUS_FAILURE )
1539 {
1540 break;
1541 }
1542
1543 /* Calculate the target index. */
1544 tgtoff = offset & pagemask;
1545
1546 /* Copy the new data into the save buffer. */
1547 for( i = tgtoff; i < pagesize && size > 0; i++ )
1548 {
1549 pDevice->flashbuffer[i] = *data++;
1550 size--;
1551 }
1552
1553 /* Move the offset to the next page. */
1554 offset = offset + (pagesize - tgtoff);
1555
1556 /*
1557 * The LM_NVRAM_ReadBlock() function releases
1558 * the access enable bit. Reacquire it.
1559 */
1560 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1561 REG_WR(pDevice, Nvram.NvmAccess, NVRAM_ACCESS_ENABLE);
1562
1563
1564 /*
1565 * Before we can erase the flash page, we need
1566 * to issue a special "write enable" command.
1567 */
1568 ctrlreg = NVRAM_CMD_WRITE_ENABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1569
1570 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1571 if( status == LM_STATUS_FAILURE )
1572 {
1573 break;
1574 }
1575
1576 /* Erase the target page */
1577 REG_WR(pDevice, Nvram.Addr, physaddr);
1578
1579 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR |
1580 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
1581
1582 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1583 if( status == LM_STATUS_FAILURE )
1584 {
1585 break;
1586 }
1587
1588 /* Issue another write enable to start the write. */
1589 ctrlreg = NVRAM_CMD_WRITE_ENABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1590
1591 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1592 if( status == LM_STATUS_FAILURE )
1593 {
1594 break;
1595 }
1596
1597 /* Copy the data into our NIC's buffers. */
1598 for( i = 0; i < pagesize; i+= 4 )
1599 {
1600 value32 = *((LM_UINT32 *)(&pDevice->flashbuffer[i]));
1601 value32 = MM_SWAP_BE32( value32 );
1602
1603 /* Write the location we wish to write to. */
1604 REG_WR( pDevice, Nvram.Addr, physaddr );
1605
1606 /* Write the data we wish to write. */
1607 REG_WR( pDevice, Nvram.WriteData, value32 );
1608
1609 ctrlreg = NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR;
1610
1611 if( i == 0 )
1612 {
1613 ctrlreg |= NVRAM_CMD_FIRST;
1614 }
1615 else if( i == (pagesize - 4) )
1616 {
1617 ctrlreg |= NVRAM_CMD_LAST;
1618 }
1619
1620 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1621 if( status == LM_STATUS_FAILURE )
1622 {
1623 size = 0;
1624 break;
1625 }
1626
1627 physaddr += sizeof(LM_UINT32);
1628 }
1629 }
1630
1631 /* Paranoia. Turn off the "write enable" flag. */
1632 ctrlreg = NVRAM_CMD_WRITE_DISABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1633
1634 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1635
1636 done:
1637
1638 return status;
1639 } /* LM_NVRAM_WriteBlockUnBuffered */
1640
1641
1642
1643 /******************************************************************************/
1644 /* Description: */
1645 /* */
1646 /* Return: */
1647 /******************************************************************************/
1648 STATIC LM_STATUS
1649 LM_NVRAM_WriteBlockBuffered( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1650 LM_UINT8 * data, LM_UINT32 size )
1651 {
1652 LM_STATUS status;
1653 LM_UINT32 value32;
1654 LM_UINT32 bytecnt;
1655 LM_UINT32 ctrlreg;
1656 LM_UINT32 pageoff;
1657 LM_UINT32 physaddr;
1658 LM_UINT32 subword1;
1659 LM_UINT32 subword2;
1660 LM_UINT8 * dstptr;
1661
1662 if(T3_ASIC_5752(pDevice->ChipRevId) &&
1663 (pDevice->flashinfo.jedecnum == JEDEC_ST ||
1664 pDevice->flashinfo.jedecnum == JEDEC_ATMEL ))
1665 {
1666 /* Do nothing as the 5752 does will take care of it */
1667 }
1668 else if( pDevice->flashinfo.jedecnum == JEDEC_ST )
1669 {
1670 /*
1671 * Program our chip to look at bit0 of the NVRAM's status
1672 * register when polling the write or erase operation status.
1673 */
1674 value32 = REG_RD(pDevice, Nvram.Config1);
1675 value32 &= ~FLASH_STATUS_BITS_MASK;
1676 REG_WR( pDevice, Nvram.Config1, value32 );
1677
1678 /* Program the "read status" and "page erase" commands. */
1679 value32 = NVRAM_STATUS_COMMAND( ST_M45PEX0_READ_STATUS_CMD ) |
1680 NVRAM_ERASE_COMMAND( ST_M45PEX0_PAGE_ERASE_CMD );
1681 REG_WR( pDevice, Nvram.Config2, value32 );
1682
1683 /* Set the write command to be "page program". */
1684 value32 = REG_RD(pDevice, Nvram.Config3); /* default = 0x03840a53 */
1685 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1686 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( ST_M45PEX0_PAGE_PRGM_CMD );
1687 REG_WR( pDevice, Nvram.Config3, value32 );
1688
1689 /* Set the "write enable" and "write disable" commands. */
1690 value32 = NVRAM_WRITE1_WRENA_CMD( ST_M45PEX0_WRENA_CMD ) |
1691 NVRAM_WRITE1_WRDIS_CMD( ST_M45PEX0_WRDIS_CMD );
1692 REG_WR( pDevice, Nvram.Write1, value32 );
1693 }
1694 else if( pDevice->flashinfo.jedecnum == JEDEC_ATMEL )
1695 {
1696 if( pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1697 {
1698 #if 0
1699 Config1 = 0x2008200
1700 Config2 = 0x9f0081
1701 Config3 = 0xa184a053
1702 Write1 = 0xaf000400
1703 #endif
1704 }
1705 else if( pDevice->flashinfo.buffered == TRUE )
1706 {
1707 /*
1708 * Program our chip to look at bit7 of the NVRAM's status
1709 * register when polling the write operation status.
1710 */
1711 value32 = REG_RD(pDevice, Nvram.Config1);
1712 value32 |= FLASH_STATUS_BITS_MASK;
1713 REG_WR( pDevice, Nvram.Config1, value32 );
1714
1715 /* Set the write command to be "page program". */
1716 value32 = REG_RD(pDevice, Nvram.Config3); /* default = 0x03840a53 */
1717 value32 &= ~NVRAM_WRITE_UNBUFFERED_COMMAND( NVRAM_COMMAND_MASK );
1718 value32 |= NVRAM_WRITE_UNBUFFERED_COMMAND( ATMEL_AT45DB0X1B_BUFFER_WRITE_CMD );
1719 REG_WR( pDevice, Nvram.Config3, value32 );
1720 /* Config1 = 0x2008273 */
1721 /* Config2 = 0x00570081 */
1722 /* Config3 = 0x68848353 */
1723 }
1724 else
1725 {
1726 /* NVRAM type unsupported. */
1727 return LM_STATUS_FAILURE;
1728 }
1729 }
1730 else
1731 {
1732 /* NVRAM type unsupported. */
1733 return LM_STATUS_FAILURE;
1734 }
1735
1736 status = LM_STATUS_SUCCESS;
1737
1738 if( offset & 0x3 )
1739 {
1740 /*
1741 * If our initial offset does not fall on a word boundary, we
1742 * have to do a read / modify / write to preserve the
1743 * preceding bits we are not interested in.
1744 */
1745 status = LM_NVRAM_ReadBlock( pDevice, offset & ~0x3,
1746 (LM_UINT8 *)&subword1,
1747 sizeof(subword1) );
1748 if( status == LM_STATUS_FAILURE )
1749 {
1750 return status;
1751 }
1752 }
1753
1754 if( (offset + size) & 0x3 )
1755 {
1756 /*
1757 * Likewise, if our ending offset does not fall on a word
1758 * boundary, we have to do a read / modify / write to
1759 * preserve the trailing bits we are not interested in.
1760 */
1761 status = LM_NVRAM_ReadBlock( pDevice, (offset + size) & ~0x3,
1762 (LM_UINT8 *)&subword2,
1763 sizeof(subword2) );
1764 if( status == LM_STATUS_FAILURE )
1765 {
1766 return status;
1767 }
1768 }
1769
1770 ctrlreg = NVRAM_CMD_FIRST;
1771
1772 while( size > 0 )
1773 {
1774 value32 = offset & 0x3;
1775 if( value32 )
1776 {
1777 /*
1778 * We have to read / modify / write the data to
1779 * preserve the flash contents preceding the offset.
1780 */
1781 offset &= ~0x3;
1782
1783 dstptr = ((LM_UINT8 *)(&value32)) + value32;
1784 bytecnt = sizeof(LM_UINT32) - value32;
1785 value32 = subword1;
1786 }
1787 else if( size < sizeof(LM_UINT32) )
1788 {
1789 dstptr = (LM_UINT8 *)(&value32);
1790 bytecnt = size;
1791 value32 = subword2;
1792 }
1793 else
1794 {
1795 dstptr = (LM_UINT8 *)(&value32);
1796 bytecnt = sizeof(LM_UINT32);
1797 }
1798
1799 if( size < bytecnt )
1800 {
1801 bytecnt = size;
1802 }
1803
1804 memcpy( dstptr, (void *)data, bytecnt );
1805
1806 data += bytecnt;
1807 size -= bytecnt;
1808
1809 /*
1810 * Swap the data so that the byte stream will be
1811 * written the same in little and big endian systems.
1812 */
1813 value32 = MM_SWAP_BE32(value32);
1814
1815 /* Set the desired write data value to the flash. */
1816 REG_WR(pDevice, Nvram.WriteData, value32);
1817
1818 pageoff = offset % pDevice->flashinfo.pagesize;
1819
1820 /* Set the target address. */
1821 if( pDevice->flashinfo.jedecnum == JEDEC_ATMEL &&
1822 pDevice->flashinfo.romtype == ROM_TYPE_FLASH )
1823 {
1824 /*
1825 * If we're dealing with the special ATMEL part, we need to
1826 * convert the submitted offset before it can be considered
1827 * a physical address.
1828 */
1829 LM_UINT32 pagenmbr;
1830
1831 pagenmbr = offset / pDevice->flashinfo.pagesize;
1832 pagenmbr = pagenmbr << ATMEL_AT45DB0X1B_PAGE_POS;
1833
1834 physaddr = pagenmbr + pageoff;
1835 }
1836 else
1837 {
1838 physaddr = offset;
1839 }
1840
1841 REG_WR(pDevice, Nvram.Addr, physaddr);
1842
1843 ctrlreg |= (NVRAM_CMD_DO_IT | NVRAM_CMD_DONE | NVRAM_CMD_WR);
1844
1845 if( pageoff == 0 )
1846 {
1847 /* Set CMD_FIRST when we are at the beginning of a page. */
1848 ctrlreg |= NVRAM_CMD_FIRST;
1849 }
1850 else if( pageoff == (pDevice->flashinfo.pagesize - 4) )
1851 {
1852 /*
1853 * Enable the write to the current page
1854 * before moving on to the next one.
1855 */
1856 ctrlreg |= NVRAM_CMD_LAST;
1857 }
1858
1859 if( size == 0 )
1860 {
1861 ctrlreg |= NVRAM_CMD_LAST;
1862 }
1863
1864 if( pDevice->flashinfo.jedecnum == JEDEC_ST &&
1865 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750) ||
1866 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5714)) &&
1867 (ctrlreg & NVRAM_CMD_FIRST) )
1868 {
1869 LM_UINT32 wrencmd;
1870
1871 REG_WR(pDevice, Nvram.Write1, ST_M45PEX0_WRENA_CMD);
1872
1873 /* We need to issue a special "write enable" command first. */
1874 wrencmd = NVRAM_CMD_WRITE_ENABLE | NVRAM_CMD_DO_IT | NVRAM_CMD_DONE;
1875
1876 status = LM_NVRAM_ExecuteCommand( pDevice, wrencmd );
1877 if( status == LM_STATUS_FAILURE )
1878 {
1879 return status;
1880 }
1881 }
1882
1883 if( pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1884 {
1885 /* We always do complete word writes to eeprom. */
1886 ctrlreg |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
1887 }
1888
1889 status = LM_NVRAM_ExecuteCommand( pDevice, ctrlreg );
1890 if( status == LM_STATUS_FAILURE )
1891 {
1892 break;
1893 }
1894
1895 offset += sizeof(LM_UINT32);
1896 ctrlreg = 0;
1897 }
1898
1899 return status;
1900 } /* LM_NVRAM_WriteBlockBuffered */
1901
1902
1903
1904 /******************************************************************************/
1905 /* Description: */
1906 /* */
1907 /* Return: */
1908 /******************************************************************************/
1909 LM_STATUS LM_NVRAM_WriteBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
1910 LM_UINT8 * data, LM_UINT32 size )
1911 {
1912 LM_UINT32 value32;
1913 LM_STATUS status;
1914
1915 if( offset > pDevice->flashinfo.chipsize ||
1916 (offset + size) > pDevice->flashinfo.chipsize )
1917 {
1918 return LM_STATUS_FAILURE;
1919 }
1920
1921 if( size == 0 )
1922 {
1923 return LM_STATUS_SUCCESS;
1924 }
1925
1926 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
1927 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 )
1928 {
1929 status = LM_EEPROM_WriteBlock( pDevice, offset, data, size );
1930 }
1931 else
1932 {
1933 status = LM_NVRAM_AcquireLock( pDevice );
1934 if( status == LM_STATUS_FAILURE )
1935 {
1936 return status;
1937 }
1938
1939 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1940 {
1941 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1942 {
1943 value32 = REG_RD( pDevice, Nvram.NvmAccess );
1944 value32 |= (NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
1945 REG_WR( pDevice, Nvram.NvmAccess, value32 );
1946 }
1947 }
1948
1949 /* Enable EEPROM write. */
1950 if( pDevice->Flags & EEPROM_WP_FLAG )
1951 {
1952 REG_WR(pDevice, Grc.LocalCtrl,
1953 pDevice->GrcLocalCtrl | GRC_MISC_LOCAL_CTRL_GPIO_OE1);
1954 REG_RD_BACK(pDevice, Grc.LocalCtrl);
1955 MM_Wait(40);
1956
1957 value32 = REG_RD(pDevice, Grc.LocalCtrl);
1958 if( value32 & GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 )
1959 {
1960 status = LM_STATUS_FAILURE;
1961 goto error;
1962 }
1963 }
1964
1965 value32 = REG_RD(pDevice, Grc.Mode);
1966 value32 |= GRC_MODE_NVRAM_WRITE_ENABLE;
1967 REG_WR(pDevice, Grc.Mode, value32);
1968
1969 if( pDevice->flashinfo.buffered == TRUE ||
1970 pDevice->flashinfo.romtype == ROM_TYPE_EEPROM )
1971 {
1972 status = LM_NVRAM_WriteBlockBuffered(pDevice, offset, data, size);
1973 }
1974 else
1975 {
1976 status = LM_NVRAM_WriteBlockUnBuffered(pDevice, offset, data, size);
1977 }
1978
1979 value32 = REG_RD(pDevice, Grc.Mode);
1980 value32 &= ~GRC_MODE_NVRAM_WRITE_ENABLE;
1981 REG_WR(pDevice, Grc.Mode, value32);
1982
1983 if( pDevice->Flags & EEPROM_WP_FLAG )
1984 {
1985 REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
1986 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
1987 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
1988 REG_RD_BACK(pDevice, Grc.LocalCtrl);
1989 MM_Wait(40);
1990 }
1991
1992 error:
1993
1994 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
1995 {
1996 if( (pDevice->Flags & PROTECTED_NVRAM_FLAG) == 0)
1997 {
1998 value32 = REG_RD(pDevice, Nvram.NvmAccess);
1999 value32 &= ~(NVRAM_ACCESS_ENABLE | NVRAM_ACCESS_WRITE_ENABLE);
2000 REG_WR(pDevice, Nvram.NvmAccess, value32);
2001 }
2002 }
2003
2004 LM_NVRAM_ReleaseLock( pDevice );
2005 }
2006
2007 return status;
2008 } /* LM_NVRAM_WriteBlock */
2009
2010
2011 LM_STATUS LM_NvramWriteBlock( PLM_DEVICE_BLOCK pDevice, LM_UINT32 offset,
2012 LM_UINT32 * data, LM_UINT32 size )
2013 {
2014 /* BCM4785: Avoid all access to NVRAM & EEPROM. */
2015 if (pDevice->Flags & SB_CORE_FLAG)
2016 return LM_STATUS_FAILURE;
2017
2018 return LM_NVRAM_WriteBlock( pDevice, offset, (LM_UINT8 *)data, size * 4 );
2019 }
2020
2021 #endif /* ETHTOOL_SEEPROM */
2022
2023
2024 STATIC void
2025 LM_ReadVPD(PLM_DEVICE_BLOCK pDevice)
2026 {
2027 #ifdef BCM_PROC_FS
2028 LM_UINT32 Vpd_arr[256/4];
2029 LM_UINT8 *Vpd = (LM_UINT8 *) &Vpd_arr[0];
2030 LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
2031 LM_UINT32 Value32;
2032 unsigned int j;
2033
2034 /* Read PN from VPD */
2035 for (j = 0; j < 256; j += 4, Vpd_dptr++ )
2036 {
2037 if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) {
2038 B57_ERR(("VPD read failed\n"));
2039 return;
2040 }
2041 *Vpd_dptr = Value32;
2042 }
2043 for (j = 0; j < 256; )
2044 {
2045 unsigned int Vpd_r_len;
2046 unsigned int Vpd_r_end;
2047
2048 if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91))
2049 {
2050 j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
2051 }
2052 else if (Vpd[j] == 0x90)
2053 {
2054 Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8);
2055 j += 3;
2056 Vpd_r_end = Vpd_r_len + j;
2057 while (j < Vpd_r_end)
2058 {
2059 if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N'))
2060 {
2061 unsigned int len = Vpd[j + 2];
2062
2063 if (len <= 24)
2064 {
2065 memcpy(pDevice->PartNo, &Vpd[j + 3], len);
2066 }
2067 break;
2068 }
2069 else
2070 {
2071 if (Vpd[j + 2] == 0)
2072 {
2073 break;
2074 }
2075 j = j + Vpd[j + 2];
2076 }
2077 }
2078 break;
2079 }
2080 else {
2081 break;
2082 }
2083 }
2084 #endif
2085 }
2086
2087 STATIC void
2088 LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice)
2089 {
2090 #ifdef BCM_PROC_FS
2091 LM_UINT32 Value32, offset, ver_offset, start_addr;
2092 int i;
2093
2094 if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)
2095 return;
2096 Value32 = MM_SWAP_BE32(Value32);
2097 if (Value32 != 0x669955aa)
2098 return;
2099 if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
2100 return;
2101
2102 offset = MM_SWAP_BE32(offset);
2103
2104 if( (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
2105 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) &&
2106 pDevice->flashinfo.jedecnum == JEDEC_ATMEL &&
2107 pDevice->flashinfo.buffered == TRUE )
2108 {
2109 LM_UINT32 highaddr;
2110
2111 highaddr = offset >> ATMEL_AT45DB0X1B_PAGE_POS;
2112 highaddr = highaddr * ATMEL_AT45DB0X1B_PAGE_SIZE;
2113
2114 offset = highaddr + (offset & ATMEL_AT45DB0X1B_PAGE_MASK);
2115 }
2116 if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
2117 return;
2118
2119 Value32 = MM_SWAP_BE32(Value32);
2120 Value32 &= 0xfc000000;
2121 if ((Value32 == 0x0c000000) &&
2122 (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) &&
2123 (Value32 == 0)) {
2124
2125 if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS)
2126 return;
2127 if (LM_NvramRead(pDevice, 4, &start_addr) != LM_STATUS_SUCCESS)
2128 return;
2129 ver_offset = MM_SWAP_BE32(ver_offset);
2130 start_addr = MM_SWAP_BE32(start_addr);
2131 offset += ver_offset - start_addr;
2132 for (i = 0; i < 16; i += 4) {
2133 if (LM_NvramRead(pDevice, offset + i, &Value32) !=
2134 LM_STATUS_SUCCESS)
2135 {
2136 return;
2137 }
2138 memcpy(&(pDevice->BootCodeVer[i]), &Value32, sizeof(Value32));
2139 }
2140 }
2141 else {
2142 char c;
2143
2144 if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
2145 return;
2146
2147 Value32 = MM_SWAP_BE32(Value32);
2148 i = 0;
2149 c = ((Value32 & 0xff00) >> 8);
2150
2151 if (c < 10) {
2152 pDevice->BootCodeVer[i++] = c + '0';
2153 }
2154 else {
2155 pDevice->BootCodeVer[i++] = (c / 10) + '0';
2156 pDevice->BootCodeVer[i++] = (c % 10) + '0';
2157 }
2158 pDevice->BootCodeVer[i++] = '.';
2159 c = Value32 & 0xff;
2160 if (c < 10) {
2161 pDevice->BootCodeVer[i++] = '0';
2162 pDevice->BootCodeVer[i++] = c + '0';
2163 }
2164 else {
2165 pDevice->BootCodeVer[i++] = (c / 10) + '0';
2166 pDevice->BootCodeVer[i++] = (c % 10) + '0';
2167 }
2168 pDevice->BootCodeVer[i] = 0;
2169 }
2170 #endif
2171 }
2172
2173 STATIC void
2174 LM_ReadIPMICodeVersion(PLM_DEVICE_BLOCK pDevice)
2175 {
2176 #ifdef BCM_PROC_FS
2177 static char * present = "BRCM ASF present";
2178 LM_UINT32 sig1, sig2;
2179 LM_UINT32 value32, offset, asf_offset, ver_offset, start_addr;
2180 int i;
2181
2182 if (LM_NvramRead(pDevice, 0x0, &value32) != LM_STATUS_SUCCESS)
2183 return;
2184 value32 = MM_SWAP_BE32(value32);
2185 if (value32 != 0x669955aa)
2186 return;
2187
2188 offset = 0x14 + 4;
2189 for (i = 0; i < 8; i++) {
2190 if (LM_NvramRead(pDevice, offset, &value32) != LM_STATUS_SUCCESS)
2191 return;
2192 value32 = MM_SWAP_BE32(value32) & 0xff000000;
2193 if (value32 == 0x1000000)
2194 break;
2195 offset += 12;
2196 }
2197
2198 if (i == 8)
2199 return;
2200
2201 if (LM_NvramRead(pDevice, 0x14 + i * 12, &start_addr) != LM_STATUS_SUCCESS)
2202 return;
2203
2204 start_addr = MM_SWAP_BE32(start_addr);
2205
2206 if (start_addr == 0xc0034000)
2207 start_addr = 0x08000000;
2208
2209 if (LM_NvramRead(pDevice, 0x14 + i * 12 + 8, &asf_offset) != LM_STATUS_SUCCESS)
2210 return;
2211
2212 asf_offset = MM_SWAP_BE32(asf_offset);
2213
2214 if (LM_NvramRead(pDevice, asf_offset, &sig1) != LM_STATUS_SUCCESS ||
2215 LM_NvramRead(pDevice, asf_offset + 4, &sig2) != LM_STATUS_SUCCESS )
2216 return;
2217
2218 sig1 = MM_SWAP_BE32(sig1);
2219
2220 if ((sig1 & 0xfc000000) != 0x0c000000 || sig2 != 0 ) {
2221 memcpy(pDevice->IPMICodeVer, present, 17);
2222 return;
2223 }
2224
2225 if (LM_NvramRead(pDevice, asf_offset + 8, &ver_offset) != LM_STATUS_SUCCESS)
2226 return;
2227
2228 ver_offset = MM_SWAP_BE32(ver_offset);
2229
2230 ver_offset -= start_addr;
2231 ver_offset += asf_offset;
2232
2233 for (i = 0; i < 16; i += 4) {
2234 if (LM_NvramRead(pDevice, ver_offset + i, &value32) != LM_STATUS_SUCCESS)
2235 return;
2236 memcpy(&(pDevice->IPMICodeVer[i]), &value32, sizeof(value32));
2237 }
2238 #endif
2239 }
2240
2241 STATIC void
2242 LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice)
2243 {
2244 #ifdef BCM_PROC_FS
2245 LM_UINT32 PciState = pDevice->PciState;
2246 LM_UINT32 ClockCtrl;
2247 char *SpeedStr = "";
2248
2249 if (pDevice->Flags & PCI_EXPRESS_FLAG)
2250 {
2251 strcpy(pDevice->BusSpeedStr, "PCI Express");
2252 return;
2253 }
2254 if (PciState & T3_PCI_STATE_32BIT_PCI_BUS)
2255 {
2256 strcpy(pDevice->BusSpeedStr, "32-bit ");
2257 }
2258 else
2259 {
2260 strcpy(pDevice->BusSpeedStr, "64-bit ");
2261 }
2262 if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)
2263 {
2264 strcat(pDevice->BusSpeedStr, "PCI ");
2265 if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED)
2266 {
2267 SpeedStr = "66MHz";
2268 }
2269 else
2270 {
2271 SpeedStr = "33MHz";
2272 }
2273 }
2274 else
2275 {
2276 strcat(pDevice->BusSpeedStr, "PCIX ");
2277
2278 // Theses devices have internal PCI-X buses. The driver
2279 // is unable to use the ClockCtrl register to determine the
2280 // bus speed, so we just hardcode the bus speed to 133MHz.
2281
2282 if ( ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) &&
2283 (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) ||
2284 (T3_ASIC_5714_FAMILY(pDevice->ChipRevId)))
2285 {
2286 SpeedStr = "133MHz";
2287 }
2288 else
2289 {
2290 ClockCtrl = pDevice->ClockCtrl & 0x1f;
2291 switch (ClockCtrl)
2292 {
2293 case 0:
2294 SpeedStr = "33MHz";
2295 break;
2296
2297 case 2:
2298 SpeedStr = "50MHz";
2299 break;
2300
2301 case 4:
2302 SpeedStr = "66MHz";
2303 break;
2304
2305 case 6:
2306 SpeedStr = "100MHz";
2307 break;
2308
2309 case 7:
2310 SpeedStr = "133MHz";
2311 break;
2312 }
2313 }
2314 }
2315 strcat(pDevice->BusSpeedStr, SpeedStr);
2316 #endif
2317 }
2318
2319 /******************************************************************************/
2320 /* Description: */
2321 /* This routine initializes default parameters and reads the PCI */
2322 /* configurations. */
2323 /* */
2324 /* Return: */
2325 /* LM_STATUS_SUCCESS */
2326 /******************************************************************************/
2327 LM_STATUS
2328 LM_GetAdapterInfo(
2329 PLM_DEVICE_BLOCK pDevice)
2330 {
2331 PLM_ADAPTER_INFO pAdapterInfo;
2332 LM_UINT32 Value32, LedCfg, Ver;
2333 LM_STATUS Status;
2334 LM_UINT32 EeSigFound;
2335 LM_UINT32 EePhyTypeSerdes = 0;
2336 LM_UINT32 EePhyId = 0;
2337
2338 /* Get Device Id and Vendor Id */
2339 Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32);
2340 if(Status != LM_STATUS_SUCCESS)
2341 {
2342 return Status;
2343 }
2344 pDevice->PciVendorId = (LM_UINT16) Value32;
2345 pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
2346
2347 Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32);
2348 if(Status != LM_STATUS_SUCCESS)
2349 {
2350 return Status;
2351 }
2352 pDevice->PciRevId = (LM_UINT8) Value32;
2353
2354 /* Get chip revision id. */
2355 Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
2356 pDevice->ChipRevId = Value32 >> 16;
2357
2358 /* determine if it is PCIE system */
2359 if( (Value32 = MM_FindCapability(pDevice, T3_PCIE_CAPABILITY_ID)) != 0)
2360 {
2361 pDevice->Flags |= PCI_EXPRESS_FLAG;
2362 }
2363
2364 /* Get subsystem vendor. */
2365 Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
2366 if(Status != LM_STATUS_SUCCESS)
2367 {
2368 return Status;
2369 }
2370 pDevice->SubsystemVendorId = (LM_UINT16) Value32;
2371
2372 /* Get PCI subsystem id. */
2373 pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);
2374
2375 /* Read bond id for baxter A0 since it has same rev id as hamilton A0*/
2376
2377 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5714_A0) {
2378 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, Value32 | MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS);
2379
2380 Value32 = LM_RegRdInd(pDevice, 0x6804);
2381 Value32 &= GRC_MISC_BD_ID_MASK;
2382
2383 if((Value32 == 0)||(Value32 == 0x8000)) {
2384 pDevice->ChipRevId = T3_CHIP_ID_5752_A0;
2385 }else{
2386 pDevice->ChipRevId = T3_CHIP_ID_5714_A0;
2387 }
2388
2389 Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
2390 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, Value32 & ~ MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS);
2391 }
2392
2393
2394 /* Get the cache line size. */
2395 MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
2396 pDevice->CacheLineSize = (LM_UINT8) Value32;
2397 pDevice->SavedCacheLineReg = Value32;
2398
2399 if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
2400 pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
2401 pDevice->ChipRevId != T3_CHIP_ID_5704_A0)
2402 {
2403 pDevice->Flags &= ~UNDI_FIX_FLAG;
2404 }
2405 #ifndef PCIX_TARGET_WORKAROUND
2406 pDevice->Flags &= ~UNDI_FIX_FLAG;
2407 #endif
2408 /* Map the memory base to system address space. */
2409 if (!(pDevice->Flags & UNDI_FIX_FLAG))
2410 {
2411 Status = MM_MapMemBase(pDevice);
2412 if(Status != LM_STATUS_SUCCESS)
2413 {
2414 return Status;
2415 }
2416 /* Initialize the memory view pointer. */
2417 pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
2418 }
2419
2420 if ((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) ||
2421 (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_AX))
2422 {
2423 pDevice->Flags |= TX_4G_WORKAROUND_FLAG;
2424 }
2425 if ( (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) ||
2426 (pDevice->Flags == PCI_EXPRESS_FLAG))
2427 {
2428 pDevice->Flags |= REG_RD_BACK_FLAG;
2429 }
2430
2431 if(pDevice->ChipRevId==T3_CHIP_ID_5750_A0)
2432 return LM_STATUS_UNKNOWN_ADAPTER;
2433
2434 #ifdef PCIX_TARGET_WORKAROUND
2435 MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
2436 if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)
2437 {
2438 if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
2439 {
2440 pDevice->Flags |= ENABLE_PCIX_FIX_FLAG;
2441 }
2442 }
2443 if (pDevice->Flags & UNDI_FIX_FLAG)
2444 {
2445 pDevice->Flags |= ENABLE_PCIX_FIX_FLAG;
2446 }
2447 #endif
2448 /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
2449 /* management register may be clobbered which may cause the */
2450 /* BCM5700 to go into D3 state. While in this state, we will */
2451 /* need to restore the device to D0 state. */
2452 MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
2453 Value32 |= T3_PM_PME_ASSERTED;
2454 Value32 &= ~T3_PM_POWER_STATE_MASK;
2455 Value32 |= T3_PM_POWER_STATE_D0;
2456 MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
2457
2458 /* read the current PCI command word */
2459 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
2460
2461 /* Make sure bus-mastering is enabled. */
2462 Value32 |= PCI_BUSMASTER_ENABLE;
2463
2464 #ifdef PCIX_TARGET_WORKAROUND
2465 /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
2466 are enabled */
2467 if (pDevice->Flags & ENABLE_PCIX_FIX_FLAG) {
2468 Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
2469 PCI_PARITY_ERROR_ENABLE);
2470 }
2471 if (pDevice->Flags & UNDI_FIX_FLAG)
2472 {
2473 Value32 &= ~PCI_MEM_SPACE_ENABLE;
2474 }
2475
2476 #endif
2477
2478 if (pDevice->Flags & ENABLE_MWI_FLAG)
2479 {
2480 Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
2481 }
2482 else {
2483 Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
2484 }
2485
2486 /* save the value we are going to write into the PCI command word */
2487 pDevice->PciCommandStatusWords = Value32;
2488
2489 Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32);
2490 if(Status != LM_STATUS_SUCCESS)
2491 {
2492 return Status;
2493 }
2494
2495 /* Setup the mode registers. */
2496 pDevice->MiscHostCtrl =
2497 MISC_HOST_CTRL_MASK_PCI_INT |
2498 MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
2499 #ifdef BIG_ENDIAN_HOST
2500 MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
2501 #endif /* BIG_ENDIAN_HOST */
2502 MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
2503 MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
2504 /* write to PCI misc host ctr first in order to enable indirect accesses */
2505 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
2506
2507 /* Set power state to D0. */
2508 LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
2509
2510 /* Preserve HOST_STACK_UP bit in case ASF firmware is running */
2511 Value32 = REG_RD(pDevice, Grc.Mode) & GRC_MODE_HOST_STACK_UP;
2512 #ifdef BIG_ENDIAN_HOST
2513 Value32 |= GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
2514 GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
2515 #else
2516 Value32 |= GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
2517 #endif
2518 REG_WR(pDevice, Grc.Mode, Value32);
2519
2520 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
2521 {
2522 REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
2523 GRC_MISC_LOCAL_CTRL_GPIO_OE1);
2524 REG_RD_BACK(pDevice, Grc.LocalCtrl);
2525 }
2526 MM_Wait(40);
2527
2528 /* Enable memory arbiter*/
2529 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
2530 {
2531 Value32 = REG_RD(pDevice,MemArbiter.Mode);
2532 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE | Value32);
2533 }
2534 else
2535 {
2536 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
2537 }
2538
2539
2540 LM_SwitchClocks(pDevice);
2541
2542 REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
2543
2544 /* Check to see if PXE ran and did not shutdown properly */
2545 if ((REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE) ||
2546 !(REG_RD(pDevice, PciCfg.MiscHostCtrl) & MISC_HOST_CTRL_MASK_PCI_INT))
2547 {
2548 LM_DisableInterrupt(pDevice);
2549 /* assume ASF is enabled */
2550 pDevice->AsfFlags = ASF_ENABLED;
2551 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2552 {
2553 pDevice->AsfFlags |= ASF_NEW_HANDSHAKE;
2554 }
2555 LM_ShutdownChip(pDevice, LM_SHUTDOWN_RESET);
2556 pDevice->AsfFlags = 0;
2557 }
2558 #ifdef PCIX_TARGET_WORKAROUND
2559 MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
2560 if (!(pDevice->Flags & ENABLE_PCIX_FIX_FLAG) &&
2561 ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0))
2562 {
2563 if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
2564 pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
2565 pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
2566 pDevice->ChipRevId == T3_CHIP_ID_5701_B5)
2567 {
2568 MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]), 0);
2569 MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x301]), 0);
2570 MM_MEMWRITEL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x301]),
2571 0xffffffff);
2572 if (MM_MEMREADL(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
2573 {
2574 pDevice->Flags |= ENABLE_PCIX_FIX_FLAG;
2575 }
2576 }
2577 }
2578 #endif
2579
2580 LM_NVRAM_Init(pDevice);
2581
2582 Status = LM_STATUS_FAILURE;
2583
2584 /* BCM4785: Use the MAC address stored in the main flash. */
2585 if (pDevice->Flags & SB_CORE_FLAG) {
2586 bcm_ether_atoe(getvar(NULL, "et0macaddr"), (struct ether_addr *)pDevice->NodeAddress);
2587 Status = LM_STATUS_SUCCESS;
2588 } else {
2589 /* Get the node address. First try to get in from the shared memory. */
2590 /* If the signature is not present, then get it from the NVRAM. */
2591 Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
2592 if((Value32 >> 16) == 0x484b)
2593 {
2594 int i;
2595
2596 pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
2597 pDevice->NodeAddress[1] = (LM_UINT8) Value32;
2598
2599 Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX);
2600
2601 pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
2602 pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
2603 pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
2604 pDevice->NodeAddress[5] = (LM_UINT8) Value32;
2605
2606 /* Check for null MAC address which can happen with older boot code */
2607 for (i = 0; i < 6; i++)
2608 {
2609 if (pDevice->NodeAddress[i] != 0)
2610 {
2611 Status = LM_STATUS_SUCCESS;
2612 break;
2613 }
2614 }
2615 }
2616 }
2617
2618 if (Status != LM_STATUS_SUCCESS)
2619 {
2620 int MacOffset;
2621
2622 MacOffset = 0x7c;
2623 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704 ||
2624 (T3_ASIC_5714_FAMILY(pDevice->ChipRevId)) )
2625 {
2626 if (REG_RD(pDevice, PciCfg.DualMacCtrl) & T3_DUAL_MAC_ID)
2627 {
2628 MacOffset = 0xcc;
2629 }
2630 /* the boot code is not running */
2631 if (LM_NVRAM_AcquireLock(pDevice) != LM_STATUS_SUCCESS)
2632 {
2633 REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RESET);
2634 }
2635 else
2636 {
2637 LM_NVRAM_ReleaseLock(pDevice);
2638 }
2639 }
2640
2641 Status = LM_NvramRead(pDevice, MacOffset, &Value32);
2642 if(Status == LM_STATUS_SUCCESS)
2643 {
2644 LM_UINT8 *c = (LM_UINT8 *) &Value32;
2645
2646 pDevice->NodeAddress[0] = c[2];
2647 pDevice->NodeAddress[1] = c[3];
2648
2649 Status = LM_NvramRead(pDevice, MacOffset + 4, &Value32);
2650
2651 c = (LM_UINT8 *) &Value32;
2652 pDevice->NodeAddress[2] = c[0];
2653 pDevice->NodeAddress[3] = c[1];
2654 pDevice->NodeAddress[4] = c[2];
2655 pDevice->NodeAddress[5] = c[3];
2656 }
2657 }
2658
2659 if(Status != LM_STATUS_SUCCESS)
2660 {
2661 Value32 = REG_RD(pDevice, MacCtrl.MacAddr[0].High);
2662 pDevice->NodeAddress[0] = (Value32 >> 8) & 0xff;
2663 pDevice->NodeAddress[1] = Value32 & 0xff;
2664 Value32 = REG_RD(pDevice, MacCtrl.MacAddr[0].Low);
2665 pDevice->NodeAddress[2] = (Value32 >> 24) & 0xff;
2666 pDevice->NodeAddress[3] = (Value32 >> 16) & 0xff;
2667 pDevice->NodeAddress[4] = (Value32 >> 8) & 0xff;
2668 pDevice->NodeAddress[5] = Value32 & 0xff;
2669 B57_ERR(("WARNING: Cannot get MAC addr from NVRAM, using %2.2x%2.2x%2.2x%2.2x%2.2x%2.2x\n",
2670 pDevice->NodeAddress[0], pDevice->NodeAddress[1],
2671 pDevice->NodeAddress[2], pDevice->NodeAddress[3],
2672 pDevice->NodeAddress[4], pDevice->NodeAddress[5]));
2673 }
2674
2675 memcpy(pDevice->PermanentNodeAddress, pDevice->NodeAddress, 6);
2676
2677 /* Initialize the default values. */
2678 pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
2679 pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
2680 pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
2681 pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
2682 pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
2683 pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
2684 pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
2685 pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
2686 pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
2687 pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
2688 pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
2689 pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
2690 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
2691 pDevice->DisableAutoNeg = FALSE;
2692 pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
2693 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
2694
2695 pDevice->PhyFlags = 0;
2696
2697 if (!(pDevice->Flags & PCI_EXPRESS_FLAG))
2698 pDevice->Flags |= DELAY_PCI_GRANT_FLAG;
2699
2700 pDevice->RequestedLineSpeed = LM_LINE_SPEED_AUTO;
2701 pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
2702 pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
2703 pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
2704 #ifdef INCLUDE_TBI_SUPPORT
2705 pDevice->TbiFlags = 0;
2706 pDevice->IgnoreTbiLinkChange = FALSE;
2707 #endif
2708 #ifdef INCLUDE_TCP_SEG_SUPPORT
2709 pDevice->LargeSendMaxSize = T3_TCP_SEG_MAX_OFFLOAD_SIZE;
2710 pDevice->LargeSendMinNumSeg = T3_TCP_SEG_MIN_NUM_SEG;
2711 #endif
2712
2713 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
2714 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) ||
2715 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705))
2716 {
2717 pDevice->PhyFlags |= PHY_RESET_ON_LINKDOWN;
2718 pDevice->PhyFlags |= PHY_CHECK_TAPS_AFTER_RESET;
2719 }
2720 if ((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5703_AX) ||
2721 (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_AX))
2722 {
2723 pDevice->PhyFlags |= PHY_ADC_FIX;
2724 }
2725 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
2726 {
2727 pDevice->PhyFlags |= PHY_5704_A0_FIX;
2728 }
2729 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
2730 {
2731 pDevice->PhyFlags |= PHY_5705_5750_FIX;
2732 }
2733 /* Ethernet@Wirespeed is supported on 5701,5702,5703,5704,5705a0,5705a1 */
2734 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
2735 !((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) &&
2736 (pDevice->ChipRevId != T3_CHIP_ID_5705_A0) &&
2737 (pDevice->ChipRevId != T3_CHIP_ID_5705_A1)))
2738 {
2739 pDevice->PhyFlags |= PHY_ETHERNET_WIRESPEED;
2740 }
2741
2742 switch (T3_ASIC_REV(pDevice->ChipRevId))
2743 {
2744 case T3_ASIC_REV_5704:
2745 pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
2746 pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
2747 break;
2748 default:
2749 pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
2750 pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
2751 break;
2752 }
2753
2754 pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
2755 pDevice->QueueRxPackets = TRUE;
2756
2757 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2758
2759 if(T3_ASIC_IS_JUMBO_CAPABLE(pDevice->ChipRevId)){
2760 if( ! T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
2761 pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
2762 pDevice->Flags |= JUMBO_CAPABLE_FLAG;
2763 }
2764
2765 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
2766
2767 pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
2768
2769 if(((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) &&
2770 ((pDevice->BondId == 0x10000) || (pDevice->BondId == 0x18000))) ||
2771 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) &&
2772 ((pDevice->BondId == 0x14000) || (pDevice->BondId == 0x1c000))))
2773 {
2774 return LM_STATUS_UNKNOWN_ADAPTER;
2775 }
2776 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
2777 {
2778 if ((pDevice->BondId == 0x8000) || (pDevice->BondId == 0x4000))
2779 {
2780 pDevice->PhyFlags |= PHY_NO_GIGABIT;
2781 }
2782 }
2783 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
2784 {
2785 if ((pDevice->BondId == GRC_MISC_BD_ID_5788) ||
2786 (pDevice->BondId == GRC_MISC_BD_ID_5788M))
2787 {
2788 pDevice->Flags |= BCM5788_FLAG;
2789 }
2790
2791 if ((pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5901)) ||
2792 (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5901A2)) ||
2793 (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5705F)))
2794 {
2795 pDevice->PhyFlags |= PHY_NO_GIGABIT;
2796 }
2797 }
2798
2799 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5750)
2800 {
2801 if ( (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5751F))||
2802 (pDevice->PciDeviceId == T3_PCI_DEVICE_ID(T3_PCI_ID_BCM5753F)))
2803 {
2804 pDevice->PhyFlags |= PHY_NO_GIGABIT;
2805 }
2806 }
2807
2808 /* CIOBE multisplit has a bug */
2809
2810 /* Get Eeprom info. */
2811 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR);
2812 if (Value32 == T3_NIC_DATA_SIG)
2813 {
2814 EeSigFound = TRUE;
2815 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
2816
2817 /* For now the 5753 cannot drive gpio2 or ASF will blow */
2818 if(Value32 & T3_NIC_GPIO2_NOT_AVAILABLE)
2819 {
2820 pDevice->Flags |= GPIO2_DONOT_OUTPUT;
2821 }
2822
2823 if (Value32 & T3_NIC_MINI_PCI)
2824 {
2825 pDevice->Flags |= MINI_PCI_FLAG;
2826 }
2827 /* Determine PHY type. */
2828 switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK)
2829 {
2830 case T3_NIC_CFG_PHY_TYPE_COPPER:
2831 EePhyTypeSerdes = FALSE;
2832 break;
2833
2834 case T3_NIC_CFG_PHY_TYPE_FIBER:
2835 EePhyTypeSerdes = TRUE;
2836 break;
2837
2838 default:
2839 EePhyTypeSerdes = FALSE;
2840 break;
2841 }
2842
2843 if ( T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2844 {
2845 LedCfg = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR2);
2846 LedCfg = LedCfg & (T3_NIC_CFG_LED_MODE_MASK |
2847 T3_SHASTA_EXT_LED_MODE_MASK);
2848 }
2849 else
2850 {
2851 /* Determine PHY led mode. for legacy devices */
2852 LedCfg = Value32 & T3_NIC_CFG_LED_MODE_MASK;
2853 }
2854
2855 switch (LedCfg)
2856 {
2857 default:
2858 case T3_NIC_CFG_LED_PHY_MODE_1:
2859 pDevice->LedCtrl = LED_CTRL_PHY_MODE_1;
2860 break;
2861
2862 case T3_NIC_CFG_LED_PHY_MODE_2:
2863 pDevice->LedCtrl = LED_CTRL_PHY_MODE_2;
2864 break;
2865
2866 case T3_NIC_CFG_LED_MAC_MODE:
2867 pDevice->LedCtrl = LED_CTRL_MAC_MODE;
2868 break;
2869
2870 case T3_SHASTA_EXT_LED_SHARED_TRAFFIC_LINK_MODE:
2871 pDevice->LedCtrl = LED_CTRL_SHARED_TRAFFIC_LINK;
2872 if ((pDevice->ChipRevId != T3_CHIP_ID_5750_A0) &&
2873 (pDevice->ChipRevId != T3_CHIP_ID_5750_A1))
2874 {
2875 pDevice->LedCtrl |= LED_CTRL_PHY_MODE_1 |
2876 LED_CTRL_PHY_MODE_2;
2877 }
2878 break;
2879
2880 case T3_SHASTA_EXT_LED_MAC_MODE:
2881 pDevice->LedCtrl = LED_CTRL_SHASTA_MAC_MODE;
2882 break;
2883
2884 case T3_SHASTA_EXT_LED_WIRELESS_COMBO_MODE:
2885 pDevice->LedCtrl = LED_CTRL_WIRELESS_COMBO;
2886 if (pDevice->ChipRevId != T3_CHIP_ID_5750_A0)
2887 {
2888 pDevice->LedCtrl |= LED_CTRL_PHY_MODE_1 |
2889 LED_CTRL_PHY_MODE_2;
2890 }
2891 break;
2892
2893 }
2894
2895 if (((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
2896 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)) &&
2897 (pDevice->SubsystemVendorId == T3_SVID_DELL))
2898 {
2899 pDevice->LedCtrl = LED_CTRL_PHY_MODE_2;
2900 }
2901
2902 if((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
2903 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) ||
2904 (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId)) )
2905 {
2906 /* Enable EEPROM write protection. */
2907 if(Value32 & T3_NIC_EEPROM_WP)
2908 {
2909 pDevice->Flags |= EEPROM_WP_FLAG;
2910 }
2911 }
2912 pDevice->AsfFlags = 0;
2913 #ifdef BCM_ASF
2914 if (Value32 & T3_NIC_CFG_ENABLE_ASF)
2915 {
2916 pDevice->AsfFlags |= ASF_ENABLED;
2917 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
2918 {
2919 pDevice->AsfFlags |= ASF_NEW_HANDSHAKE;
2920 }
2921 }
2922 #endif
2923 if (Value32 & T3_NIC_FIBER_WOL_CAPABLE)
2924 {
2925 pDevice->Flags |= FIBER_WOL_CAPABLE_FLAG;
2926 }
2927 if (Value32 & T3_NIC_WOL_LIMIT_10)
2928 {
2929 pDevice->Flags |= WOL_LIMIT_10MBPS_FLAG;
2930 }
2931
2932 /* Get the PHY Id. */
2933 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR);
2934 if (Value32)
2935 {
2936 EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
2937 PHY_ID1_OUI_MASK) << 10;
2938
2939 Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
2940
2941 EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
2942 (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
2943 }
2944 else
2945 {
2946 EePhyId = 0;
2947 if (!EePhyTypeSerdes && !(pDevice->AsfFlags & ASF_ENABLED))
2948 {
2949 /* reset PHY if boot code couldn't read the PHY ID */
2950 LM_ResetPhy(pDevice);
2951 }
2952 }
2953
2954 Ver = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_VER);
2955 Ver >>= T3_NIC_DATA_VER_SHIFT;
2956
2957 Value32 = 0;
2958 if((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
2959 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) &&
2960 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703) &&
2961 (Ver > 0) && (Ver < 0x100)){
2962
2963 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR2);
2964
2965 if (Value32 & T3_NIC_CFG_CAPACITIVE_COUPLING)
2966 {
2967 pDevice->PhyFlags |= PHY_CAPACITIVE_COUPLING;
2968 }
2969
2970 if (Value32 & T3_NIC_CFG_PRESERVE_PREEMPHASIS)
2971 {
2972 pDevice->TbiFlags |= TBI_DO_PREEMPHASIS;
2973 }
2974
2975 }
2976
2977 }
2978 else
2979 {
2980 EeSigFound = FALSE;
2981 }
2982
2983 /* Set the PHY address. */
2984 pDevice->PhyAddr = PHY_DEVICE_ID;
2985
2986 /* Disable auto polling. */
2987 pDevice->MiMode = 0xc0000;
2988 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
2989 REG_RD_BACK(pDevice, MacCtrl.MiMode);
2990 MM_Wait(80);
2991
2992 if (pDevice->AsfFlags & ASF_ENABLED)
2993 {
2994 /* Reading PHY registers will contend with ASF */
2995 pDevice->PhyId = 0;
2996 }
2997 else
2998 {
2999 /* Get the PHY id. */
3000 LM_GetPhyId(pDevice);
3001 }
3002
3003 /* Set the EnableTbi flag to false if we have a copper PHY. */
3004 switch(pDevice->PhyId & PHY_ID_MASK)
3005 {
3006 case PHY_BCM5400_PHY_ID:
3007 case PHY_BCM5401_PHY_ID:
3008 case PHY_BCM5411_PHY_ID:
3009 case PHY_BCM5461_PHY_ID:
3010 case PHY_BCM5701_PHY_ID:
3011 case PHY_BCM5703_PHY_ID:
3012 case PHY_BCM5704_PHY_ID:
3013 case PHY_BCM5705_PHY_ID:
3014 case PHY_BCM5750_PHY_ID:
3015 break;
3016 case PHY_BCM5714_PHY_ID:
3017 case PHY_BCM5780_PHY_ID:
3018 if(EePhyTypeSerdes == TRUE)
3019 {
3020 pDevice->PhyFlags |= PHY_IS_FIBER;
3021 }
3022 break;
3023 case PHY_BCM5752_PHY_ID:
3024 break;
3025
3026 case PHY_BCM8002_PHY_ID:
3027 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
3028 break;
3029
3030 default:
3031
3032 if (EeSigFound)
3033 {
3034 pDevice->PhyId = EePhyId;
3035
3036 if (EePhyTypeSerdes && ((pDevice->PhyId == PHY_BCM5780_PHY_ID)) )
3037 {
3038 pDevice->PhyFlags |= PHY_IS_FIBER;
3039 }
3040 else if (EePhyTypeSerdes)
3041 {
3042 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
3043 }
3044 }
3045 else if ((pAdapterInfo = LM_GetAdapterInfoBySsid(
3046 pDevice->SubsystemVendorId,
3047 pDevice->SubsystemId)))
3048 {
3049 pDevice->PhyId = pAdapterInfo->PhyId;
3050 if (pAdapterInfo->Serdes)
3051 {
3052 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
3053 }
3054 }
3055 else
3056 {
3057 if (UNKNOWN_PHY_ID(pDevice->PhyId))
3058 {
3059 LM_ResetPhy(pDevice);
3060 LM_GetPhyId(pDevice);
3061 }
3062 }
3063 break;
3064 }
3065
3066 if(UNKNOWN_PHY_ID(pDevice->PhyId) &&
3067 !(pDevice->TbiFlags & ENABLE_TBI_FLAG))
3068 {
3069 if (pDevice->Flags & ROBO_SWITCH_FLAG) {
3070 B57_ERR(("PHY ID unknown, assume it is a copper PHY.\n"));
3071 } else {
3072 pDevice->TbiFlags |= ENABLE_TBI_FLAG;
3073 B57_ERR(("PHY ID unknown, assume it is SerDes\n"));
3074 }
3075 }
3076
3077 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
3078 {
3079 if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000)
3080 {
3081 pDevice->SavedCacheLineReg &= 0xffff00ff;
3082 pDevice->SavedCacheLineReg |= 0x4000;
3083 }
3084 }
3085
3086 pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
3087 LM_ACCEPT_UNICAST;
3088
3089 pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
3090 LM_TASK_OFFLOAD_TX_UDP_CHECKSUM | LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
3091 LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
3092
3093 if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0)
3094 {
3095 pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
3096 LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
3097 }
3098
3099 #ifdef INCLUDE_TCP_SEG_SUPPORT
3100 pDevice->TaskOffloadCap |= LM_TASK_OFFLOAD_TCP_SEGMENTATION;
3101
3102 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
3103 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) ||
3104 (pDevice->ChipRevId == T3_CHIP_ID_5705_A0))
3105 {
3106 pDevice->TaskOffloadCap &= ~LM_TASK_OFFLOAD_TCP_SEGMENTATION;
3107 }
3108 #endif
3109
3110 #ifdef BCM_ASF
3111 if (pDevice->AsfFlags & ASF_ENABLED)
3112 {
3113 if (!T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
3114 {
3115 pDevice->TaskOffloadCap &= ~LM_TASK_OFFLOAD_TCP_SEGMENTATION;
3116 }
3117 }
3118 #endif
3119
3120 /* Change driver parameters. */
3121 Status = MM_GetConfig(pDevice);
3122 if(Status != LM_STATUS_SUCCESS)
3123 {
3124 return Status;
3125 }
3126
3127 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3128 {
3129 pDevice->Flags &= ~NIC_SEND_BD_FLAG;
3130 }
3131
3132 /* Save the current phy link status. */
3133 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG) &&
3134 !(pDevice->AsfFlags & ASF_ENABLED))
3135 {
3136 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
3137 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
3138
3139 /* If we don't have link reset the PHY. */
3140 if(!(Value32 & PHY_STATUS_LINK_PASS) ||
3141 (pDevice->PhyFlags & PHY_RESET_ON_INIT))
3142 {
3143
3144 LM_ResetPhy(pDevice);
3145
3146 if (LM_PhyAdvertiseAll(pDevice) != LM_STATUS_SUCCESS)
3147 {
3148 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
3149 PHY_AN_AD_ALL_SPEEDS;
3150 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
3151 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
3152
3153 if(!(pDevice->PhyFlags & PHY_NO_GIGABIT))
3154 Value32 = BCM540X_AN_AD_ALL_1G_SPEEDS ;
3155 else
3156 Value32 =0;
3157
3158 #ifdef INCLUDE_5701_AX_FIX
3159 if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
3160 pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
3161 {
3162 Value32 |= BCM540X_CONFIG_AS_MASTER |
3163 BCM540X_ENABLE_CONFIG_AS_MASTER;
3164 }
3165 #endif
3166 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
3167
3168 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
3169 PHY_CTRL_RESTART_AUTO_NEG);
3170 }
3171
3172 }
3173 LM_SetEthWireSpeed(pDevice);
3174
3175 LM_ReadPhy(pDevice, PHY_AN_AD_REG, &pDevice->advertising);
3176 LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG,
3177 &pDevice->advertising1000);
3178
3179 }
3180 /* Currently 5401 phy only */
3181 LM_PhyTapPowerMgmt(pDevice);
3182
3183 #ifdef INCLUDE_TBI_SUPPORT
3184 if(pDevice->TbiFlags & ENABLE_TBI_FLAG)
3185 {
3186 if (!(pDevice->Flags & FIBER_WOL_CAPABLE_FLAG))
3187 {
3188 pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
3189 }
3190 pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
3191 if (pDevice->TbiFlags & TBI_PURE_POLLING_FLAG)
3192 {
3193 pDevice->IgnoreTbiLinkChange = TRUE;
3194 }
3195 }
3196 else
3197 {
3198 pDevice->TbiFlags = 0;
3199 }
3200
3201 #endif /* INCLUDE_TBI_SUPPORT */
3202
3203 /* UseTaggedStatus is only valid for 5701 and later. */
3204 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
3205 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) &&
3206 ((pDevice->BondId == GRC_MISC_BD_ID_5788) ||
3207 (pDevice->BondId == GRC_MISC_BD_ID_5788M))))
3208 {
3209 pDevice->Flags &= ~USE_TAGGED_STATUS_FLAG;
3210 pDevice->CoalesceMode = 0;
3211 }
3212 else
3213 {
3214 pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
3215 HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
3216 }
3217
3218 /* Set the status block size. */
3219 if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
3220 T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX)
3221 {
3222 pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
3223 }
3224
3225 /* Check the DURING_INT coalescing ticks parameters. */
3226 if (pDevice->Flags & USE_TAGGED_STATUS_FLAG)
3227 {
3228 if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
3229 {
3230 pDevice->RxCoalescingTicksDuringInt =
3231 DEFAULT_RX_COALESCING_TICKS_DURING_INT;
3232 }
3233
3234 if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
3235 {
3236 pDevice->TxCoalescingTicksDuringInt =
3237 DEFAULT_TX_COALESCING_TICKS_DURING_INT;
3238 }
3239
3240 if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
3241 {
3242 pDevice->RxMaxCoalescedFramesDuringInt =
3243 DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
3244 }
3245
3246 if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
3247 {
3248 pDevice->TxMaxCoalescedFramesDuringInt =
3249 DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
3250 }
3251 }
3252 else
3253 {
3254 if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
3255 {
3256 pDevice->RxCoalescingTicksDuringInt = 0;
3257 }
3258
3259 if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
3260 {
3261 pDevice->TxCoalescingTicksDuringInt = 0;
3262 }
3263
3264 if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
3265 {
3266 pDevice->RxMaxCoalescedFramesDuringInt = 0;
3267 }
3268
3269 if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
3270 {
3271 pDevice->TxMaxCoalescedFramesDuringInt = 0;
3272 }
3273 }
3274
3275 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3276 if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */))
3277 {
3278 pDevice->RxJumboDescCnt = 0;
3279 if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC)
3280 {
3281 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3282 }
3283 }
3284 else if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
3285 {
3286 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3287 pDevice->RxJumboDescCnt = 0;
3288 }
3289 else
3290 {
3291 pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ +
3292 COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK;
3293
3294 if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE)
3295 {
3296 pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE;
3297 pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */;
3298 }
3299 pDevice->TxMtu = pDevice->RxMtu;
3300 }
3301 #else
3302 pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3303 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3304
3305 pDevice->RxPacketDescCnt =
3306 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3307 pDevice->RxJumboDescCnt +
3308 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3309 pDevice->RxStdDescCnt;
3310
3311 if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC)
3312 {
3313 pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
3314 }
3315
3316 if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE)
3317 {
3318 pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
3319 }
3320
3321 /* Configure the proper ways to get link change interrupt. */
3322 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO)
3323 {
3324 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3325 {
3326 pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
3327 }
3328 else
3329 {
3330 pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
3331 }
3332 }
3333 else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
3334 {
3335 /* Auto-polling does not work on 5700_AX and 5700_BX. */
3336 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3337 {
3338 pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
3339 }
3340 }
3341
3342 /* Determine the method to get link change status. */
3343 if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO)
3344 {
3345 /* The link status bit in the status block does not work on 5700_AX */
3346 /* and 5700_BX chips. */
3347 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3348 {
3349 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
3350 }
3351 else
3352 {
3353 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
3354 }
3355 }
3356
3357 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
3358 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
3359 {
3360 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
3361 }
3362
3363 if (!EeSigFound)
3364 {
3365 pDevice->LedCtrl = LED_CTRL_PHY_MODE_1;
3366 }
3367
3368 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
3369 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
3370 {
3371 /* bug? 5701 in LINK10 mode does not seem to work when */
3372 /* PhyIntMode is LINK_READY. */
3373 if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
3374 #ifdef INCLUDE_TBI_SUPPORT
3375 !(pDevice->TbiFlags & ENABLE_TBI_FLAG) &&
3376 #endif
3377 pDevice->LedCtrl == LED_CTRL_PHY_MODE_2)
3378 {
3379 pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
3380 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
3381 }
3382 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
3383 {
3384 pDevice->LedCtrl = LED_CTRL_PHY_MODE_1;
3385 }
3386 }
3387
3388 #ifdef BCM_WOL
3389 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
3390 pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
3391 pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
3392 pDevice->ChipRevId == T3_CHIP_ID_5701_B2)
3393 {
3394 pDevice->WolSpeed = WOL_SPEED_10MB;
3395 }
3396 else
3397 {
3398 if (pDevice->Flags & WOL_LIMIT_10MBPS_FLAG)
3399 {
3400 pDevice->WolSpeed = WOL_SPEED_10MB;
3401 }
3402 else
3403 {
3404 pDevice->WolSpeed = WOL_SPEED_100MB;
3405 }
3406 }
3407 #endif
3408
3409 pDevice->PciState = REG_RD(pDevice, PciCfg.PciState);
3410
3411 pDevice->DmaReadFifoSize = 0;
3412 if (((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705) &&
3413 (pDevice->ChipRevId != T3_CHIP_ID_5705_A0)) ||
3414 T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId) )
3415 {
3416 #ifdef INCLUDE_TCP_SEG_SUPPORT
3417 if ((pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION) &&
3418 ((pDevice->ChipRevId == T3_CHIP_ID_5705_A1) ||
3419 (pDevice->ChipRevId == T3_CHIP_ID_5705_A2)))
3420 {
3421 pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_SIZE_128;
3422 }
3423 else
3424 #endif
3425 {
3426 if (!(pDevice->PciState & T3_PCI_STATE_HIGH_BUS_SPEED) &&
3427 !(pDevice->Flags & BCM5788_FLAG) &&
3428 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3429 {
3430 pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_LONG_BURST;
3431 if (pDevice->ChipRevId == T3_CHIP_ID_5705_A1)
3432 {
3433 pDevice->Flags |= RX_BD_LIMIT_64_FLAG;
3434 }
3435 pDevice->Flags |= DMA_WR_MODE_RX_ACCELERATE_FLAG;
3436 }
3437 else if (pDevice->Flags & PCI_EXPRESS_FLAG)
3438 {
3439 pDevice->DmaReadFifoSize = DMA_READ_MODE_FIFO_LONG_BURST;
3440 }
3441 }
3442 }
3443
3444 pDevice->Flags &= ~T3_HAS_TWO_CPUS;
3445 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
3446 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
3447 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703 ||
3448 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
3449 {
3450 pDevice->Flags |= T3_HAS_TWO_CPUS;
3451 }
3452
3453 /*
3454 * BCM4785: In general, various information is read from NVRAM,
3455 * including vital product data, version info, and other goodies.
3456 *
3457 * In the case of the BCM4785, access to external EEPROM is
3458 * avoided, so these calls are skipped.
3459 */
3460 if (!pDevice->Flags & SB_CORE_FLAG) {
3461 LM_ReadVPD(pDevice);
3462 LM_ReadBootCodeVersion(pDevice);
3463 LM_ReadIPMICodeVersion(pDevice);
3464 LM_GetBusSpeed(pDevice);
3465 }
3466
3467 return LM_STATUS_SUCCESS;
3468 } /* LM_GetAdapterInfo */
3469
3470 STATIC PLM_ADAPTER_INFO
3471 LM_GetAdapterInfoBySsid(
3472 LM_UINT16 Svid,
3473 LM_UINT16 Ssid)
3474 {
3475 static LM_ADAPTER_INFO AdapterArr[] =
3476 {
3477 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0},
3478 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0},
3479 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1},
3480 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 },
3481 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0},
3482 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0},
3483 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
3484 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0},
3485 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0},
3486 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5703_PHY_ID, 0},
3487 { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5703_PHY_ID, 0},
3488
3489 { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 },
3490 { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 },
3491 { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 },
3492 { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 },
3493 { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 },
3494
3495 { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 },
3496 { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 },
3497 { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 },
3498 { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 },
3499
3500 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 },
3501 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 },
3502 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 },
3503 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 },
3504 { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 },
3505
3506 { 0x1014, 0x0281, 0, 1 },
3507 };
3508 LM_UINT32 j;
3509
3510 for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++)
3511 {
3512 if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid)
3513 {
3514 return &AdapterArr[j];
3515 }
3516 }
3517
3518 return NULL;
3519 }
3520
3521
3522
3523 /******************************************************************************/
3524 /* Description: */
3525 /* This routine sets up receive/transmit buffer descriptions queues. */
3526 /* */
3527 /* Return: */
3528 /* LM_STATUS_SUCCESS */
3529 /******************************************************************************/
3530 LM_STATUS
3531 LM_InitializeAdapter(
3532 PLM_DEVICE_BLOCK pDevice)
3533 {
3534 LM_PHYSICAL_ADDRESS MemPhy;
3535 PLM_UINT8 pMemVirt;
3536 PLM_PACKET pPacket;
3537 LM_STATUS Status;
3538 LM_UINT32 Size;
3539 LM_UINT32 Value32, j;
3540 LM_UINT32 DmaWrCmd, DmaRdCmd, DmaWrBdry, DmaRdBdry;
3541
3542 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
3543 j = 0;
3544 while (((Value32 & 0x3ff) != (pDevice->PciCommandStatusWords & 0x3ff)) &&
3545 (j < 1000))
3546 {
3547 /* On PCIE devices, there are some rare cases where the device */
3548 /* is in the process of link-training at this point */
3549 MM_Wait(200);
3550 MM_WriteConfig32(pDevice, PCI_COMMAND_REG, pDevice->PciCommandStatusWords);
3551 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
3552 j++;
3553 }
3554 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
3555 /* Set power state to D0. */
3556 LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
3557
3558 /* Intialize the queues. */
3559 QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container,
3560 MAX_RX_PACKET_DESC_COUNT);
3561 QQ_InitQueue(&pDevice->RxPacketFreeQ.Container,
3562 MAX_RX_PACKET_DESC_COUNT);
3563
3564 QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT);
3565 QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT);
3566
3567 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
3568 {
3569 pDevice->RcvRetRcbEntryCount = 512;
3570 pDevice->RcvRetRcbEntryCountMask = 511;
3571 }
3572 else
3573 {
3574 pDevice->RcvRetRcbEntryCount = T3_RCV_RETURN_RCB_ENTRY_COUNT;
3575 pDevice->RcvRetRcbEntryCountMask = T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK;
3576 }
3577
3578 /* Allocate shared memory for: status block, the buffers for receive */
3579 /* rings -- standard, mini, jumbo, and return rings. */
3580 Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) +
3581 T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
3582 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3583 T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
3584 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3585 (pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD));
3586
3587 /* Memory for host based Send BD. */
3588 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
3589 {
3590 Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
3591 }
3592
3593 /* Allocate the memory block. */
3594 Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE);
3595 if(Status != LM_STATUS_SUCCESS)
3596 {
3597 return Status;
3598 }
3599
3600 DmaWrCmd = DMA_CTRL_WRITE_CMD;
3601 DmaRdCmd = DMA_CTRL_READ_CMD;
3602 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_DISABLE;
3603 DmaRdBdry = DMA_CTRL_READ_BOUNDARY_DISABLE;
3604 #ifdef BCM_DISCONNECT_AT_CACHELINE
3605 /* This code is intended for PPC64 and other similar architectures */
3606 /* Only the following chips support this */
3607 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
3608 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) ||
3609 (pDevice->Flags & PCI_EXPRESS_FLAG))
3610 {
3611 switch(pDevice->CacheLineSize * 4)
3612 {
3613 case 16:
3614 case 32:
3615 case 64:
3616 case 128:
3617 if (!(pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) &&
3618 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3619 {
3620 /* PCI-X */
3621 /* use 384 which is a multiple of 16,32,64,128 */
3622 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_384_PCIX;
3623 break;
3624 }
3625 else if (pDevice->Flags & PCI_EXPRESS_FLAG)
3626 {
3627 /* PCI Express */
3628 /* use 128 which is a multiple of 16,32,64,128 */
3629 DmaWrCmd = DMA_CTRL_WRITE_BOUNDARY_128_PCIE;
3630 break;
3631 }
3632 /* fall through */
3633 case 256:
3634 /* use 256 which is a multiple of 16,32,64,128,256 */
3635 if ((pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) &&
3636 !(pDevice->Flags & PCI_EXPRESS_FLAG))
3637 {
3638 /* PCI */
3639 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_256;
3640 }
3641 else if (!(pDevice->Flags & PCI_EXPRESS_FLAG))
3642 {
3643 /* PCI-X */
3644 DmaWrBdry = DMA_CTRL_WRITE_BOUNDARY_256_PCIX;
3645 }
3646 break;
3647 }
3648 }
3649 #endif
3650 pDevice->DmaReadWriteCtrl = DmaWrCmd | DmaRdCmd | DmaWrBdry | DmaRdBdry;
3651 /* Program DMA Read/Write */
3652 if (pDevice->Flags & PCI_EXPRESS_FLAG)
3653 {
3654
3655 /* !=0 is 256 max or greater payload size so set water mark accordingly*/
3656 Value32 = (REG_RD(pDevice, PciCfg.DeviceCtrl) & MAX_PAYLOAD_SIZE_MASK);
3657 if (Value32)
3658 {
3659 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_PCIE_H20MARK_256;
3660 }else
3661 {
3662 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_PCIE_H20MARK_128;
3663 }
3664
3665 }
3666 else if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS)
3667 {
3668 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3669 {
3670 pDevice->DmaReadWriteCtrl |= 0x003f0000;
3671 }
3672 else
3673 {
3674 pDevice->DmaReadWriteCtrl |= 0x003f000f;
3675 }
3676 }
3677 else /* pci-x */
3678 {
3679 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
3680 {
3681 pDevice->DmaReadWriteCtrl |= 0x009f0000;
3682 }
3683
3684 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
3685 {
3686 pDevice->DmaReadWriteCtrl |= 0x009C0000;
3687 }
3688
3689 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704 ||
3690 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703 )
3691 {
3692 Value32 = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f;
3693 if ((Value32 == 0x6) || (Value32 == 0x7))
3694 {
3695 pDevice->Flags |= ONE_DMA_AT_ONCE_FLAG;
3696 }
3697 }
3698 else if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
3699 {
3700 pDevice->DmaReadWriteCtrl &= ~DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
3701 if( T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5780)
3702 pDevice->DmaReadWriteCtrl |= (BIT_20 | BIT_18 | DMA_CTRL_WRITE_ONE_DMA_AT_ONCE);
3703 else
3704 pDevice->DmaReadWriteCtrl |= (BIT_20 | BIT_18 | BIT_15);
3705 /* bit 15 is the current CQ 13140 Fix */
3706 }
3707 else
3708 {
3709 pDevice->DmaReadWriteCtrl |= 0x001b000f;
3710 }
3711 }
3712 if((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
3713 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704))
3714 {
3715 pDevice->DmaReadWriteCtrl &= 0xfffffff0;
3716 }
3717
3718 if (pDevice->Flags & ONE_DMA_AT_ONCE_FLAG)
3719 {
3720 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
3721 }
3722
3723 REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
3724
3725 LM_SwitchClocks(pDevice);
3726
3727 if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS)
3728 {
3729 return LM_STATUS_FAILURE;
3730 }
3731
3732 /* Status block. */
3733 pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
3734 pDevice->StatusBlkPhy = MemPhy;
3735 pMemVirt += T3_STATUS_BLOCK_SIZE;
3736 LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE);
3737
3738 /* Statistics block. */
3739 pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
3740 pDevice->StatsBlkPhy = MemPhy;
3741 pMemVirt += sizeof(T3_STATS_BLOCK);
3742 LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK));
3743
3744 /* Receive standard BD buffer. */
3745 pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
3746 pDevice->RxStdBdPhy = MemPhy;
3747
3748 pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
3749 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3750 T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
3751
3752 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3753 /* Receive jumbo BD buffer. */
3754 pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
3755 pDevice->RxJumboBdPhy = MemPhy;
3756
3757 pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
3758 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3759 T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
3760 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3761
3762 /* Receive return BD buffer. */
3763 pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
3764 pDevice->RcvRetBdPhy = MemPhy;
3765
3766 pMemVirt += pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD);
3767 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3768 pDevice->RcvRetRcbEntryCount * sizeof(T3_RCV_BD));
3769
3770 /* Set up Send BD. */
3771 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
3772 {
3773 pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
3774 pDevice->SendBdPhy = MemPhy;
3775
3776 pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
3777 LM_INC_PHYSICAL_ADDRESS(&MemPhy,
3778 sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT);
3779 }
3780 #ifdef BCM_NIC_SEND_BD
3781 else
3782 {
3783 pDevice->pSendBdVirt = (PT3_SND_BD)
3784 pDevice->pMemView->uIntMem.First32k.BufferDesc;
3785 pDevice->SendBdPhy.High = 0;
3786 pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
3787 }
3788 #endif
3789
3790 /* Allocate memory for packet descriptors. */
3791 Size = (pDevice->RxPacketDescCnt +
3792 pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
3793 Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket);
3794 if(Status != LM_STATUS_SUCCESS)
3795 {
3796 return Status;
3797 }
3798 pDevice->pPacketDescBase = (PLM_VOID) pPacket;
3799
3800 /* Create transmit packet descriptors from the memory block and add them */
3801 /* to the TxPacketFreeQ for each send ring. */
3802 for(j = 0; j < pDevice->TxPacketDescCnt; j++)
3803 {
3804 /* Ring index. */
3805 pPacket->Flags = 0;
3806
3807 /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
3808 QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);
3809
3810 /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
3811 /* is the total size of the packet descriptor including the */
3812 /* os-specific extensions in the UM_PACKET structure. */
3813 pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
3814 } /* for(j.. */
3815
3816 /* Create receive packet descriptors from the memory block and add them */
3817 /* to the RxPacketFreeQ. Create the Standard packet descriptors. */
3818 for(j = 0; j < pDevice->RxStdDescCnt; j++)
3819 {
3820 /* Receive producer ring. */
3821 pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
3822
3823 /* Receive buffer size. */
3824 if (T3_ASIC_5714_FAMILY(pDevice->ChipRevId) &&
3825 (pDevice->RxJumboBufferSize) )
3826 {
3827 pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
3828 }else{
3829 pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
3830 }
3831
3832 /* Add the descriptor to RxPacketFreeQ. */
3833 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
3834
3835 /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
3836 /* is the total size of the packet descriptor including the */
3837 /* os-specific extensions in the UM_PACKET structure. */
3838 pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
3839 } /* for */
3840
3841
3842 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3843 /* Create the Jumbo packet descriptors. */
3844 for(j = 0; j < pDevice->RxJumboDescCnt; j++)
3845 {
3846 /* Receive producer ring. */
3847 pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;
3848
3849 /* Receive buffer size. */
3850 pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
3851
3852 /* Add the descriptor to RxPacketFreeQ. */
3853 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
3854
3855 /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
3856 /* is the total size of the packet descriptor including the */
3857 /* os-specific extensions in the UM_PACKET structure. */
3858 pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
3859 } /* for */
3860 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3861
3862 /* Initialize the rest of the packet descriptors. */
3863 Status = MM_InitializeUmPackets(pDevice);
3864 if(Status != LM_STATUS_SUCCESS)
3865 {
3866 return Status;
3867 } /* if */
3868
3869 /* Default receive mask. */
3870 pDevice->ReceiveMask &= LM_KEEP_VLAN_TAG;
3871 pDevice->ReceiveMask |= LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
3872 LM_ACCEPT_UNICAST;
3873
3874 /* Make sure we are in the first 32k memory window or NicSendBd. */
3875 REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
3876
3877 /* Initialize the hardware. */
3878 Status = LM_ResetAdapter(pDevice);
3879 if(Status != LM_STATUS_SUCCESS)
3880 {
3881 return Status;
3882 }
3883
3884 /* We are done with initialization. */
3885 pDevice->InitDone = TRUE;
3886
3887 return LM_STATUS_SUCCESS;
3888 } /* LM_InitializeAdapter */
3889
3890
3891 LM_STATUS
3892 LM_DisableChip(PLM_DEVICE_BLOCK pDevice)
3893 {
3894 LM_UINT32 data;
3895
3896 pDevice->RxMode &= ~RX_MODE_ENABLE;
3897 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
3898 if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE))
3899 {
3900 MM_Wait(20);
3901 }
3902 data = REG_RD(pDevice, RcvBdIn.Mode);
3903 data &= ~RCV_BD_IN_MODE_ENABLE;
3904 REG_WR(pDevice, RcvBdIn.Mode,data);
3905 if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE))
3906 {
3907 MM_Wait(20);
3908 }
3909 data = REG_RD(pDevice, RcvListPlmt.Mode);
3910 data &= ~RCV_LIST_PLMT_MODE_ENABLE;
3911 REG_WR(pDevice, RcvListPlmt.Mode,data);
3912 if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE))
3913 {
3914 MM_Wait(20);
3915 }
3916 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3917 {
3918 data = REG_RD(pDevice, RcvListSel.Mode);
3919 data &= ~RCV_LIST_SEL_MODE_ENABLE;
3920 REG_WR(pDevice, RcvListSel.Mode,data);
3921 if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE))
3922 {
3923 MM_Wait(20);
3924 }
3925 }
3926 data = REG_RD(pDevice, RcvDataBdIn.Mode);
3927 data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
3928 REG_WR(pDevice, RcvDataBdIn.Mode,data);
3929 if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE))
3930 {
3931 MM_Wait(20);
3932 }
3933 data = REG_RD(pDevice, RcvDataComp.Mode);
3934 data &= ~RCV_DATA_COMP_MODE_ENABLE;
3935 REG_WR(pDevice, RcvDataComp.Mode,data);
3936 if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE))
3937 {
3938 MM_Wait(20);
3939 }
3940 data = REG_RD(pDevice, RcvBdComp.Mode);
3941 data &= ~RCV_BD_COMP_MODE_ENABLE;
3942 REG_WR(pDevice, RcvBdComp.Mode,data);
3943 if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE))
3944 {
3945 MM_Wait(20);
3946 }
3947 data = REG_RD(pDevice, SndBdSel.Mode);
3948 data &= ~SND_BD_SEL_MODE_ENABLE;
3949 REG_WR(pDevice, SndBdSel.Mode, data);
3950 if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE))
3951 {
3952 MM_Wait(20);
3953 }
3954 data = REG_RD(pDevice, SndBdIn.Mode);
3955 data &= ~SND_BD_IN_MODE_ENABLE;
3956 REG_WR(pDevice, SndBdIn.Mode, data);
3957 if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE))
3958 {
3959 MM_Wait(20);
3960 }
3961 data = REG_RD(pDevice, SndDataIn.Mode);
3962 data &= ~T3_SND_DATA_IN_MODE_ENABLE;
3963 REG_WR(pDevice, SndDataIn.Mode,data);
3964 if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE))
3965 {
3966 MM_Wait(20);
3967 }
3968 data = REG_RD(pDevice, DmaRead.Mode);
3969 data &= ~DMA_READ_MODE_ENABLE;
3970 REG_WR(pDevice, DmaRead.Mode, data);
3971 if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE))
3972 {
3973 MM_Wait(20);
3974 }
3975 data = REG_RD(pDevice, SndDataComp.Mode);
3976 data &= ~SND_DATA_COMP_MODE_ENABLE;
3977 REG_WR(pDevice, SndDataComp.Mode, data);
3978 if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE))
3979 {
3980 MM_Wait(20);
3981 }
3982
3983 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
3984 {
3985 data = REG_RD(pDevice,DmaComp.Mode);
3986 data &= ~DMA_COMP_MODE_ENABLE;
3987 REG_WR(pDevice, DmaComp.Mode, data);
3988 if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE))
3989 {
3990 MM_Wait(20);
3991 }
3992 }
3993 data = REG_RD(pDevice, SndBdComp.Mode);
3994 data &= ~SND_BD_COMP_MODE_ENABLE;
3995 REG_WR(pDevice, SndBdComp.Mode, data);
3996 if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE))
3997 {
3998 MM_Wait(20);
3999 }
4000 /* Clear TDE bit */
4001 pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE;
4002 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
4003 pDevice->TxMode &= ~TX_MODE_ENABLE;
4004 REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
4005 if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE))
4006 {
4007 MM_Wait(20);
4008 }
4009 data = REG_RD(pDevice, HostCoalesce.Mode);
4010 data &= ~HOST_COALESCE_ENABLE;
4011 REG_WR(pDevice, HostCoalesce.Mode, data);
4012 if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE))
4013 {
4014 MM_Wait(20);
4015 }
4016 data = REG_RD(pDevice, DmaWrite.Mode);
4017 data &= ~DMA_WRITE_MODE_ENABLE;
4018 REG_WR(pDevice, DmaWrite.Mode,data);
4019 if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE))
4020 {
4021 MM_Wait(20);
4022 }
4023
4024 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4025 {
4026 data = REG_RD(pDevice, MbufClusterFree.Mode);
4027 data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
4028 REG_WR(pDevice, MbufClusterFree.Mode,data);
4029 if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE))
4030 {
4031 MM_Wait(20);
4032 }
4033 }
4034 /* Reset all FTQs */
4035 REG_WR(pDevice, Ftq.Reset, 0xffffffff);
4036 REG_WR(pDevice, Ftq.Reset, 0x0);
4037
4038 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4039 {
4040 data = REG_RD(pDevice, BufMgr.Mode);
4041 data &= ~BUFMGR_MODE_ENABLE;
4042 REG_WR(pDevice, BufMgr.Mode,data);
4043 if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE))
4044 {
4045 MM_Wait(20);
4046 }
4047 data = REG_RD(pDevice, MemArbiter.Mode);
4048 data &= ~T3_MEM_ARBITER_MODE_ENABLE;
4049 REG_WR(pDevice, MemArbiter.Mode, data);
4050 if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE))
4051 {
4052 MM_Wait(20);
4053 }
4054 }
4055 return LM_STATUS_SUCCESS;
4056 }
4057
4058 LM_STATUS
4059 LM_DisableFW(PLM_DEVICE_BLOCK pDevice)
4060 {
4061 #ifdef BCM_ASF
4062 int j;
4063 LM_UINT32 Value32;
4064
4065 if (pDevice->AsfFlags & ASF_ENABLED)
4066 {
4067 MEM_WR_OFFSET(pDevice, T3_CMD_MAILBOX, T3_CMD_NICDRV_PAUSE_FW);
4068 Value32 = REG_RD(pDevice, Grc.RxCpuEvent);
4069 REG_WR(pDevice, Grc.RxCpuEvent, Value32 | BIT_14);
4070 for (j = 0; j < 100; j++)
4071 {
4072 Value32 = REG_RD(pDevice, Grc.RxCpuEvent);
4073 if (!(Value32 & BIT_14))
4074 {
4075 break;
4076 }
4077 MM_Wait(1);
4078 }
4079 }
4080 #endif
4081 return LM_STATUS_SUCCESS;
4082 }
4083
4084 /******************************************************************************/
4085 /* Description: */
4086 /* This function reinitializes the adapter. */
4087 /* */
4088 /* Return: */
4089 /* LM_STATUS_SUCCESS */
4090 /******************************************************************************/
4091 LM_STATUS
4092 LM_ResetAdapter(
4093 PLM_DEVICE_BLOCK pDevice)
4094 {
4095 LM_UINT32 Value32;
4096 LM_UINT32 j, k;
4097 int reset_count = 0;
4098
4099 /* Disable interrupt. */
4100 LM_DisableInterrupt(pDevice);
4101
4102 restart_reset:
4103 LM_DisableFW(pDevice);
4104
4105 /* May get a spurious interrupt */
4106 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;
4107
4108 LM_WritePreResetSignatures(pDevice, LM_INIT_RESET);
4109 /* Disable transmit and receive DMA engines. Abort all pending requests. */
4110 if(pDevice->InitDone)
4111 {
4112 LM_Abort(pDevice);
4113 }
4114
4115 pDevice->ShuttingDown = FALSE;
4116
4117 LM_ResetChip(pDevice);
4118
4119 LM_WriteLegacySignatures(pDevice, LM_INIT_RESET);
4120
4121 /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */
4122 /* in other chip revisions except 5750 */
4123 if ((pDevice->Flags & DELAY_PCI_GRANT_FLAG) &&
4124 !(pDevice->Flags & PCI_EXPRESS_FLAG))
4125 {
4126 REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | BIT_31);
4127 }
4128
4129 if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
4130 {
4131 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
4132 {
4133 Value32 = REG_RD(pDevice, PciCfg.PciState);
4134 Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
4135 REG_WR(pDevice, PciCfg.PciState, Value32);
4136 }
4137 }
4138 if (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5704_BX)
4139 {
4140 /* New bits defined in register 0x64 to enable some h/w fixes */
4141 /* These new bits are 'write-only' */
4142 Value32 = REG_RD(pDevice, PciCfg.MsiData);
4143 REG_WR(pDevice, PciCfg.MsiData, Value32 | BIT_26 | BIT_28 | BIT_29);
4144 }
4145
4146 /* Enable TaggedStatus mode. */
4147 if (pDevice->Flags & USE_TAGGED_STATUS_FLAG)
4148 {
4149 pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
4150 }
4151
4152 /* Restore PCI configuration registers. */
4153 MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
4154 pDevice->SavedCacheLineReg);
4155 MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
4156 (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
4157
4158 /* Initialize the statistis Block */
4159 pDevice->pStatusBlkVirt->Status = 0;
4160 pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
4161 pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
4162 pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
4163
4164 for(j = 0; j < 16; j++)
4165 {
4166 pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
4167 pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
4168 }
4169
4170 for(k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT ;k++)
4171 {
4172 pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
4173 pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
4174 pDevice->pRxStdBdVirt[k].Flags = RCV_BD_FLAG_END;
4175 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) &&
4176 (pDevice->RxJumboBufferSize) )
4177 pDevice->pRxStdBdVirt[k].Len = pDevice->RxJumboBufferSize;
4178 else
4179 pDevice->pRxStdBdVirt[k].Len = MAX_STD_RCV_BUFFER_SIZE;
4180 }
4181
4182 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
4183 /* Receive jumbo BD buffer. */
4184 for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++)
4185 {
4186 pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
4187 pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
4188 pDevice->pRxJumboBdVirt[k].Flags = RCV_BD_FLAG_END |
4189 RCV_BD_FLAG_JUMBO_RING;
4190 pDevice->pRxJumboBdVirt[k].Len = (LM_UINT16) pDevice->RxJumboBufferSize;
4191 }
4192 #endif
4193
4194 REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
4195
4196 /* GRC mode control register. */
4197 Value32 =
4198 #ifdef BIG_ENDIAN_HOST
4199 GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
4200 GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
4201 GRC_MODE_BYTE_SWAP_DATA |
4202 GRC_MODE_WORD_SWAP_DATA |
4203 #else
4204 GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
4205 GRC_MODE_BYTE_SWAP_DATA |
4206 GRC_MODE_WORD_SWAP_DATA |
4207 #endif
4208 GRC_MODE_INT_ON_MAC_ATTN |
4209 GRC_MODE_HOST_STACK_UP;
4210
4211 /* Configure send BD mode. */
4212 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
4213 {
4214 Value32 |= GRC_MODE_HOST_SEND_BDS;
4215 }
4216 #ifdef BCM_NIC_SEND_BD
4217 else
4218 {
4219 Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;
4220 }
4221 #endif
4222
4223 /* Configure pseudo checksum mode. */
4224 if (pDevice->Flags & NO_TX_PSEUDO_HDR_CSUM_FLAG)
4225 {
4226 Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;
4227 }
4228
4229 if (pDevice->Flags & NO_RX_PSEUDO_HDR_CSUM_FLAG)
4230 {
4231 Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;
4232 }
4233
4234 pDevice->GrcMode = Value32;
4235 REG_WR(pDevice, Grc.Mode, Value32);
4236
4237 /* Setup the timer prescalar register. */
4238 Value32 = REG_RD(pDevice, Grc.MiscCfg) & ~0xff;
4239 /* Clock is always 66Mhz. */
4240 REG_WR(pDevice, Grc.MiscCfg, Value32 | (65 << 1));
4241
4242 /* Set up the MBUF pool base address and size. */
4243 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
4244 {
4245 #ifdef INCLUDE_TCP_SEG_SUPPORT
4246 if (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION)
4247 {
4248 Value32 = LM_GetStkOffLdFirmwareSize(pDevice);
4249 Value32 = (Value32 + 0x7f) & ~0x7f;
4250 pDevice->MbufBase = T3_NIC_BCM5705_MBUF_POOL_ADDR + Value32;
4251 pDevice->MbufSize = T3_NIC_BCM5705_MBUF_POOL_SIZE - Value32 - 0xa00;
4252 REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
4253 REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
4254 }
4255 #endif
4256 }
4257 else if (!T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
4258 {
4259 REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
4260 REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
4261
4262 /* Set up the DMA descriptor pool base address and size. */
4263 REG_WR(pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
4264 REG_WR(pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
4265
4266 }
4267
4268 /* Configure MBUF and Threshold watermarks */
4269 /* Configure the DMA read MBUF low water mark. */
4270 if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
4271 {
4272 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4273 {
4274 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
4275 T3_DEF_DMA_MBUF_LOW_WMARK_5705);
4276 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
4277 T3_DEF_RX_MAC_MBUF_LOW_WMARK_5705);
4278 REG_WR(pDevice, BufMgr.MbufHighWaterMark,
4279 T3_DEF_MBUF_HIGH_WMARK_5705);
4280 }
4281 else
4282 {
4283 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
4284 T3_DEF_DMA_MBUF_LOW_WMARK);
4285 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
4286 T3_DEF_RX_MAC_MBUF_LOW_WMARK);
4287 REG_WR(pDevice, BufMgr.MbufHighWaterMark,
4288 T3_DEF_MBUF_HIGH_WMARK);
4289 }
4290 }else if( T3_ASIC_5714_FAMILY(pDevice->ChipRevId)){
4291
4292 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,0);
4293 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,0x4b);
4294 REG_WR(pDevice, BufMgr.MbufHighWaterMark,0x96);
4295 }
4296 else
4297 {
4298 REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
4299 T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
4300 REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
4301 T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
4302 REG_WR(pDevice, BufMgr.MbufHighWaterMark,
4303 T3_DEF_MBUF_HIGH_WMARK_JUMBO);
4304 }
4305
4306 REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
4307 REG_WR(pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);
4308
4309 /* Enable buffer manager. */
4310 REG_WR(pDevice, BufMgr.Mode, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
4311
4312 for(j = 0 ;j < 2000; j++)
4313 {
4314 if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
4315 break;
4316 MM_Wait(10);
4317 }
4318
4319 if(j >= 2000)
4320 {
4321 return LM_STATUS_FAILURE;
4322 }
4323
4324 /* GRC reset will reset FTQ */
4325
4326 /* Receive BD Ring replenish threshold. */
4327 REG_WR(pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt/8);
4328
4329 /* Initialize the Standard Receive RCB. */
4330 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
4331 pDevice->RxStdBdPhy.High);
4332 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
4333 pDevice->RxStdBdPhy.Low);
4334 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
4335 (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
4336
4337 if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4338 {
4339 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
4340 512 << 16);
4341 }
4342 else
4343 {
4344 REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
4345 MAX_STD_RCV_BUFFER_SIZE << 16);
4346
4347 /* Initialize the Jumbo Receive RCB. */
4348 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
4349 T3_RCB_FLAG_RING_DISABLED);
4350 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
4351 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
4352 pDevice->RxJumboBdPhy.High);
4353 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
4354 pDevice->RxJumboBdPhy.Low);
4355 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);
4356 REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
4357 (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
4358
4359 REG_WR(pDevice, RcvBdIn.JumboRcvThreshold, pDevice->RxJumboDescCnt/8);
4360
4361 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
4362
4363 /* Initialize the Mini Receive RCB. */
4364 REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
4365 T3_RCB_FLAG_RING_DISABLED);
4366
4367 /* Disable all the unused rings. */
4368 for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
4369 MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags,
4370 T3_RCB_FLAG_RING_DISABLED);
4371 } /* for */
4372
4373 }
4374
4375 /* Initialize the indices. */
4376 pDevice->SendProdIdx = 0;
4377 pDevice->SendConIdx = 0;
4378
4379 MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
4380 MB_REG_RD(pDevice, Mailbox.SendHostProdIdx[0].Low);
4381 MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
4382 MB_REG_RD(pDevice, Mailbox.SendNicProdIdx[0].Low);
4383
4384 /* Set up host or NIC based send RCB. */
4385 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
4386 {
4387 MEM_WR(pDevice, SendRcb[0].HostRingAddr.High,
4388 pDevice->SendBdPhy.High);
4389 MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low,
4390 pDevice->SendBdPhy.Low);
4391
4392 /* Setup the RCB. */
4393 MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags,
4394 T3_SEND_RCB_ENTRY_COUNT << 16);
4395
4396 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4397 {
4398 /* Set up the NIC ring address in the RCB. */
4399 MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR);
4400 }
4401 for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
4402 {
4403 pDevice->pSendBdVirt[k].HostAddr.High = 0;
4404 pDevice->pSendBdVirt[k].HostAddr.Low = 0;
4405 }
4406 }
4407 #ifdef BCM_NIC_SEND_BD
4408 else
4409 {
4410 MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0);
4411 MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0);
4412 MEM_WR(pDevice, SendRcb[0].NicRingAddr,
4413 pDevice->SendBdPhy.Low);
4414
4415 for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
4416 {
4417 MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].HostAddr.High), 0);
4418 MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].HostAddr.Low), 0);
4419 MM_MEMWRITEL(&(pDevice->pSendBdVirt[k].u1.Len_Flags), 0);
4420 pDevice->ShadowSendBd[k].HostAddr.High = 0;
4421 pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
4422 }
4423 }
4424 #endif
4425 MM_ATOMIC_SET(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1);
4426
4427 /* Configure the receive return rings. */
4428 for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++)
4429 {
4430 MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED);
4431 }
4432
4433 pDevice->RcvRetConIdx = 0;
4434
4435 MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High,
4436 pDevice->RcvRetBdPhy.High);
4437 MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low,
4438 pDevice->RcvRetBdPhy.Low);
4439
4440 MEM_WR(pDevice, RcvRetRcb[0].NicRingAddr, 0);
4441
4442 /* Setup the RCB. */
4443 MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags,
4444 pDevice->RcvRetRcbEntryCount << 16);
4445
4446 /* Reinitialize RX ring producer index */
4447 MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0);
4448 MB_REG_RD(pDevice, Mailbox.RcvStdProdIdx.Low);
4449 MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
4450 MB_REG_RD(pDevice, Mailbox.RcvJumboProdIdx.Low);
4451 MB_REG_WR(pDevice, Mailbox.RcvMiniProdIdx.Low, 0);
4452 MB_REG_RD(pDevice, Mailbox.RcvMiniProdIdx.Low);
4453
4454 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
4455 pDevice->RxJumboProdIdx = 0;
4456 pDevice->RxJumboQueuedCnt = 0;
4457 #endif
4458
4459 /* Reinitialize our copy of the indices. */
4460 pDevice->RxStdProdIdx = 0;
4461 pDevice->RxStdQueuedCnt = 0;
4462
4463 #if T3_JUMBO_RCV_ENTRY_COUNT
4464 pDevice->RxJumboProdIdx = 0;
4465 #endif /* T3_JUMBO_RCV_ENTRY_COUNT */
4466
4467 /* Configure the MAC address. */
4468 LM_SetMacAddress(pDevice, pDevice->NodeAddress);
4469
4470 /* Initialize the transmit random backoff seed. */
4471 Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
4472 pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
4473 pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
4474 MAC_TX_BACKOFF_SEED_MASK;
4475 REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32);
4476
4477 /* Receive MTU. Frames larger than the MTU is marked as oversized. */
4478 REG_WR(pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */
4479
4480 /* Configure Time slot/IPG per 802.3 */
4481 REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
4482
4483 /*
4484 * Configure Receive Rules so that packets don't match
4485 * Programmble rule will be queued to Return Ring 1
4486 */
4487 REG_WR(pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
4488
4489 /*
4490 * Configure to have 16 Classes of Services (COS) and one
4491 * queue per class. Bad frames are queued to RRR#1.
4492 * And frames don't match rules are also queued to COS#1.
4493 */
4494 REG_WR(pDevice, RcvListPlmt.Config, 0x181);
4495
4496 /* Enable Receive Placement Statistics */
4497 if ((pDevice->DmaReadFifoSize == DMA_READ_MODE_FIFO_LONG_BURST) &&
4498 (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION))
4499 {
4500 Value32 = REG_RD(pDevice, RcvListPlmt.StatsEnableMask);
4501 Value32 &= ~T3_DISABLE_LONG_BURST_READ_DYN_FIX;
4502 REG_WR(pDevice, RcvListPlmt.StatsEnableMask, Value32);
4503 }
4504 else
4505 {
4506 REG_WR(pDevice, RcvListPlmt.StatsEnableMask,0xffffff);
4507 }
4508 REG_WR(pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
4509
4510 /* Enable Send Data Initator Statistics */
4511 REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff);
4512 REG_WR(pDevice, SndDataIn.StatsCtrl,
4513 T3_SND_DATA_IN_STATS_CTRL_ENABLE | \
4514 T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
4515
4516 /* Disable the host coalescing state machine before configuring it's */
4517 /* parameters. */
4518 REG_WR(pDevice, HostCoalesce.Mode, 0);
4519 for(j = 0; j < 2000; j++)
4520 {
4521 Value32 = REG_RD(pDevice, HostCoalesce.Mode);
4522 if(!(Value32 & HOST_COALESCE_ENABLE))
4523 {
4524 break;
4525 }
4526 MM_Wait(10);
4527 }
4528
4529 /* Host coalescing configurations. */
4530 REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks);
4531 REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks);
4532 REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames,
4533 pDevice->RxMaxCoalescedFrames);
4534 REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames,
4535 pDevice->TxMaxCoalescedFrames);
4536
4537 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4538 {
4539 REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt,
4540 pDevice->RxCoalescingTicksDuringInt);
4541 REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt,
4542 pDevice->TxCoalescingTicksDuringInt);
4543 }
4544 REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
4545 pDevice->RxMaxCoalescedFramesDuringInt);
4546 REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
4547 pDevice->TxMaxCoalescedFramesDuringInt);
4548
4549 /* Initialize the address of the status block. The NIC will DMA */
4550 /* the status block to this memory which resides on the host. */
4551 REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High,
4552 pDevice->StatusBlkPhy.High);
4553 REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low,
4554 pDevice->StatusBlkPhy.Low);
4555
4556 /* Initialize the address of the statistics block. The NIC will DMA */
4557 /* the statistics to this block of memory. */
4558 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4559 {
4560 REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High,
4561 pDevice->StatsBlkPhy.High);
4562 REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low,
4563 pDevice->StatsBlkPhy.Low);
4564
4565 REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks,
4566 pDevice->StatsCoalescingTicks);
4567
4568 REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
4569 REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00);
4570 }
4571
4572 /* Enable Host Coalesing state machine */
4573 REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
4574 pDevice->CoalesceMode);
4575
4576 /* Enable the Receive BD Completion state machine. */
4577 REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
4578 RCV_BD_COMP_MODE_ATTN_ENABLE);
4579
4580 /* Enable the Receive List Placement state machine. */
4581 REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
4582
4583 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4584 {
4585 /* Enable the Receive List Selector state machine. */
4586 REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
4587 RCV_LIST_SEL_MODE_ATTN_ENABLE);
4588 }
4589
4590 /* Reset the Rx MAC State Machine.
4591 *
4592 * The Rx MAC State Machine must be reset when using fiber to prevent the
4593 * first packet being lost. This is needed primarily so that the loopback
4594 * test (which currently only sends one packet) doesn't fail.
4595 *
4596 * Also note that the Rx MAC State Machine (0x468) should be reset _before_
4597 * writting to the MAC Mode register (0x400). Failures have been seen on
4598 * 5780/5714's using fiber where they stopped receiving packets in a simple
4599 * ping test when the Rx MAC State Machine was reset _after_ the MAC Mode
4600 * register was set.
4601 */
4602
4603 if ((pDevice->TbiFlags & ENABLE_TBI_FLAG) ||
4604 (pDevice->PhyFlags & PHY_IS_FIBER))
4605 {
4606 REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET);
4607 REG_RD_BACK(pDevice, MacCtrl.RxMode);
4608 MM_Wait(10);
4609 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
4610 REG_RD_BACK(pDevice, MacCtrl.RxMode);
4611 }
4612
4613 /* Clear the statistics block. */
4614 for(j = 0x0300; j < 0x0b00; j = j + 4)
4615 {
4616 MEM_WR_OFFSET(pDevice, j, 0);
4617 }
4618
4619 /* Set Mac Mode */
4620 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
4621 {
4622 pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
4623 }
4624 else if(pDevice->PhyFlags & PHY_IS_FIBER)
4625 {
4626 pDevice->MacMode = MAC_MODE_PORT_MODE_GMII;
4627 }
4628 else
4629 {
4630 pDevice->MacMode = 0;
4631 }
4632
4633 /* Enable transmit DMA, clear statistics. */
4634 pDevice->MacMode |= MAC_MODE_ENABLE_TX_STATISTICS |
4635 MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
4636 MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
4637 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
4638 MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
4639
4640 /* GRC miscellaneous local control register. */
4641 pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
4642 GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
4643
4644 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
4645 {
4646 pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
4647 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
4648 }
4649 else if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) &&
4650 !(pDevice->Flags & EEPROM_WP_FLAG))
4651 {
4652 /* Make sure we're on Vmain */
4653 /* The other port may cause us to be on Vaux */
4654 pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
4655 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2;
4656 }
4657
4658 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
4659 MM_Wait(40);
4660
4661 /* Reset RX counters. */
4662 for(j = 0; j < sizeof(LM_RX_COUNTERS); j++)
4663 {
4664 ((PLM_UINT8) &pDevice->RxCounters)[j] = 0;
4665 }
4666
4667 /* Reset TX counters. */
4668 for(j = 0; j < sizeof(LM_TX_COUNTERS); j++)
4669 {
4670 ((PLM_UINT8) &pDevice->TxCounters)[j] = 0;
4671 }
4672
4673 MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0);
4674 MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low);
4675 pDevice->LastTag = 0;
4676
4677 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4678 {
4679 /* Enable the DMA Completion state machine. */
4680 REG_WR(pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
4681 }
4682
4683 /* Enable the DMA Write state machine. */
4684 Value32 = DMA_WRITE_MODE_ENABLE |
4685 DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
4686 DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
4687 DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
4688 DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
4689 DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
4690 DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
4691 DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
4692 DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
4693
4694 if (pDevice->Flags & DMA_WR_MODE_RX_ACCELERATE_FLAG)
4695 {
4696 Value32 |= DMA_WRITE_MODE_RECEIVE_ACCELERATE;
4697 }
4698
4699 if (pDevice->Flags & HOST_COALESCING_BUG_FIX)
4700 {
4701 Value32 |= (1 << 29);
4702 }
4703
4704 REG_WR(pDevice, DmaWrite.Mode, Value32);
4705
4706 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
4707 {
4708 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
4709 {
4710 Value32 = REG_RD(pDevice, PciCfg.PciXCapabilities);
4711 Value32 &= ~PCIX_CMD_MAX_BURST_MASK;
4712 Value32 |= PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL;
4713 REG_WR(pDevice, PciCfg.PciXCapabilities, Value32);
4714 }
4715 else if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
4716 {
4717 Value32 = REG_RD(pDevice, PciCfg.PciXCapabilities);
4718 Value32 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK);
4719 Value32 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) &
4720 PCIX_CMD_MAX_BURST_MASK);
4721 if (pDevice->Flags & MULTI_SPLIT_ENABLE_FLAG)
4722 {
4723 Value32 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
4724 & PCIX_CMD_MAX_SPLIT_MASK;
4725 }
4726 REG_WR(pDevice, PciCfg.PciXCapabilities, Value32);
4727 }
4728 }
4729
4730 /* Enable the Read DMA state machine. */
4731 Value32 = DMA_READ_MODE_ENABLE |
4732 DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
4733 DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
4734 DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
4735 DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
4736 DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
4737 DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
4738 DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
4739 DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
4740
4741 if (pDevice->Flags & MULTI_SPLIT_ENABLE_FLAG)
4742 {
4743 Value32 |= DMA_READ_MODE_MULTI_SPLIT_ENABLE;
4744 }
4745
4746 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4747 {
4748 Value32 |= pDevice->DmaReadFifoSize;
4749 }
4750 #ifdef INCLUDE_TCP_SEG_SUPPORT
4751 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
4752 {
4753 Value32 |= BIT_27;
4754 }
4755 #endif
4756
4757
4758 REG_WR(pDevice, DmaRead.Mode, Value32);
4759
4760 /* Enable the Receive Data Completion state machine. */
4761 REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
4762 RCV_DATA_COMP_MODE_ATTN_ENABLE);
4763
4764 if (!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
4765 {
4766 /* Enable the Mbuf Cluster Free state machine. */
4767 REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
4768 }
4769
4770 /* Enable the Send Data Completion state machine. */
4771 REG_WR(pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
4772
4773 /* Enable the Send BD Completion state machine. */
4774 REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
4775 SND_BD_COMP_MODE_ATTN_ENABLE);
4776
4777 /* Enable the Receive BD Initiator state machine. */
4778 REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
4779 RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
4780
4781 /* Enable the Receive Data and Receive BD Initiator state machine. */
4782 REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
4783 RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
4784
4785 /* Enable the Send Data Initiator state machine. */
4786 REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
4787
4788 #ifdef INCLUDE_TCP_SEG_SUPPORT
4789 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
4790 {
4791 REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE | 0x8);
4792 }
4793 #endif
4794
4795 /* Enable the Send BD Initiator state machine. */
4796 REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
4797 SND_BD_IN_MODE_ATTN_ENABLE);
4798
4799 /* Enable the Send BD Selector state machine. */
4800 REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
4801 SND_BD_SEL_MODE_ATTN_ENABLE);
4802
4803 #ifdef INCLUDE_5701_AX_FIX
4804 if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0)
4805 {
4806 LM_LoadRlsFirmware(pDevice);
4807 }
4808 #endif
4809
4810 /* Queue Rx packet buffers. */
4811 if(pDevice->QueueRxPackets)
4812 {
4813 LM_QueueRxPackets(pDevice);
4814 }
4815
4816 if (pDevice->ChipRevId == T3_CHIP_ID_5705_A0)
4817 {
4818 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_STD_RCV_BUFFER_DESC_ADDR + 8);
4819 j = 0;
4820 while ((Value32 != MAX_STD_RCV_BUFFER_SIZE) && (j < 10))
4821 {
4822 MM_Wait(20);
4823 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_STD_RCV_BUFFER_DESC_ADDR + 8);
4824 j++;
4825 }
4826 if (j >= 10)
4827 {
4828 reset_count++;
4829 LM_Abort(pDevice);
4830 if (reset_count > 5)
4831 return LM_STATUS_FAILURE;
4832 goto restart_reset;
4833 }
4834 }
4835
4836 /* Enable the transmitter. */
4837 pDevice->TxMode = TX_MODE_ENABLE;
4838 REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
4839
4840 /* Enable the receiver. */
4841 pDevice->RxMode = (pDevice->RxMode & RX_MODE_KEEP_VLAN_TAG) |
4842 RX_MODE_ENABLE;
4843 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
4844
4845 #ifdef BCM_WOL
4846 if (pDevice->RestoreOnWakeUp)
4847 {
4848 pDevice->RestoreOnWakeUp = FALSE;
4849 pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
4850 pDevice->RequestedLineSpeed = pDevice->WakeUpRequestedLineSpeed;
4851 pDevice->RequestedDuplexMode = pDevice->WakeUpRequestedDuplexMode;
4852 }
4853 #endif
4854
4855 /* Disable auto polling. */
4856 pDevice->MiMode = 0xc0000;
4857 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
4858
4859 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl);
4860
4861 /* Activate Link to enable MAC state machine */
4862 REG_WR(pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);
4863
4864 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
4865 {
4866 if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1)
4867 {
4868 REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000);
4869 }
4870 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
4871 {
4872
4873 if(!(pDevice->TbiFlags & TBI_DO_PREEMPHASIS))
4874 {
4875 /* Set SerDes drive transmission level to 1.2V */
4876 Value32 = REG_RD(pDevice, MacCtrl.SerdesCfg) & 0xfffff000;
4877 REG_WR(pDevice, MacCtrl.SerdesCfg, Value32 | 0x880);
4878 }
4879 }
4880 }
4881
4882 REG_WR(pDevice, MacCtrl.LowWaterMarkMaxRxFrame, 2);
4883
4884 if(pDevice->PhyFlags & PHY_IS_FIBER)
4885 {
4886 Value32 = REG_RD_OFFSET(pDevice, 0x5b0);
4887 REG_WR_OFFSET(pDevice, 0x5b0, Value32 | BIT_10 );
4888
4889 pDevice->GrcLocalCtrl |= BIT_4 ;
4890 pDevice->GrcLocalCtrl &= ~BIT_5 ;
4891
4892 REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
4893 Value32 = REG_RD(pDevice, Grc.LocalCtrl);
4894 MM_Wait(40);
4895 }
4896
4897 if (!pDevice->InitDone)
4898 {
4899 if(UNKNOWN_PHY_ID(pDevice->PhyId) && (pDevice->Flags & ROBO_SWITCH_FLAG)) {
4900 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
4901 } else {
4902 pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
4903 }
4904 }
4905
4906 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG) &&
4907 ( ((pDevice->PhyId & PHY_ID_MASK) != PHY_BCM5401_PHY_ID)&&
4908 ((pDevice->PhyId & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) ))
4909 {
4910 /* 5401/5411 PHY needs a delay of about 1 second after PHY reset */
4911 /* Without the delay, it has problem linking at forced 10 half */
4912 /* So skip the reset... */
4913 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5780)
4914 for(j =0; j<0x5000; j++)
4915 MM_Wait(1);
4916
4917 LM_ResetPhy(pDevice);
4918 }
4919
4920 /* Setup the phy chip. */
4921 LM_SetupPhy(pDevice);
4922
4923 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG)){
4924 /* Clear CRC stats */
4925 LM_ReadPhy(pDevice, 0x1e, &Value32);
4926 LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000);
4927 LM_ReadPhy(pDevice, 0x14, &Value32);
4928 }
4929
4930 /* Set up the receive mask. */
4931 LM_SetReceiveMask(pDevice, pDevice->ReceiveMask);
4932
4933 #ifdef INCLUDE_TCP_SEG_SUPPORT
4934 if (pDevice->TaskToOffload & LM_TASK_OFFLOAD_TCP_SEGMENTATION)
4935 {
4936 if (LM_LoadStkOffLdFirmware(pDevice) == LM_STATUS_FAILURE)
4937 {
4938 return LM_STATUS_FAILURE;
4939 }
4940 }
4941 #endif
4942 LM_WritePostResetSignatures(pDevice, LM_INIT_RESET);
4943
4944 return LM_STATUS_SUCCESS;
4945 } /* LM_ResetAdapter */
4946
4947
4948 /******************************************************************************/
4949 /* Description: */
4950 /* This routine disables the adapter from generating interrupts. */
4951 /* */
4952 /* Return: */
4953 /* LM_STATUS_SUCCESS */
4954 /******************************************************************************/
4955 LM_STATUS
4956 LM_DisableInterrupt(
4957 PLM_DEVICE_BLOCK pDevice)
4958 {
4959 REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
4960 MISC_HOST_CTRL_MASK_PCI_INT);
4961 MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1);
4962 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
4963 {
4964 MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low);
4965 }
4966
4967 return LM_STATUS_SUCCESS;
4968 }
4969
4970
4971
4972 /******************************************************************************/
4973 /* Description: */
4974 /* This routine enables the adapter to generate interrupts. */
4975 /* */
4976 /* Return: */
4977 /* LM_STATUS_SUCCESS */
4978 /******************************************************************************/
4979 LM_STATUS
4980 LM_EnableInterrupt(
4981 PLM_DEVICE_BLOCK pDevice)
4982 {
4983 MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, pDevice->LastTag << 24);
4984 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
4985 {
4986 MB_REG_RD(pDevice, Mailbox.Interrupt[0].Low);
4987 }
4988
4989 REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
4990 ~MISC_HOST_CTRL_MASK_PCI_INT);
4991
4992 REG_WR(pDevice, HostCoalesce.Mode, pDevice->CoalesceMode |
4993 HOST_COALESCE_ENABLE | HOST_COALESCE_NOW);
4994
4995 return LM_STATUS_SUCCESS;
4996 }
4997
4998
4999
5000 /******************************************************************************/
5001 /* Description: */
5002 /* This routine puts a packet on the wire if there is a transmit DMA */
5003 /* descriptor available; otherwise the packet is queued for later */
5004 /* transmission. If the second argue is NULL, this routine will put */
5005 /* the queued packet on the wire if possible. */
5006 /* */
5007 /* Return: */
5008 /* LM_STATUS_SUCCESS */
5009 /******************************************************************************/
5010 LM_STATUS
5011 LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
5012 {
5013 LM_UINT32 FragCount;
5014 PT3_SND_BD pSendBd, pTmpSendBd;
5015 #ifdef BCM_NIC_SEND_BD
5016 PT3_SND_BD pShadowSendBd;
5017 T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
5018 #endif
5019 LM_UINT32 StartIdx, Idx;
5020
5021 while (1)
5022 {
5023 /* Initalize the send buffer descriptors. */
5024 StartIdx = Idx = pDevice->SendProdIdx;
5025
5026 #ifdef BCM_NIC_SEND_BD
5027 if (pDevice->Flags & NIC_SEND_BD_FLAG)
5028 {
5029 pTmpSendBd = pSendBd = &NicSendBdArr[0];
5030 }
5031 else
5032 #endif
5033 {
5034 pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
5035 }
5036
5037 /* Next producer index. */
5038 for(FragCount = 0; ; )
5039 {
5040 LM_UINT32 Value32, Len;
5041
5042 /* Initialize the pointer to the send buffer fragment. */
5043 MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount);
5044
5045 pSendBd->u2.VlanTag = pPacket->VlanTag;
5046
5047 /* Setup the control flags and send buffer size. */
5048 Value32 = (Len << 16) | pPacket->Flags;
5049
5050 #ifdef INCLUDE_TCP_SEG_SUPPORT
5051 if (Value32 & (SND_BD_FLAG_CPU_PRE_DMA | SND_BD_FLAG_CPU_POST_DMA))
5052 {
5053 if(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
5054 {
5055 pSendBd->u2.s2.Reserved = pPacket->u.Tx.MaxSegmentSize;
5056 }
5057 else if (FragCount == 0)
5058 {
5059 pSendBd->u2.s2.Reserved = pPacket->u.Tx.MaxSegmentSize;
5060 }
5061 else
5062 {
5063 pSendBd->u2.s2.Reserved = 0;
5064 Value32 &= 0xffff0fff;
5065 }
5066 }
5067 #endif
5068 Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
5069
5070 FragCount++;
5071 if (FragCount >= pPacket->u.Tx.FragCount)
5072 {
5073 pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END;
5074 break;
5075 }
5076 else
5077 {
5078 pSendBd->u1.Len_Flags = Value32;
5079 }
5080
5081 pSendBd++;
5082 if ((Idx == 0) &&
5083 !(pDevice->Flags & NIC_SEND_BD_FLAG))
5084 {
5085 pSendBd = &pDevice->pSendBdVirt[0];
5086 }
5087
5088 pDevice->SendRing[Idx] = 0;
5089
5090 } /* for */
5091 if (pDevice->Flags & TX_4G_WORKAROUND_FLAG)
5092 {
5093 if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) ==
5094 LM_STATUS_SUCCESS)
5095 {
5096 if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS)
5097 {
5098 QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
5099 return LM_STATUS_FAILURE;
5100 }
5101 continue;
5102 }
5103 }
5104 break;
5105 }
5106 /* Put the packet descriptor in the ActiveQ. */
5107 pDevice->SendRing[StartIdx] = pPacket;
5108
5109 #ifdef BCM_NIC_SEND_BD
5110 if (pDevice->Flags & NIC_SEND_BD_FLAG)
5111 {
5112 pSendBd = &pDevice->pSendBdVirt[StartIdx];
5113 pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];
5114
5115 while (StartIdx != Idx)
5116 {
5117 LM_UINT32 Value32;
5118
5119 if ((Value32 = pTmpSendBd->HostAddr.High) !=
5120 pShadowSendBd->HostAddr.High)
5121 {
5122 MM_MEMWRITEL(&(pSendBd->HostAddr.High), Value32);
5123 pShadowSendBd->HostAddr.High = Value32;
5124 }
5125
5126 MM_MEMWRITEL(&(pSendBd->HostAddr.Low), pTmpSendBd->HostAddr.Low);
5127
5128 if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
5129 pShadowSendBd->u1.Len_Flags)
5130 {
5131 MM_MEMWRITEL(&(pSendBd->u1.Len_Flags), Value32);
5132 pShadowSendBd->u1.Len_Flags = Value32;
5133 }
5134
5135 if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG)
5136 {
5137 MM_MEMWRITEL(&(pSendBd->u2.VlanTag), pTmpSendBd->u2.VlanTag);
5138 }
5139
5140 StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
5141 if (StartIdx == 0)
5142 {
5143 pSendBd = &pDevice->pSendBdVirt[0];
5144 pShadowSendBd = &pDevice->ShadowSendBd[0];
5145 }
5146 else
5147 {
5148 pSendBd++;
5149 pShadowSendBd++;
5150 }
5151 pTmpSendBd++;
5152 }
5153 MM_WMB();
5154 MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
5155
5156 if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
5157 {
5158 MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
5159 }
5160 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
5161 {
5162 MB_REG_RD(pDevice, Mailbox.SendNicProdIdx[0].Low);
5163 }
5164 else
5165 {
5166 MM_MMIOWB();
5167 }
5168 }
5169 else
5170 #endif
5171 {
5172 MM_WMB();
5173 MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
5174
5175 if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
5176 {
5177 MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
5178 }
5179 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
5180 {
5181 MB_REG_RD(pDevice, Mailbox.SendHostProdIdx[0].Low);
5182 }
5183 else
5184 {
5185 MM_MMIOWB();
5186 }
5187 }
5188
5189 /* Update the SendBdLeft count. */
5190 MM_ATOMIC_SUB(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount);
5191
5192 /* Update the producer index. */
5193 pDevice->SendProdIdx = Idx;
5194
5195 return LM_STATUS_SUCCESS;
5196 }
5197
5198 STATIC LM_STATUS
5199 LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
5200 PT3_SND_BD pSendBd)
5201 {
5202 int FragCount;
5203 LM_UINT32 Idx, Base, Len;
5204
5205 Idx = pDevice->SendProdIdx;
5206 for(FragCount = 0; ; )
5207 {
5208 Len = pSendBd->u1.Len_Flags >> 16;
5209 if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) &&
5210 ((Base + 8 + Len) < Base))
5211 {
5212 return LM_STATUS_SUCCESS;
5213 }
5214 FragCount++;
5215 if (FragCount >= pPacket->u.Tx.FragCount)
5216 {
5217 break;
5218 }
5219 pSendBd++;
5220 if (!(pDevice->Flags & NIC_SEND_BD_FLAG))
5221 {
5222 Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
5223 if (Idx == 0)
5224 {
5225 pSendBd = &pDevice->pSendBdVirt[0];
5226 }
5227 }
5228 }
5229 return LM_STATUS_FAILURE;
5230 }
5231
5232 /******************************************************************************/
5233 /* Description: */
5234 /* */
5235 /* Return: */
5236 /******************************************************************************/
5237 LM_UINT32
5238 ComputeCrc32(LM_UINT8 *pBuffer, LM_UINT32 BufferSize)
5239 {
5240 LM_UINT32 Reg;
5241 LM_UINT32 Tmp;
5242 int j, k;
5243
5244 Reg = 0xffffffff;
5245
5246 for(j = 0; j < BufferSize; j++)
5247 {
5248 Reg ^= pBuffer[j];
5249
5250 for(k = 0; k < 8; k++)
5251 {
5252 Tmp = Reg & 0x01;
5253
5254 Reg >>= 1;
5255
5256 if(Tmp)
5257 {
5258 Reg ^= 0xedb88320;
5259 }
5260 }
5261 }
5262
5263 return ~Reg;
5264 } /* ComputeCrc32 */
5265
5266
5267
5268 /******************************************************************************/
5269 /* Description: */
5270 /* This routine sets the receive control register according to ReceiveMask */
5271 /* */
5272 /* Return: */
5273 /* LM_STATUS_SUCCESS */
5274 /******************************************************************************/
5275 LM_STATUS
5276 LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask)
5277 {
5278 LM_UINT32 ReceiveMask;
5279 LM_UINT32 RxMode;
5280 LM_UINT32 j, k;
5281
5282 ReceiveMask = Mask;
5283
5284 RxMode = pDevice->RxMode;
5285
5286 if(Mask & LM_ACCEPT_UNICAST)
5287 {
5288 Mask &= ~LM_ACCEPT_UNICAST;
5289 }
5290
5291 if(Mask & LM_ACCEPT_MULTICAST)
5292 {
5293 Mask &= ~LM_ACCEPT_MULTICAST;
5294 }
5295
5296 if(Mask & LM_ACCEPT_ALL_MULTICAST)
5297 {
5298 Mask &= ~LM_ACCEPT_ALL_MULTICAST;
5299 }
5300
5301 if(Mask & LM_ACCEPT_BROADCAST)
5302 {
5303 Mask &= ~LM_ACCEPT_BROADCAST;
5304 }
5305
5306 RxMode &= ~RX_MODE_KEEP_VLAN_TAG;
5307 if (Mask & LM_KEEP_VLAN_TAG)
5308 {
5309 RxMode |= RX_MODE_KEEP_VLAN_TAG;
5310 Mask &= ~LM_KEEP_VLAN_TAG;
5311 }
5312
5313 RxMode &= ~RX_MODE_PROMISCUOUS_MODE;
5314 if(Mask & LM_PROMISCUOUS_MODE)
5315 {
5316 RxMode |= RX_MODE_PROMISCUOUS_MODE;
5317 Mask &= ~LM_PROMISCUOUS_MODE;
5318 }
5319
5320 RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED);
5321 if(Mask & LM_ACCEPT_ERROR_PACKET)
5322 {
5323 RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED;
5324 Mask &= ~LM_ACCEPT_ERROR_PACKET;
5325 }
5326
5327 /* Make sure all the bits are valid before committing changes. */
5328 if(Mask)
5329 {
5330 return LM_STATUS_FAILURE;
5331 }
5332
5333 /* Commit the new filter. */
5334 pDevice->ReceiveMask = ReceiveMask;
5335
5336 pDevice->RxMode = RxMode;
5337
5338 if (pDevice->PowerLevel != LM_POWER_STATE_D0)
5339 {
5340 return LM_STATUS_SUCCESS;
5341 }
5342
5343 REG_WR(pDevice, MacCtrl.RxMode, RxMode);
5344
5345 /* Set up the MC hash table. */
5346 if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST)
5347 {
5348 for(k = 0; k < 4; k++)
5349 {
5350 REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff);
5351 }
5352 }
5353 else if(ReceiveMask & LM_ACCEPT_MULTICAST)
5354 {
5355 for(k = 0; k < 4; k++)
5356 {
5357 REG_WR(pDevice, MacCtrl.HashReg[k], pDevice->MulticastHash[k]);
5358 }
5359 }
5360 else
5361 {
5362 /* Reject all multicast frames. */
5363 for(j = 0; j < 4; j++)
5364 {
5365 REG_WR(pDevice, MacCtrl.HashReg[j], 0);
5366 }
5367 }
5368
5369 /* By default, Tigon3 will accept broadcast frames. We need to setup */
5370 if(ReceiveMask & LM_ACCEPT_BROADCAST)
5371 {
5372 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
5373 REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
5374 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
5375 REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
5376 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
5377 REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
5378 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
5379 REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
5380 }
5381 else
5382 {
5383 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
5384 REJECT_BROADCAST_RULE1_RULE);
5385 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
5386 REJECT_BROADCAST_RULE1_VALUE);
5387 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
5388 REJECT_BROADCAST_RULE2_RULE);
5389 REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
5390 REJECT_BROADCAST_RULE2_VALUE);
5391 }
5392
5393 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
5394 {
5395 k = 16;
5396 }
5397 else if (!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
5398 {
5399 k = 16;
5400 }
5401 else
5402 {
5403 k = 8;
5404 }
5405 #ifdef BCM_ASF
5406 if (pDevice->AsfFlags & ASF_ENABLED)
5407 {
5408 k -= 4;
5409 }
5410 #endif
5411
5412 /* disable the rest of the rules. */
5413 for(j = RCV_LAST_RULE_IDX; j < k; j++)
5414 {
5415 REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0);
5416 REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0);
5417 }
5418
5419 return LM_STATUS_SUCCESS;
5420 } /* LM_SetReceiveMask */
5421
5422
5423
5424 /******************************************************************************/
5425 /* Description: */
5426 /* Disable the interrupt and put the transmitter and receiver engines in */
5427 /* an idle state. Also aborts all pending send requests and receive */
5428 /* buffers. */
5429 /* */
5430 /* Return: */
5431 /* LM_STATUS_SUCCESS */
5432 /******************************************************************************/
5433 LM_STATUS
5434 LM_Abort(
5435 PLM_DEVICE_BLOCK pDevice)
5436 {
5437 PLM_PACKET pPacket;
5438 LM_UINT Idx;
5439
5440 LM_DisableInterrupt(pDevice);
5441
5442 LM_DisableChip(pDevice);
5443
5444 /*
5445 * If we do not have a status block pointer, then
5446 * the device hasn't really been opened. Do not
5447 * attempt to clean up packets.
5448 */
5449 if (pDevice->pStatusBlkVirt == NULL)
5450 return LM_STATUS_SUCCESS;
5451
5452 /* Abort packets that have already queued to go out. */
5453 Idx = pDevice->SendConIdx;
5454 for ( ; ; )
5455 {
5456 if ((pPacket = pDevice->SendRing[Idx]))
5457 {
5458 pDevice->SendRing[Idx] = 0;
5459 pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED;
5460 pDevice->TxCounters.TxPacketAbortedCnt++;
5461
5462 MM_ATOMIC_ADD(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount);
5463 Idx = (Idx + pPacket->u.Tx.FragCount) &
5464 T3_SEND_RCB_ENTRY_COUNT_MASK;
5465
5466 QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
5467 }
5468 else
5469 {
5470 break;
5471 }
5472 }
5473
5474 /* Cleanup the receive return rings. */
5475 #ifdef BCM_NAPI_RXPOLL
5476 LM_ServiceRxPoll(pDevice, T3_RCV_RETURN_RCB_ENTRY_COUNT);
5477 #else
5478 LM_ServiceRxInterrupt(pDevice);
5479 #endif
5480
5481 /* Indicate packets to the protocol. */
5482 MM_IndicateTxPackets(pDevice);
5483
5484 #ifdef BCM_NAPI_RXPOLL
5485
5486 /* Move the receive packet descriptors in the ReceivedQ to the */
5487 /* free queue. */
5488 for(; ;)
5489 {
5490 pPacket = (PLM_PACKET) QQ_PopHead(
5491 &pDevice->RxPacketReceivedQ.Container);
5492 if(pPacket == NULL)
5493 {
5494 break;
5495 }
5496 MM_UnmapRxDma(pDevice, pPacket);
5497 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5498 }
5499 #else
5500 /* Indicate received packets to the protocols. */
5501 MM_IndicateRxPackets(pDevice);
5502 #endif
5503
5504 /* Clean up the Std Receive Producer ring. */
5505 /* Don't always trust the consumer idx in the status block in case of */
5506 /* hw failure */
5507 Idx = 0;
5508
5509 while(Idx < T3_STD_RCV_RCB_ENTRY_COUNT)
5510 {
5511 if ((pPacket = pDevice->RxStdRing[Idx]))
5512 {
5513 MM_UnmapRxDma(pDevice, pPacket);
5514 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5515 pDevice->RxStdRing[Idx] = 0;
5516 }
5517
5518 Idx++;
5519 } /* while */
5520
5521 /* Reinitialize our copy of the indices. */
5522 pDevice->RxStdProdIdx = 0;
5523
5524 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
5525 /* Clean up the Jumbo Receive Producer ring. */
5526 Idx = 0;
5527
5528 while(Idx < T3_JUMBO_RCV_RCB_ENTRY_COUNT)
5529 {
5530 if ((pPacket = pDevice->RxJumboRing[Idx]))
5531 {
5532 MM_UnmapRxDma(pDevice, pPacket);
5533 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5534 pDevice->RxJumboRing[Idx] = 0;
5535 }
5536 Idx++;
5537 } /* while */
5538
5539 /* Reinitialize our copy of the indices. */
5540 pDevice->RxJumboProdIdx = 0;
5541 #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
5542
5543 /* Initialize the statistis Block */
5544 pDevice->pStatusBlkVirt->Status = 0;
5545 pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
5546 pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
5547 pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
5548
5549 return LM_STATUS_SUCCESS;
5550 } /* LM_Abort */
5551
5552
5553
5554 /******************************************************************************/
5555 /* Description: */
5556 /* Disable the interrupt and put the transmitter and receiver engines in */
5557 /* an idle state. Aborts all pending send requests and receive buffers. */
5558 /* Also free all the receive buffers. */
5559 /* */
5560 /* Return: */
5561 /* LM_STATUS_SUCCESS */
5562 /******************************************************************************/
5563 LM_STATUS
5564 LM_DoHalt(LM_DEVICE_BLOCK *pDevice)
5565 {
5566 PLM_PACKET pPacket;
5567 LM_UINT32 EntryCnt;
5568
5569 LM_DisableFW(pDevice);
5570
5571 LM_WritePreResetSignatures(pDevice, LM_SHUTDOWN_RESET);
5572 LM_Abort(pDevice);
5573
5574 if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5461_PHY_ID)
5575 LM_WritePhy(pDevice, BCM546X_1c_SHADOW_REG,
5576 (BCM546X_1c_SPR_CTRL_1 | BCM546X_1c_WR_EN));
5577
5578 /* Get the number of entries in the queue. */
5579 EntryCnt = QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container);
5580
5581 /* Make sure all the packets have been accounted for. */
5582 for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++)
5583 {
5584 pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
5585 if (pPacket == 0)
5586 break;
5587
5588 MM_FreeRxBuffer(pDevice, pPacket);
5589
5590 QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
5591 }
5592
5593 LM_ResetChip(pDevice);
5594 LM_WriteLegacySignatures(pDevice, LM_SHUTDOWN_RESET);
5595
5596 /* Restore PCI configuration registers. */
5597 MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
5598 pDevice->SavedCacheLineReg);
5599 LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
5600 (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
5601
5602 /* Reprogram the MAC address. */
5603 LM_SetMacAddress(pDevice, pDevice->NodeAddress);
5604
5605 return LM_STATUS_SUCCESS;
5606 } /* LM_DoHalt */
5607
5608
5609 LM_STATUS
5610 LM_Halt(LM_DEVICE_BLOCK *pDevice)
5611 {
5612 LM_STATUS status;
5613
5614 status = LM_DoHalt(pDevice);
5615 LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET);
5616 return status;
5617 }
5618
5619
5620 STATIC LM_VOID
5621 LM_WritePreResetSignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode)
5622 {
5623 MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX,T3_MAGIC_NUM_FIRMWARE_INIT_DONE);
5624 #ifdef BCM_ASF
5625 if (pDevice->AsfFlags & ASF_NEW_HANDSHAKE)
5626 {
5627 if (Mode == LM_INIT_RESET)
5628 {
5629 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_START);
5630 }
5631 else if (Mode == LM_SHUTDOWN_RESET)
5632 {
5633 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_UNLOAD);
5634 }
5635 else if (Mode == LM_SUSPEND_RESET)
5636 {
5637 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_SUSPEND);
5638 }
5639 }
5640 #endif
5641 }
5642
5643 STATIC LM_VOID
5644 LM_WritePostResetSignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode)
5645 {
5646 #ifdef BCM_ASF
5647 if (pDevice->AsfFlags & ASF_NEW_HANDSHAKE)
5648 {
5649 if (Mode == LM_INIT_RESET)
5650 {
5651 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX,
5652 T3_DRV_STATE_START_DONE);
5653 }
5654 else if (Mode == LM_SHUTDOWN_RESET)
5655 {
5656 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX,
5657 T3_DRV_STATE_UNLOAD_DONE);
5658 }
5659 }
5660 #endif
5661 }
5662
5663 STATIC LM_VOID
5664 LM_WriteLegacySignatures(LM_DEVICE_BLOCK *pDevice, LM_RESET_TYPE Mode)
5665 {
5666 #ifdef BCM_ASF
5667 if (pDevice->AsfFlags & ASF_ENABLED)
5668 {
5669 if (Mode == LM_INIT_RESET)
5670 {
5671 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_START);
5672 }
5673 else if (Mode == LM_SHUTDOWN_RESET)
5674 {
5675 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_UNLOAD);
5676 }
5677 else if (Mode == LM_SUSPEND_RESET)
5678 {
5679 MEM_WR_OFFSET(pDevice, T3_DRV_STATE_MAILBOX, T3_DRV_STATE_SUSPEND);
5680 }
5681 }
5682 #endif
5683 }
5684
5685 STATIC LM_STATUS
5686 LM_ResetChip(PLM_DEVICE_BLOCK pDevice)
5687 {
5688 LM_UINT32 Value32;
5689 LM_UINT32 j, tmp1 = 0, tmp2 = 0;
5690
5691 /* Wait for access to the nvram interface before resetting. This is */
5692 if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
5693 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
5694 {
5695 /* Request access to the flash interface. */
5696 LM_NVRAM_AcquireLock(pDevice);
5697 }
5698
5699 Value32 = GRC_MISC_CFG_CORE_CLOCK_RESET;
5700 if (pDevice->Flags & PCI_EXPRESS_FLAG)
5701 {
5702 if (REG_RD_OFFSET(pDevice, 0x7e2c) == 0x60) /* PCIE 1.0 system */
5703 {
5704 REG_WR_OFFSET(pDevice, 0x7e2c, 0x20);
5705 }
5706 if (pDevice->ChipRevId != T3_CHIP_ID_5750_A0)
5707 {
5708 /* This bit prevents PCIE link training during GRC reset */
5709 REG_WR(pDevice, Grc.MiscCfg, BIT_29); /* Write bit 29 first */
5710 Value32 |= BIT_29; /* and keep bit 29 set during GRC reset */
5711 }
5712 }
5713 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
5714 {
5715 Value32 |= GRC_MISC_GPHY_KEEP_POWER_DURING_RESET;
5716 }
5717
5718 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
5719 {
5720 /* Save the MSI ENABLE bit (may need to save the message as well) */
5721 tmp1 = LM_RegRd( pDevice, T3_PCI_MSI_ENABLE );
5722 }
5723
5724 /* Global reset. */
5725 RAW_REG_WR(pDevice, Grc.MiscCfg, Value32);
5726 MM_Wait(120);
5727
5728 MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
5729
5730 MM_Wait(120);
5731
5732 /* make sure we re-enable indirect accesses */
5733 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG,
5734 pDevice->MiscHostCtrl);
5735
5736 /* Set MAX PCI retry to zero. */
5737 Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE;
5738 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
5739 {
5740 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
5741 {
5742 Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
5743 }
5744 }
5745 MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32);
5746
5747 /* Restore PCI command register. */
5748 MM_WriteConfig32(pDevice, PCI_COMMAND_REG,
5749 pDevice->PciCommandStatusWords);
5750
5751 /* Disable PCI-X relaxed ordering bit. */
5752 MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32);
5753 Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING;
5754 MM_WriteConfig32(pDevice, PCIX_CAP_REG, Value32);
5755
5756 /* Enable memory arbiter */
5757 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId) )
5758 {
5759 Value32 = REG_RD(pDevice,MemArbiter.Mode);
5760 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE | Value32);
5761 }
5762 else
5763 {
5764 REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
5765 }
5766
5767 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
5768 {
5769 /* restore the MSI ENABLE bit (may need to restore the message also) */
5770 tmp2 = LM_RegRd( pDevice, T3_PCI_MSI_ENABLE );
5771 tmp2 |= (tmp1 & (1 << 16));
5772 LM_RegWr( pDevice, T3_PCI_MSI_ENABLE, tmp2, TRUE );
5773 tmp2 = LM_RegRd( pDevice, T3_PCI_MSI_ENABLE );
5774 }
5775
5776
5777 if (pDevice->ChipRevId == T3_CHIP_ID_5750_A3)
5778 {
5779 /* Because of chip bug on A3, we need to kill the CPU */
5780 LM_DisableFW(pDevice);
5781 REG_WR_OFFSET(pDevice, 0x5000, 0x400);
5782 }
5783
5784 /*
5785 * BCM4785: In order to avoid repercussions from using potentially
5786 * defective internal ROM, stop the Rx RISC CPU, which is not
5787 * required.
5788 */
5789 if (pDevice->Flags & SB_CORE_FLAG) {
5790 LM_DisableFW(pDevice);
5791 LM_HaltCpu(pDevice, T3_RX_CPU_ID);
5792 }
5793
5794 #ifdef BIG_ENDIAN_HOST
5795 /* Reconfigure the mode register. */
5796 Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
5797 GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
5798 GRC_MODE_BYTE_SWAP_DATA |
5799 GRC_MODE_WORD_SWAP_DATA;
5800 #else
5801 /* Reconfigure the mode register. */
5802 Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
5803 #endif
5804 REG_WR(pDevice, Grc.Mode, Value32);
5805
5806 if ((pDevice->Flags & MINI_PCI_FLAG) &&
5807 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705))
5808 {
5809 pDevice->ClockCtrl |= T3_PCI_CLKRUN_OUTPUT_EN;
5810 if (pDevice->ChipRevId == T3_CHIP_ID_5705_A0)
5811 {
5812 pDevice->ClockCtrl |= T3_PCI_FORCE_CLKRUN;
5813 }
5814 REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl);
5815 }
5816
5817 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
5818 {
5819 pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
5820 }
5821 else if(pDevice->PhyFlags & PHY_IS_FIBER)
5822 {
5823 pDevice->MacMode = MAC_MODE_PORT_MODE_GMII;
5824 }
5825 else
5826 {
5827 pDevice->MacMode = 0;
5828 }
5829
5830 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
5831 REG_RD_BACK(pDevice, MacCtrl.Mode);
5832 MM_Wait(40);
5833
5834 /* BCM4785: Don't use any firmware, so don't wait */
5835 if (!pDevice->Flags & SB_CORE_FLAG) {
5836 /* Wait for the firmware to finish initialization. */
5837 for(j = 0; j < 100000; j++) {
5838 MM_Wait(10);
5839
5840 if (j < 100)
5841 continue;
5842
5843 Value32 = MEM_RD_OFFSET(pDevice, T3_FIRMWARE_MAILBOX);
5844 if(Value32 == ~T3_MAGIC_NUM_FIRMWARE_INIT_DONE) {
5845 break;
5846 }
5847 }
5848 if ((j >= 0x100000) && (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)) {
5849 /* if the boot code is not running */
5850 if (LM_NVRAM_AcquireLock(pDevice) != LM_STATUS_SUCCESS) {
5851 LM_DEVICE_BLOCK *pDevice2;
5852
5853 REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RESET);
5854 pDevice2 = MM_FindPeerDev(pDevice);
5855 if (pDevice2 && !pDevice2->InitDone)
5856 REG_WR(pDevice2, Nvram.Cmd, NVRAM_CMD_RESET);
5857 } else {
5858 LM_NVRAM_ReleaseLock(pDevice);
5859 }
5860 }
5861 }
5862
5863 if ((pDevice->Flags & PCI_EXPRESS_FLAG) &&
5864 (pDevice->ChipRevId != T3_CHIP_ID_5750_A0))
5865 {
5866 /* Enable PCIE bug fix */
5867 Value32 = REG_RD_OFFSET(pDevice, 0x7c00);
5868 REG_WR_OFFSET(pDevice, 0x7c00, Value32 | BIT_25 | BIT_29);
5869 }
5870
5871 #ifdef BCM_ASF
5872 pDevice->AsfFlags = 0;
5873 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR);
5874
5875 if (Value32 == T3_NIC_DATA_SIG)
5876 {
5877 Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
5878 if (Value32 & T3_NIC_CFG_ENABLE_ASF)
5879 {
5880 pDevice->AsfFlags = ASF_ENABLED;
5881 if (T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
5882 {
5883 pDevice->AsfFlags |= ASF_NEW_HANDSHAKE;
5884 }
5885 }
5886 }
5887 #endif
5888
5889 return LM_STATUS_SUCCESS;
5890 }
5891
5892
5893 LM_STATUS
5894 LM_ShutdownChip(PLM_DEVICE_BLOCK pDevice, LM_RESET_TYPE Mode)
5895 {
5896 LM_DisableFW(pDevice);
5897 LM_WritePreResetSignatures(pDevice, Mode);
5898 if (pDevice->InitDone)
5899 {
5900 LM_Abort(pDevice);
5901 }
5902 else
5903 {
5904 LM_DisableChip(pDevice);
5905 }
5906 LM_ResetChip(pDevice);
5907 LM_WriteLegacySignatures(pDevice, Mode);
5908 LM_WritePostResetSignatures(pDevice, Mode);
5909 return LM_STATUS_SUCCESS;
5910 }
5911
5912 /******************************************************************************/
5913 /* Description: */
5914 /* */
5915 /* Return: */
5916 /******************************************************************************/
5917 void
5918 LM_ServiceTxInterrupt(
5919 PLM_DEVICE_BLOCK pDevice) {
5920 PLM_PACKET pPacket;
5921 LM_UINT32 HwConIdx;
5922 LM_UINT32 SwConIdx;
5923
5924 HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
5925
5926 /* Get our copy of the consumer index. The buffer descriptors */
5927 /* that are in between the consumer indices are freed. */
5928 SwConIdx = pDevice->SendConIdx;
5929
5930 /* Move the packets from the TxPacketActiveQ that are sent out to */
5931 /* the TxPacketXmittedQ. Packets that are sent use the */
5932 /* descriptors that are between SwConIdx and HwConIdx. */
5933 while(SwConIdx != HwConIdx)
5934 {
5935 pPacket = pDevice->SendRing[SwConIdx];
5936 pDevice->SendRing[SwConIdx] = 0;
5937
5938 /* Set the return status. */
5939 pPacket->PacketStatus = LM_STATUS_SUCCESS;
5940
5941 /* Put the packet in the TxPacketXmittedQ for indication later. */
5942 QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
5943
5944 /* Move to the next packet's BD. */
5945 SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) &
5946 T3_SEND_RCB_ENTRY_COUNT_MASK;
5947
5948 /* Update the number of unused BDs. */
5949 MM_ATOMIC_ADD(&pDevice->SendBdLeft, pPacket->u.Tx.FragCount);
5950
5951 /* Get the new updated HwConIdx. */
5952 HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
5953 } /* while */
5954
5955 /* Save the new SwConIdx. */
5956 pDevice->SendConIdx = SwConIdx;
5957
5958 } /* LM_ServiceTxInterrupt */
5959
5960
5961 #ifdef BCM_NAPI_RXPOLL
5962 /******************************************************************************/
5963 /* Description: */
5964 /* */
5965 /* Return: */
5966 /******************************************************************************/
5967 int
5968 LM_ServiceRxPoll(PLM_DEVICE_BLOCK pDevice, int limit)
5969 {
5970 PLM_PACKET pPacket=NULL;
5971 PT3_RCV_BD pRcvBd;
5972 LM_UINT32 HwRcvRetProdIdx;
5973 LM_UINT32 SwRcvRetConIdx;
5974 int received = 0;
5975
5976 /* Loop thru the receive return rings for received packets. */
5977 HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
5978
5979 SwRcvRetConIdx = pDevice->RcvRetConIdx;
5980 MM_RMB();
5981 while (SwRcvRetConIdx != HwRcvRetProdIdx)
5982 {
5983 pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
5984
5985 /* Get the received packet descriptor. */
5986 pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
5987 MM_UINT_PTR(pRcvBd->Opaque));
5988
5989 switch(pPacket->u.Rx.RcvProdRing) {
5990 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
5991 case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
5992 pDevice->RxJumboRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
5993 break;
5994 #endif
5995 case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
5996 pDevice->RxStdRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
5997 break;
5998 }
5999
6000 /* Check the error flag. */
6001 if(pRcvBd->ErrorFlag &&
6002 pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
6003 {
6004 pPacket->PacketStatus = LM_STATUS_FAILURE;
6005
6006 pDevice->RxCounters.RxPacketErrCnt++;
6007
6008 if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC)
6009 {
6010 pDevice->RxCounters.RxErrCrcCnt++;
6011 }
6012
6013 if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT)
6014 {
6015 pDevice->RxCounters.RxErrCollCnt++;
6016 }
6017
6018 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT)
6019 {
6020 pDevice->RxCounters.RxErrLinkLostCnt++;
6021 }
6022
6023 if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR)
6024 {
6025 pDevice->RxCounters.RxErrPhyDecodeCnt++;
6026 }
6027
6028 if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
6029 {
6030 pDevice->RxCounters.RxErrOddNibbleCnt++;
6031 }
6032
6033 if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT)
6034 {
6035 pDevice->RxCounters.RxErrMacAbortCnt++;
6036 }
6037
6038 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64)
6039 {
6040 pDevice->RxCounters.RxErrShortPacketCnt++;
6041 }
6042
6043 if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES)
6044 {
6045 pDevice->RxCounters.RxErrNoResourceCnt++;
6046 }
6047
6048 if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD)
6049 {
6050 pDevice->RxCounters.RxErrLargePacketCnt++;
6051 }
6052 }
6053 else
6054 {
6055 pPacket->PacketStatus = LM_STATUS_SUCCESS;
6056 pPacket->PacketSize = pRcvBd->Len - 4;
6057
6058 pPacket->Flags = pRcvBd->Flags;
6059 if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG)
6060 {
6061 pPacket->VlanTag = pRcvBd->VlanTag;
6062 }
6063
6064 pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
6065 }
6066
6067 /* Put the packet descriptor containing the received packet */
6068 /* buffer in the RxPacketReceivedQ for indication later. */
6069 QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket);
6070
6071 /* Go to the next buffer descriptor. */
6072 SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
6073 pDevice->RcvRetRcbEntryCountMask;
6074
6075 if (++received >= limit)
6076 {
6077 break;
6078 }
6079 } /* while */
6080
6081 pDevice->RcvRetConIdx = SwRcvRetConIdx;
6082
6083 /* Update the receive return ring consumer index. */
6084 MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
6085 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
6086 {
6087 MB_REG_RD(pDevice, Mailbox.RcvRetConIdx[0].Low);
6088 }
6089 else
6090 {
6091 MM_MMIOWB();
6092 }
6093 return received;
6094 } /* LM_ServiceRxPoll */
6095 #endif /* BCM_NAPI_RXPOLL */
6096
6097
6098 /******************************************************************************/
6099 /* Description: */
6100 /* */
6101 /* Return: */
6102 /******************************************************************************/
6103 void
6104 LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice)
6105 {
6106 #ifndef BCM_NAPI_RXPOLL
6107 PLM_PACKET pPacket;
6108 PT3_RCV_BD pRcvBd;
6109 #endif
6110 LM_UINT32 HwRcvRetProdIdx;
6111 LM_UINT32 SwRcvRetConIdx;
6112
6113 /* Loop thru the receive return rings for received packets. */
6114 HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
6115
6116 SwRcvRetConIdx = pDevice->RcvRetConIdx;
6117 #ifdef BCM_NAPI_RXPOLL
6118 if (!pDevice->RxPoll)
6119 {
6120 if (SwRcvRetConIdx != HwRcvRetProdIdx)
6121 {
6122 if (MM_ScheduleRxPoll(pDevice) == LM_STATUS_SUCCESS)
6123 {
6124 pDevice->RxPoll = TRUE;
6125 REG_WR(pDevice, Grc.Mode,
6126 pDevice->GrcMode | GRC_MODE_NO_INTERRUPT_ON_RECEIVE);
6127 }
6128 }
6129 }
6130 #else
6131 MM_RMB();
6132 while(SwRcvRetConIdx != HwRcvRetProdIdx)
6133 {
6134 pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
6135
6136 /* Get the received packet descriptor. */
6137 pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
6138 MM_UINT_PTR(pRcvBd->Opaque));
6139
6140 switch(pPacket->u.Rx.RcvProdRing) {
6141 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
6142 case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
6143 pDevice->RxJumboRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
6144 break;
6145 #endif
6146 case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
6147 pDevice->RxStdRing[pPacket->u.Rx.RcvRingProdIdx] = 0;
6148 break;
6149 }
6150
6151 /* Check the error flag. */
6152 if(pRcvBd->ErrorFlag &&
6153 pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
6154 {
6155 pPacket->PacketStatus = LM_STATUS_FAILURE;
6156
6157 pDevice->RxCounters.RxPacketErrCnt++;
6158
6159 if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC)
6160 {
6161 pDevice->RxCounters.RxErrCrcCnt++;
6162 }
6163
6164 if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT)
6165 {
6166 pDevice->RxCounters.RxErrCollCnt++;
6167 }
6168
6169 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT)
6170 {
6171 pDevice->RxCounters.RxErrLinkLostCnt++;
6172 }
6173
6174 if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR)
6175 {
6176 pDevice->RxCounters.RxErrPhyDecodeCnt++;
6177 }
6178
6179 if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
6180 {
6181 pDevice->RxCounters.RxErrOddNibbleCnt++;
6182 }
6183
6184 if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT)
6185 {
6186 pDevice->RxCounters.RxErrMacAbortCnt++;
6187 }
6188
6189 if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64)
6190 {
6191 pDevice->RxCounters.RxErrShortPacketCnt++;
6192 }
6193
6194 if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES)
6195 {
6196 pDevice->RxCounters.RxErrNoResourceCnt++;
6197 }
6198
6199 if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD)
6200 {
6201 pDevice->RxCounters.RxErrLargePacketCnt++;
6202 }
6203 }
6204 else
6205 {
6206 pPacket->PacketStatus = LM_STATUS_SUCCESS;
6207 pPacket->PacketSize = pRcvBd->Len - 4;
6208
6209 pPacket->Flags = pRcvBd->Flags;
6210 if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG)
6211 {
6212 pPacket->VlanTag = pRcvBd->VlanTag;
6213 }
6214
6215 pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
6216 }
6217
6218 /* Put the packet descriptor containing the received packet */
6219 /* buffer in the RxPacketReceivedQ for indication later. */
6220 QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket);
6221
6222 /* Go to the next buffer descriptor. */
6223 SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
6224 pDevice->RcvRetRcbEntryCountMask;
6225
6226 } /* while */
6227
6228 pDevice->RcvRetConIdx = SwRcvRetConIdx;
6229
6230 /* Update the receive return ring consumer index. */
6231 MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
6232 if (pDevice->Flags & FLUSH_POSTED_WRITE_FLAG)
6233 {
6234 MB_REG_RD(pDevice, Mailbox.RcvRetConIdx[0].Low);
6235 }
6236 else
6237 {
6238 MM_MMIOWB();
6239 }
6240
6241 #endif
6242 } /* LM_ServiceRxInterrupt */
6243
6244
6245
6246 /******************************************************************************/
6247 /* Description: */
6248 /* This is the interrupt event handler routine. It acknowledges all */
6249 /* pending interrupts and process all pending events. */
6250 /* */
6251 /* Return: */
6252 /* LM_STATUS_SUCCESS */
6253 /******************************************************************************/
6254 LM_STATUS
6255 LM_ServiceInterrupts(
6256 PLM_DEVICE_BLOCK pDevice)
6257 {
6258 LM_UINT32 Value32;
6259 int ServicePhyInt = FALSE;
6260
6261 /* Setup the phy chip whenever the link status changes. */
6262 if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG)
6263 {
6264 Value32 = REG_RD(pDevice, MacCtrl.Status);
6265 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
6266 {
6267 if (Value32 & MAC_STATUS_MI_INTERRUPT)
6268 {
6269 ServicePhyInt = TRUE;
6270 }
6271 }
6272 else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED)
6273 {
6274 ServicePhyInt = TRUE;
6275 }
6276 }
6277 else
6278 {
6279 if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS)
6280 {
6281 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
6282 (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
6283 ServicePhyInt = TRUE;
6284 }
6285 }
6286 #ifdef INCLUDE_TBI_SUPPORT
6287 if (pDevice->IgnoreTbiLinkChange == TRUE)
6288 {
6289 ServicePhyInt = FALSE;
6290 }
6291 #endif
6292 if (ServicePhyInt == TRUE)
6293 {
6294 MM_ACQUIRE_PHY_LOCK_IN_IRQ(pDevice);
6295 LM_SetupPhy(pDevice);
6296 MM_RELEASE_PHY_LOCK_IN_IRQ(pDevice);
6297 }
6298
6299 /* Service receive and transmit interrupts. */
6300 LM_ServiceRxInterrupt(pDevice);
6301 LM_ServiceTxInterrupt(pDevice);
6302
6303 #ifndef BCM_NAPI_RXPOLL
6304 /* No spinlock for this queue since this routine is serialized. */
6305 if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container))
6306 {
6307 /* Indicate receive packets. */
6308 MM_IndicateRxPackets(pDevice);
6309 }
6310 #endif
6311
6312 /* No spinlock for this queue since this routine is serialized. */
6313 if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container))
6314 {
6315 MM_IndicateTxPackets(pDevice);
6316 }
6317
6318 return LM_STATUS_SUCCESS;
6319 } /* LM_ServiceInterrupts */
6320
6321
6322 /******************************************************************************/
6323 /* Description: Add a Multicast address. Note that MC addresses, once added, */
6324 /* cannot be individually deleted. All addresses must be */
6325 /* cleared. */
6326 /* */
6327 /* Return: */
6328 /******************************************************************************/
6329 LM_STATUS
6330 LM_MulticastAdd(LM_DEVICE_BLOCK *pDevice, PLM_UINT8 pMcAddress)
6331 {
6332
6333 LM_UINT32 RegIndex;
6334 LM_UINT32 Bitpos;
6335 LM_UINT32 Crc32;
6336
6337 Crc32 = ComputeCrc32(pMcAddress, ETHERNET_ADDRESS_SIZE);
6338
6339 /* The most significant 7 bits of the CRC32 (no inversion), */
6340 /* are used to index into one of the possible 128 bit positions. */
6341 Bitpos = ~Crc32 & 0x7f;
6342
6343 /* Hash register index. */
6344 RegIndex = (Bitpos & 0x60) >> 5;
6345
6346 /* Bit to turn on within a hash register. */
6347 Bitpos &= 0x1f;
6348
6349 /* Enable the multicast bit. */
6350 pDevice->MulticastHash[RegIndex] |= (1 << Bitpos);
6351
6352 LM_SetReceiveMask(pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST);
6353
6354 return LM_STATUS_SUCCESS;
6355 }
6356
6357
6358 /******************************************************************************/
6359 /* Description: */
6360 /* */
6361 /* Return: */
6362 /******************************************************************************/
6363 LM_STATUS
6364 LM_MulticastDel(LM_DEVICE_BLOCK *pDevice, PLM_UINT8 pMcAddress)
6365 {
6366 return LM_STATUS_FAILURE;
6367 } /* LM_MulticastDel */
6368
6369
6370
6371 /******************************************************************************/
6372 /* Description: */
6373 /* */
6374 /* Return: */
6375 /******************************************************************************/
6376 LM_STATUS
6377 LM_MulticastClear(LM_DEVICE_BLOCK *pDevice)
6378 {
6379 int i;
6380
6381 for (i = 0; i < 4; i++)
6382 {
6383 pDevice->MulticastHash[i] = 0;
6384 }
6385 LM_SetReceiveMask(pDevice, pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
6386
6387 return LM_STATUS_SUCCESS;
6388 } /* LM_MulticastClear */
6389
6390
6391
6392 /******************************************************************************/
6393 /* Description: */
6394 /* */
6395 /* Return: */
6396 /******************************************************************************/
6397 LM_STATUS
6398 LM_SetMacAddress(
6399 PLM_DEVICE_BLOCK pDevice,
6400 PLM_UINT8 pMacAddress)
6401 {
6402 LM_UINT32 j;
6403
6404 for(j = 0; j < 4; j++)
6405 {
6406 REG_WR(pDevice, MacCtrl.MacAddr[j].High,
6407 (pMacAddress[0] << 8) | pMacAddress[1]);
6408 REG_WR(pDevice, MacCtrl.MacAddr[j].Low,
6409 (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
6410 (pMacAddress[4] << 8) | pMacAddress[5]);
6411 }
6412
6413 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) ||
6414 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704))
6415 {
6416 for (j = 0; j < 12; j++)
6417 {
6418 REG_WR(pDevice, MacCtrl.MacAddrExt[j].High,
6419 (pMacAddress[0] << 8) | pMacAddress[1]);
6420 REG_WR(pDevice, MacCtrl.MacAddrExt[j].Low,
6421 (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
6422 (pMacAddress[4] << 8) | pMacAddress[5]);
6423 }
6424 }
6425 return LM_STATUS_SUCCESS;
6426 }
6427
6428 LM_VOID
6429 LM_PhyTapPowerMgmt(LM_DEVICE_BLOCK *pDevice)
6430 {
6431 /* Turn off tap power management. */
6432 if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
6433 {
6434 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20);
6435 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
6436 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
6437 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
6438 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
6439 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
6440 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
6441 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
6442 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
6443 LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
6444 LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
6445
6446 MM_Wait(40);
6447 }
6448 }
6449
6450 /******************************************************************************/
6451 /* Description: */
6452 /* */
6453 /* Return: */
6454 /* LM_STATUS_LINK_ACTIVE */
6455 /* LM_STATUS_LINK_DOWN */
6456 /******************************************************************************/
6457 static LM_STATUS
6458 LM_InitBcm540xPhy(
6459 PLM_DEVICE_BLOCK pDevice)
6460 {
6461 LM_LINE_SPEED CurrentLineSpeed;
6462 LM_DUPLEX_MODE CurrentDuplexMode;
6463 LM_STATUS CurrentLinkStatus;
6464 LM_UINT32 Value32;
6465 LM_UINT32 j;
6466 robo_info_t *robo;
6467
6468 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02);
6469
6470 if ((pDevice->PhyFlags & PHY_RESET_ON_LINKDOWN) &&
6471 (pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE))
6472 {
6473 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6474 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6475 if(!(Value32 & PHY_STATUS_LINK_PASS))
6476 {
6477 LM_ResetPhy(pDevice);
6478 }
6479 }
6480 if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
6481 {
6482 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6483 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6484
6485 if(!pDevice->InitDone)
6486 {
6487 Value32 = 0;
6488 }
6489
6490 if(!(Value32 & PHY_STATUS_LINK_PASS))
6491 {
6492 LM_PhyTapPowerMgmt(pDevice);
6493
6494 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6495 for(j = 0; j < 1000; j++)
6496 {
6497 MM_Wait(10);
6498
6499 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6500 if(Value32 & PHY_STATUS_LINK_PASS)
6501 {
6502 MM_Wait(40);
6503 break;
6504 }
6505 }
6506
6507 if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV)
6508 {
6509 if(!(Value32 & PHY_STATUS_LINK_PASS) &&
6510 (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS))
6511 {
6512 LM_ResetPhy(pDevice);
6513 }
6514 }
6515 }
6516 }
6517 else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
6518 pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
6519 {
6520 LM_WritePhy(pDevice, 0x15, 0x0a75);
6521 LM_WritePhy(pDevice, 0x1c, 0x8c68);
6522 LM_WritePhy(pDevice, 0x1c, 0x8d68);
6523 LM_WritePhy(pDevice, 0x1c, 0x8c68);
6524 }
6525
6526 /* Acknowledge interrupts. */
6527 LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
6528 LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
6529
6530 /* Configure the interrupt mask. */
6531 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
6532 {
6533 LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE);
6534 }
6535
6536 /* Configure PHY led mode. */
6537 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
6538 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700))
6539 {
6540 if(pDevice->LedCtrl == LED_CTRL_PHY_MODE_1)
6541 {
6542 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
6543 BCM540X_EXT_CTRL_LINK3_LED_MODE);
6544 }
6545 else
6546 {
6547 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0);
6548 }
6549 }
6550 else if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5461_PHY_ID)
6551 {
6552 /*
6553 ** Set up the 'link' LED for the 4785+5461 combo,
6554 ** using the INTR/ENERGYDET pin (on the BCM4785 bringup board).
6555 */
6556 LM_WritePhy( pDevice,
6557 BCM546X_1c_SHADOW_REG,
6558 (BCM546X_1c_SPR_CTRL_2 | BCM546X_1c_WR_EN | BCM546X_1c_SP2_NRG_DET) );
6559
6560 /*
6561 ** Set up the LINK LED mode for the 4785+5461 combo,
6562 ** using the 5461 SLAVE/ANEN pin (on the BCM4785 bringup board) as
6563 ** active low link status (phy ready) feedback to the 4785
6564 */
6565 LM_WritePhy( pDevice,
6566 BCM546X_1c_SHADOW_REG,
6567 (BCM546X_1c_SPR_CTRL_1 | BCM546X_1c_WR_EN | BCM546X_1c_SP1_LINK_LED) );
6568 }
6569
6570 if (pDevice->PhyFlags & PHY_CAPACITIVE_COUPLING)
6571 {
6572 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4007);
6573 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &Value32);
6574 if (!(Value32 & BIT_10))
6575 {
6576 /* set the bit and re-link */
6577 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, Value32 | BIT_10);
6578 return LM_STATUS_LINK_SETTING_MISMATCH;
6579 }
6580 }
6581
6582 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
6583
6584 if(UNKNOWN_PHY_ID(pDevice->PhyId) && (pDevice->Flags & ROBO_SWITCH_FLAG)) {
6585 B57_INFO(("Force to active link of 1000 MBPS and full duplex mod.\n"));
6586 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6587
6588 /* Set the line speed based on the robo switch type */
6589 robo = ((PUM_DEVICE_BLOCK)pDevice)->robo;
6590 if (robo->devid == DEVID5325)
6591 {
6592 CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
6593 }
6594 else
6595 {
6596 CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
6597 }
6598 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6599
6600 /* Save line settings. */
6601 pDevice->LineSpeed = CurrentLineSpeed;
6602 pDevice->DuplexMode = CurrentDuplexMode;
6603 } else {
6604
6605 /* Get current link and duplex mode. */
6606 for(j = 0; j < 100; j++)
6607 {
6608 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6609 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
6610
6611 if(Value32 & PHY_STATUS_LINK_PASS)
6612 {
6613 break;
6614 }
6615 MM_Wait(40);
6616 }
6617
6618 if(Value32 & PHY_STATUS_LINK_PASS)
6619 {
6620
6621 /* Determine the current line and duplex settings. */
6622 LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
6623 for(j = 0; j < 2000; j++)
6624 {
6625 MM_Wait(10);
6626
6627 LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
6628 if(Value32)
6629 {
6630 break;
6631 }
6632 }
6633
6634 switch(Value32 & BCM540X_AUX_SPEED_MASK)
6635 {
6636 case BCM540X_AUX_10BASET_HD:
6637 CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
6638 CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
6639 break;
6640
6641 case BCM540X_AUX_10BASET_FD:
6642 CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
6643 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6644 break;
6645
6646 case BCM540X_AUX_100BASETX_HD:
6647 CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
6648 CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
6649 break;
6650
6651 case BCM540X_AUX_100BASETX_FD:
6652 CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
6653 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6654 break;
6655
6656 case BCM540X_AUX_100BASET_HD:
6657 CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
6658 CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
6659 break;
6660
6661 case BCM540X_AUX_100BASET_FD:
6662 CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
6663 CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
6664 break;
6665
6666 default:
6667
6668 CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN;
6669 CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
6670 break;
6671 }
6672
6673 /* Make sure we are in auto-neg mode. */
6674 for (j = 0; j < 200; j++)
6675 {
6676 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
6677 if(Value32 && Value32 != 0x7fff)
6678 {
6679 break;
6680 }
6681
6682 if(Value32 == 0 &&
6683 pDevice->RequestedLineSpeed == LM_LINE_SPEED_10MBPS &&
6684 pDevice->RequestedDuplexMode == LM_DUPLEX_MODE_HALF)
6685 {
6686 break;
6687 }
6688
6689 MM_Wait(10);
6690 }
6691
6692 /* Use the current line settings for "auto" mode. */
6693 if(pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)
6694 {
6695 if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)
6696 {
6697 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6698
6699 /* We may be exiting low power mode and the link is in */
6700 /* 10mb. In this case, we need to restart autoneg. */
6701
6702 if (LM_PhyAdvertiseAll(pDevice) != LM_STATUS_SUCCESS)
6703 {
6704 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6705 }
6706 }
6707 else
6708 {
6709 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6710 }
6711 }
6712 else
6713 {
6714 /* Force line settings. */
6715 /* Use the current setting if it matches the user's requested */
6716 /* setting. */
6717 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
6718 if((pDevice->LineSpeed == CurrentLineSpeed) &&
6719 (pDevice->DuplexMode == CurrentDuplexMode))
6720 {
6721 if ((pDevice->DisableAutoNeg &&
6722 !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) ||
6723 (!pDevice->DisableAutoNeg &&
6724 (Value32 & PHY_CTRL_AUTO_NEG_ENABLE)))
6725 {
6726 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
6727 }
6728 else
6729 {
6730 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6731 }
6732 }
6733 else
6734 {
6735 CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
6736 }
6737 }
6738
6739 /* Save line settings. */
6740 pDevice->LineSpeed = CurrentLineSpeed;
6741 pDevice->DuplexMode = CurrentDuplexMode;
6742 }
6743 }
6744
6745 return CurrentLinkStatus;
6746 } /* LM_InitBcm540xPhy */
6747
6748 /******************************************************************************/
6749 /* Description: */
6750 /* */
6751 /* Return: */
6752 /******************************************************************************/
6753 LM_STATUS
6754 LM_SetFlowControl(
6755 PLM_DEVICE_BLOCK pDevice,
6756 LM_UINT32 LocalPhyAd,
6757 LM_UINT32 RemotePhyAd)
6758 {
6759 LM_FLOW_CONTROL FlowCap;
6760
6761 /* Resolve flow control. */
6762 FlowCap = LM_FLOW_CONTROL_NONE;
6763
6764 /* See Table 28B-3 of 802.3ab-1999 spec. */
6765 if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE)
6766 {
6767 if(pDevice->PhyFlags & PHY_IS_FIBER){
6768 LocalPhyAd &= ~(PHY_AN_AD_ASYM_PAUSE |
6769 PHY_AN_AD_PAUSE_CAPABLE);
6770 RemotePhyAd &= ~(PHY_AN_AD_ASYM_PAUSE |
6771 PHY_AN_AD_PAUSE_CAPABLE);
6772
6773 if (LocalPhyAd & PHY_AN_AD_1000XPAUSE)
6774 LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
6775 if (LocalPhyAd & PHY_AN_AD_1000XPSE_ASYM)
6776 LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
6777 if (RemotePhyAd & PHY_AN_AD_1000XPAUSE)
6778 RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
6779 if (RemotePhyAd & PHY_AN_AD_1000XPSE_ASYM)
6780 RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
6781 }
6782
6783 if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE)
6784 {
6785 if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
6786 {
6787 if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
6788 {
6789 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
6790 LM_FLOW_CONTROL_RECEIVE_PAUSE;
6791 }
6792 else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)
6793 {
6794 FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE;
6795 }
6796 }
6797 else
6798 {
6799 if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
6800 {
6801 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
6802 LM_FLOW_CONTROL_RECEIVE_PAUSE;
6803 }
6804 }
6805 }
6806 else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
6807 {
6808 if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) &&
6809 (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE))
6810 {
6811 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE;
6812 }
6813 }
6814 }
6815 else
6816 {
6817 FlowCap = pDevice->FlowControlCap;
6818 }
6819
6820 pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
6821
6822 /* Enable/disable rx PAUSE. */
6823 pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL;
6824 if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE &&
6825 (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
6826 pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE))
6827 {
6828 pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
6829 pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL;
6830
6831 }
6832 REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
6833
6834 /* Enable/disable tx PAUSE. */
6835 pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL;
6836 if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE &&
6837 (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
6838 pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))
6839 {
6840 pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
6841 pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL;
6842
6843 }
6844 REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
6845
6846 return LM_STATUS_SUCCESS;
6847 }
6848
6849
6850 #ifdef INCLUDE_TBI_SUPPORT
6851 /******************************************************************************/
6852 /* Description: */
6853 /* */
6854 /* Return: */
6855 /******************************************************************************/
6856 STATIC LM_STATUS
6857 LM_InitBcm800xPhy(
6858 PLM_DEVICE_BLOCK pDevice)
6859 {
6860 LM_UINT32 Value32;
6861 LM_UINT32 j;
6862
6863
6864 Value32 = REG_RD(pDevice, MacCtrl.Status);
6865
6866 /* Reset the SERDES during init and when we have link. */
6867 if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED)
6868 {
6869 /* Set PLL lock range. */
6870 LM_WritePhy(pDevice, 0x16, 0x8007);
6871
6872 /* Software reset. */
6873 LM_WritePhy(pDevice, 0x00, 0x8000);
6874
6875 /* Wait for reset to complete. */
6876 for(j = 0; j < 500; j++)
6877 {
6878 MM_Wait(10);
6879 }
6880
6881 /* Config mode; seletct PMA/Ch 1 regs. */
6882 LM_WritePhy(pDevice, 0x10, 0x8411);
6883
6884 /* Enable auto-lock and comdet, select txclk for tx. */
6885 LM_WritePhy(pDevice, 0x11, 0x0a10);
6886
6887 LM_WritePhy(pDevice, 0x18, 0x00a0);
6888 LM_WritePhy(pDevice, 0x16, 0x41ff);
6889
6890 /* Assert and deassert POR. */
6891 LM_WritePhy(pDevice, 0x13, 0x0400);
6892 MM_Wait(40);
6893 LM_WritePhy(pDevice, 0x13, 0x0000);
6894
6895 LM_WritePhy(pDevice, 0x11, 0x0a50);
6896 MM_Wait(40);
6897 LM_WritePhy(pDevice, 0x11, 0x0a10);
6898
6899 /* Delay for signal to stabilize. */
6900 for(j = 0; j < 15000; j++)
6901 {
6902 MM_Wait(10);
6903 }
6904
6905 /* Deselect the channel register so we can read the PHY id later. */
6906 LM_WritePhy(pDevice, 0x10, 0x8011);
6907 }
6908
6909 return LM_STATUS_SUCCESS;
6910 }
6911
6912
6913
6914 /******************************************************************************/
6915 /* Description: */
6916 /* */
6917 /* Return: */
6918 /******************************************************************************/
6919 STATIC LM_STATUS
6920 LM_SetupFiberPhy(
6921 PLM_DEVICE_BLOCK pDevice)
6922 {
6923 LM_STATUS CurrentLinkStatus;
6924 AUTONEG_STATUS AnStatus = 0;
6925 LM_UINT32 Value32;
6926 LM_UINT32 Cnt;
6927 LM_UINT32 j, k;
6928 LM_UINT32 MacStatus, RemotePhyAd, LocalPhyAd;
6929 LM_FLOW_CONTROL PreviousFlowControl = pDevice->FlowControl;
6930
6931
6932 if (pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE)
6933 {
6934 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
6935 MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE);
6936 return LM_STATUS_SUCCESS;
6937 }
6938
6939
6940 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5704) &&
6941 (pDevice->LinkStatus == LM_STATUS_LINK_ACTIVE) && pDevice->InitDone)
6942 {
6943 MacStatus = REG_RD(pDevice, MacCtrl.Status);
6944 if ((MacStatus & (MAC_STATUS_PCS_SYNCED | MAC_STATUS_SIGNAL_DETECTED |
6945 MAC_STATUS_CFG_CHANGED | MAC_STATUS_RECEIVING_CFG))
6946 == (MAC_STATUS_PCS_SYNCED | MAC_STATUS_SIGNAL_DETECTED))
6947 {
6948
6949 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
6950 MAC_STATUS_CFG_CHANGED);
6951 return LM_STATUS_SUCCESS;
6952 }
6953 }
6954 pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK);
6955
6956 /* Initialize the send_config register. */
6957 REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
6958
6959 pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI;
6960 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
6961 MM_Wait(10);
6962
6963 /* Initialize the BCM8002 SERDES PHY. */
6964 switch(pDevice->PhyId & PHY_ID_MASK)
6965 {
6966 case PHY_BCM8002_PHY_ID:
6967 LM_InitBcm800xPhy(pDevice);
6968 break;
6969
6970 default:
6971 break;
6972 }
6973
6974 /* Enable link change interrupt. */
6975 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
6976
6977 /* Default to link down. */
6978 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
6979
6980 /* Get the link status. */
6981 MacStatus = REG_RD(pDevice, MacCtrl.Status);
6982
6983 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
6984 {
6985 LM_UINT32 SgDigCtrl, SgDigStatus;
6986 LM_UINT32 SerdesCfg = 0;
6987 LM_UINT32 ExpectedSgDigCtrl = 0;
6988 LM_UINT32 WorkAround = 0;
6989 LM_UINT32 PortA = 1;
6990
6991 if ((pDevice->ChipRevId != T3_CHIP_ID_5704_A0) &&
6992 (pDevice->ChipRevId != T3_CHIP_ID_5704_A1))
6993 {
6994 WorkAround = 1;
6995 if (REG_RD(pDevice, PciCfg.DualMacCtrl) & T3_DUAL_MAC_ID)
6996 {
6997 PortA = 0;
6998 }
6999
7000 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7001 {
7002 /* Save voltage reg bits & bits 14:0 */
7003 SerdesCfg = REG_RD(pDevice, MacCtrl.SerdesCfg) &
7004 (BIT_23 | BIT_22 | BIT_21 | BIT_20 | 0x7fff );
7005
7006 }
7007 else
7008 {
7009 /* preserve the voltage regulator bits */
7010 SerdesCfg = REG_RD(pDevice, MacCtrl.SerdesCfg) &
7011 (BIT_23 | BIT_22 | BIT_21 | BIT_20);
7012 }
7013 }
7014 SgDigCtrl = REG_RD(pDevice, MacCtrl.SgDigControl);
7015 if((pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) ||
7016 (pDevice->DisableAutoNeg == FALSE))
7017 {
7018
7019 ExpectedSgDigCtrl = 0x81388400;
7020 LocalPhyAd = GetPhyAdFlowCntrlSettings(pDevice);
7021 if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE)
7022 {
7023 ExpectedSgDigCtrl |= BIT_11;
7024 }
7025 if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
7026 {
7027 ExpectedSgDigCtrl |= BIT_12;
7028 }
7029 if (SgDigCtrl != ExpectedSgDigCtrl)
7030 {
7031 if (WorkAround)
7032 {
7033 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7034 {
7035 REG_WR(pDevice, MacCtrl.SerdesCfg, 0xc011000 | SerdesCfg);
7036 }
7037 else
7038 {
7039 REG_WR(pDevice, MacCtrl.SerdesCfg, 0xc011880 | SerdesCfg);
7040 }
7041 }
7042 REG_WR(pDevice, MacCtrl.SgDigControl, ExpectedSgDigCtrl |
7043 BIT_30);
7044 REG_RD_BACK(pDevice, MacCtrl.SgDigControl);
7045 MM_Wait(5);
7046 REG_WR(pDevice, MacCtrl.SgDigControl, ExpectedSgDigCtrl);
7047 pDevice->AutoNegJustInited = TRUE;
7048 }
7049 /* If autoneg is off, you only get SD when link is up */
7050 else if(MacStatus & (MAC_STATUS_PCS_SYNCED |
7051 MAC_STATUS_SIGNAL_DETECTED))
7052 {
7053 SgDigStatus = REG_RD(pDevice, MacCtrl.SgDigStatus);
7054 if ((SgDigStatus & BIT_1) &&
7055 (MacStatus & MAC_STATUS_PCS_SYNCED))
7056 {
7057 /* autoneg. completed */
7058 RemotePhyAd = 0;
7059 if(SgDigStatus & BIT_19)
7060 {
7061 RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
7062 }
7063
7064 if(SgDigStatus & BIT_20)
7065 {
7066 RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
7067 }
7068
7069 LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
7070 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7071 pDevice->AutoNegJustInited = FALSE;
7072 }
7073 else if (!(SgDigStatus & BIT_1))
7074 {
7075 if (pDevice->AutoNegJustInited == TRUE)
7076 {
7077 /* we may be checking too soon, so check again */
7078 /* at the next poll interval */
7079 pDevice->AutoNegJustInited = FALSE;
7080 }
7081 else
7082 {
7083 /* autoneg. failed */
7084 if (WorkAround)
7085 {
7086 if (PortA)
7087 {
7088 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7089 {
7090 REG_WR(pDevice, MacCtrl.SerdesCfg,
7091 0xc010000 | (SerdesCfg & ~0x00001000));
7092 }
7093 else
7094 {
7095 REG_WR(pDevice, MacCtrl.SerdesCfg,
7096 0xc010880 | SerdesCfg);
7097 }
7098 }
7099 else
7100 {
7101 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7102 {
7103 REG_WR(pDevice, MacCtrl.SerdesCfg,
7104 0x4010000 | (SerdesCfg & ~0x00001000));
7105 }
7106 else
7107 {
7108 REG_WR(pDevice, MacCtrl.SerdesCfg,
7109 0x4010880 | SerdesCfg);
7110 }
7111 }
7112 }
7113 /* turn off autoneg. to allow traffic to pass */
7114 REG_WR(pDevice, MacCtrl.SgDigControl, 0x01388400);
7115 REG_RD_BACK(pDevice, MacCtrl.SgDigControl);
7116 MM_Wait(40);
7117 MacStatus = REG_RD(pDevice, MacCtrl.Status);
7118 if ((MacStatus & MAC_STATUS_PCS_SYNCED) && !(MacStatus & MAC_STATUS_RECEIVING_CFG))
7119 {
7120 LM_SetFlowControl(pDevice, 0, 0);
7121 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7122 }
7123 }
7124 }
7125 }
7126 }
7127 else
7128 {
7129 if (SgDigCtrl & BIT_31) {
7130 if (WorkAround)
7131 {
7132 if (PortA)
7133 {
7134
7135 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7136 {
7137 REG_WR(pDevice, MacCtrl.SerdesCfg,
7138 0xc010000 | (SerdesCfg & ~0x00001000));
7139 }
7140 else
7141 {
7142 REG_WR(pDevice, MacCtrl.SerdesCfg,
7143 0xc010880 | SerdesCfg);
7144 }
7145 }
7146 else
7147 {
7148 if(pDevice->TbiFlags & TBI_DO_PREEMPHASIS)
7149 {
7150 REG_WR(pDevice, MacCtrl.SerdesCfg,
7151 0x4010000 | (SerdesCfg & ~0x00001000));
7152 }
7153 else
7154 {
7155 REG_WR(pDevice, MacCtrl.SerdesCfg,
7156 0x4010880 | SerdesCfg);
7157 }
7158 }
7159 }
7160 REG_WR(pDevice, MacCtrl.SgDigControl, 0x01388400);
7161 }
7162 if(MacStatus & MAC_STATUS_PCS_SYNCED)
7163 {
7164 LM_SetFlowControl(pDevice, 0, 0);
7165 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7166 }
7167 }
7168 }
7169 else if(MacStatus & MAC_STATUS_PCS_SYNCED)
7170 {
7171 if((pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) ||
7172 (pDevice->DisableAutoNeg == FALSE))
7173 {
7174 /* auto-negotiation mode. */
7175 /* Initialize the autoneg default capaiblities. */
7176 AutonegInit(&pDevice->AnInfo);
7177
7178 /* Set the context pointer to point to the main device structure. */
7179 pDevice->AnInfo.pContext = pDevice;
7180
7181 /* Setup flow control advertisement register. */
7182 Value32 = GetPhyAdFlowCntrlSettings(pDevice);
7183 if(Value32 & PHY_AN_AD_PAUSE_CAPABLE)
7184 {
7185 pDevice->AnInfo.mr_adv_sym_pause = 1;
7186 }
7187 else
7188 {
7189 pDevice->AnInfo.mr_adv_sym_pause = 0;
7190 }
7191
7192 if(Value32 & PHY_AN_AD_ASYM_PAUSE)
7193 {
7194 pDevice->AnInfo.mr_adv_asym_pause = 1;
7195 }
7196 else
7197 {
7198 pDevice->AnInfo.mr_adv_asym_pause = 0;
7199 }
7200
7201 /* Try to autoneg up to six times. */
7202 if (pDevice->IgnoreTbiLinkChange)
7203 {
7204 Cnt = 1;
7205 }
7206 else
7207 {
7208 Cnt = 6;
7209 }
7210 for (j = 0; j < Cnt; j++)
7211 {
7212 REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
7213
7214 Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK;
7215 REG_WR(pDevice, MacCtrl.Mode, Value32);
7216 REG_RD_BACK(pDevice, MacCtrl.Mode);
7217 MM_Wait(20);
7218
7219 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
7220 MAC_MODE_SEND_CONFIGS);
7221 REG_RD_BACK(pDevice, MacCtrl.Mode);
7222
7223 MM_Wait(20);
7224
7225 pDevice->AnInfo.State = AN_STATE_UNKNOWN;
7226 pDevice->AnInfo.CurrentTime_us = 0;
7227
7228 REG_WR(pDevice, Grc.Timer, 0);
7229 for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) &&
7230 (k < 75000); k++)
7231 {
7232 AnStatus = Autoneg8023z(&pDevice->AnInfo);
7233
7234 if((AnStatus == AUTONEG_STATUS_DONE) ||
7235 (AnStatus == AUTONEG_STATUS_FAILED))
7236 {
7237 break;
7238 }
7239
7240 pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer);
7241
7242 }
7243 if((AnStatus == AUTONEG_STATUS_DONE) ||
7244 (AnStatus == AUTONEG_STATUS_FAILED))
7245 {
7246 break;
7247 }
7248 if (j >= 1)
7249 {
7250 if (!(REG_RD(pDevice, MacCtrl.Status) &
7251 MAC_STATUS_PCS_SYNCED)) {
7252 break;
7253 }
7254 }
7255 }
7256
7257 /* Stop sending configs. */
7258 MM_AnTxIdle(&pDevice->AnInfo);
7259
7260 /* Resolve flow control settings. */
7261 if((AnStatus == AUTONEG_STATUS_DONE) &&
7262 pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok &&
7263 pDevice->AnInfo.mr_lp_adv_full_duplex)
7264 {
7265 LM_UINT32 RemotePhyAd;
7266 LM_UINT32 LocalPhyAd;
7267
7268 LocalPhyAd = 0;
7269 if(pDevice->AnInfo.mr_adv_sym_pause)
7270 {
7271 LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
7272 }
7273
7274 if(pDevice->AnInfo.mr_adv_asym_pause)
7275 {
7276 LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
7277 }
7278
7279 RemotePhyAd = 0;
7280 if(pDevice->AnInfo.mr_lp_adv_sym_pause)
7281 {
7282 RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
7283 }
7284
7285 if(pDevice->AnInfo.mr_lp_adv_asym_pause)
7286 {
7287 RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
7288 }
7289
7290 LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
7291
7292 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7293 }
7294 else
7295 {
7296 LM_SetFlowControl(pDevice, 0, 0);
7297 }
7298 for (j = 0; j < 30; j++)
7299 {
7300 MM_Wait(20);
7301 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7302 MAC_STATUS_CFG_CHANGED);
7303 REG_RD_BACK(pDevice, MacCtrl.Status);
7304 MM_Wait(20);
7305 if ((REG_RD(pDevice, MacCtrl.Status) &
7306 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
7307 break;
7308 }
7309 if (pDevice->TbiFlags & TBI_POLLING_FLAGS)
7310 {
7311 Value32 = REG_RD(pDevice, MacCtrl.Status);
7312 if (Value32 & MAC_STATUS_RECEIVING_CFG)
7313 {
7314 pDevice->IgnoreTbiLinkChange = TRUE;
7315 }
7316 else if (pDevice->TbiFlags & TBI_POLLING_INTR_FLAG)
7317 {
7318 pDevice->IgnoreTbiLinkChange = FALSE;
7319 }
7320 }
7321 Value32 = REG_RD(pDevice, MacCtrl.Status);
7322 if (CurrentLinkStatus == LM_STATUS_LINK_DOWN &&
7323 (Value32 & MAC_STATUS_PCS_SYNCED) &&
7324 ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0))
7325 {
7326 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7327 }
7328 }
7329 else
7330 {
7331 /* We are forcing line speed. */
7332 pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
7333 LM_SetFlowControl(pDevice, 0, 0);
7334
7335 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7336 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
7337 MAC_MODE_SEND_CONFIGS);
7338 }
7339 }
7340 /* Set the link polarity bit. */
7341 pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
7342 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7343
7344 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
7345 (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
7346
7347 for (j = 0; j < 100; j++)
7348 {
7349 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7350 MAC_STATUS_CFG_CHANGED);
7351 REG_RD_BACK(pDevice, MacCtrl.Status);
7352 MM_Wait(5);
7353 if ((REG_RD(pDevice, MacCtrl.Status) &
7354 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
7355 break;
7356 }
7357
7358 Value32 = REG_RD(pDevice, MacCtrl.Status);
7359 if((Value32 & MAC_STATUS_PCS_SYNCED) == 0)
7360 {
7361 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7362 if (pDevice->DisableAutoNeg == FALSE)
7363 {
7364 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
7365 MAC_MODE_SEND_CONFIGS);
7366 REG_RD_BACK(pDevice, MacCtrl.Mode);
7367 MM_Wait(1);
7368 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7369 }
7370 }
7371
7372 /* Initialize the current link status. */
7373 if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7374 {
7375 pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
7376 pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
7377 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl |
7378 LED_CTRL_OVERRIDE_LINK_LED |
7379 LED_CTRL_1000MBPS_LED_ON);
7380 }
7381 else
7382 {
7383 pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN;
7384 pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN;
7385 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl |
7386 LED_CTRL_OVERRIDE_LINK_LED |
7387 LED_CTRL_OVERRIDE_TRAFFIC_LED);
7388 }
7389
7390 /* Indicate link status. */
7391 if ((pDevice->LinkStatus != CurrentLinkStatus) ||
7392 ((CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
7393 (PreviousFlowControl != pDevice->FlowControl)))
7394 {
7395 pDevice->LinkStatus = CurrentLinkStatus;
7396 MM_IndicateStatus(pDevice, CurrentLinkStatus);
7397 }
7398
7399 return LM_STATUS_SUCCESS;
7400 }
7401 #endif /* INCLUDE_TBI_SUPPORT */
7402
7403
7404 /******************************************************************************/
7405 /* Description: */
7406 /* */
7407 /* Return: */
7408 /******************************************************************************/
7409 LM_STATUS
7410 LM_SetupCopperPhy(
7411 PLM_DEVICE_BLOCK pDevice)
7412 {
7413 LM_STATUS CurrentLinkStatus;
7414 LM_UINT32 Value32;
7415
7416 /* Assume there is not link first. */
7417 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7418
7419 /* Disable phy link change attention. */
7420 REG_WR(pDevice, MacCtrl.MacEvent, 0);
7421
7422 /* Clear link change attention. */
7423 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7424 MAC_STATUS_CFG_CHANGED | MAC_STATUS_MI_COMPLETION |
7425 MAC_STATUS_LINK_STATE_CHANGED);
7426
7427 /* Disable auto-polling for the moment. */
7428 pDevice->MiMode = 0xc0000;
7429 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
7430 REG_RD_BACK(pDevice, MacCtrl.MiMode);
7431 MM_Wait(40);
7432
7433 /* Determine the requested line speed and duplex. */
7434 pDevice->OldLineSpeed = pDevice->LineSpeed;
7435 /* Set line and duplex only if we don't have a Robo switch */
7436 if (!(pDevice->Flags & ROBO_SWITCH_FLAG)) {
7437 pDevice->LineSpeed = pDevice->RequestedLineSpeed;
7438 pDevice->DuplexMode = pDevice->RequestedDuplexMode;
7439 }
7440
7441 /* Set the phy to loopback mode. */
7442 if ((pDevice->LoopBackMode == LM_PHY_LOOP_BACK_MODE) ||
7443 (pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE))
7444 {
7445 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
7446 if(!(Value32 & PHY_CTRL_LOOPBACK_MODE) &&
7447 (pDevice->LoopBackMode == LM_PHY_LOOP_BACK_MODE))
7448 {
7449 /* Disable link change and PHY interrupts. */
7450 REG_WR(pDevice, MacCtrl.MacEvent, 0);
7451
7452 /* Clear link change attention. */
7453 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7454 MAC_STATUS_CFG_CHANGED);
7455
7456 LM_WritePhy(pDevice, PHY_CTRL_REG, 0x4140);
7457 MM_Wait(40);
7458
7459 pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
7460 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
7461 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703 ||
7462 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704 ||
7463 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705 ||
7464 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 &&
7465 (pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID))
7466 {
7467 pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
7468 }
7469
7470 /* Prevent the interrupt handling from being called. */
7471 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
7472 (pDevice->pStatusBlkVirt->Status &
7473 ~STATUS_BLOCK_LINK_CHANGED_STATUS);
7474
7475 /* GMII interface. */
7476 pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
7477 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7478 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7479 REG_RD_BACK(pDevice, MacCtrl.Mode);
7480 MM_Wait(40);
7481
7482 /* Configure PHY led mode. */
7483 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
7484 (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700))
7485 {
7486 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
7487 BCM540X_EXT_CTRL_LINK3_LED_MODE);
7488 MM_Wait(40);
7489 }
7490
7491 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
7492 {
7493 int j = 0;
7494
7495 while (REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE)
7496 {
7497 MM_Wait(40);
7498 j++;
7499 if (j > 20)
7500 break;
7501 }
7502
7503 Value32 = DMA_WRITE_MODE_ENABLE |
7504 DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
7505 DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
7506 DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
7507 DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
7508 DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
7509 DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
7510 DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
7511 DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
7512 REG_WR(pDevice, DmaWrite.Mode, Value32);
7513 }
7514 }
7515
7516 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
7517 MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE);
7518
7519 return LM_STATUS_SUCCESS;
7520 }
7521
7522 /* For Robo switch read PHY_CTRL_REG value as zero */
7523 if (pDevice->Flags & ROBO_SWITCH_FLAG)
7524 Value32 = 0;
7525 else
7526 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
7527
7528 if(Value32 & PHY_CTRL_LOOPBACK_MODE)
7529 {
7530 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7531
7532 /* Re-enable link change interrupt. This was disabled when we */
7533 /* enter loopback mode. */
7534 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
7535 {
7536 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT);
7537 }
7538 else
7539 {
7540 REG_WR(pDevice, MacCtrl.MacEvent,
7541 MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
7542 }
7543 }
7544 else
7545 {
7546 /* Initialize the phy chip. */
7547 CurrentLinkStatus = LM_InitBcm540xPhy(pDevice);
7548 }
7549
7550 if(CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH)
7551 {
7552 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7553 }
7554
7555 /* Setup flow control. */
7556 pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
7557 if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7558 {
7559 LM_FLOW_CONTROL FlowCap; /* Flow control capability. */
7560
7561 FlowCap = LM_FLOW_CONTROL_NONE;
7562
7563 if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL)
7564 {
7565 if(pDevice->DisableAutoNeg == FALSE ||
7566 pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)
7567 {
7568 LM_UINT32 ExpectedPhyAd;
7569 LM_UINT32 LocalPhyAd;
7570 LM_UINT32 RemotePhyAd;
7571
7572 LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd);
7573 pDevice->advertising = LocalPhyAd;
7574 LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE);
7575
7576 ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice);
7577
7578 if(LocalPhyAd != ExpectedPhyAd)
7579 {
7580 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
7581 }
7582 else
7583 {
7584 LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG,
7585 &RemotePhyAd);
7586
7587 LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
7588 }
7589 }
7590 else
7591 {
7592 pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
7593 LM_SetFlowControl(pDevice, 0, 0);
7594 }
7595 }
7596 }
7597
7598 if(CurrentLinkStatus == LM_STATUS_LINK_DOWN)
7599 {
7600 LM_ForceAutoNeg(pDevice);
7601
7602 /* If we force line speed, we make get link right away. */
7603 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
7604 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
7605 if(Value32 & PHY_STATUS_LINK_PASS)
7606 {
7607 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
7608 }
7609 }
7610
7611 /* GMII interface. */
7612 pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
7613 if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7614 {
7615 if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS ||
7616 pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
7617 {
7618 pDevice->MacMode |= MAC_MODE_PORT_MODE_MII;
7619 }
7620 else
7621 {
7622 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7623 }
7624 }
7625 else {
7626 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7627 }
7628
7629 /* In order for the 5750 core in BCM4785 chip to work properly
7630 * in RGMII mode, the Led Control Register must be set up.
7631 */
7632 if (pDevice->Flags & RGMII_MODE_FLAG)
7633 {
7634 LM_UINT32 LedCtrl_Reg;
7635
7636 LedCtrl_Reg = REG_RD(pDevice, MacCtrl.LedCtrl);
7637 LedCtrl_Reg &= ~(LED_CTRL_1000MBPS_LED_ON | LED_CTRL_100MBPS_LED_ON);
7638
7639 if(pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
7640 LedCtrl_Reg |= LED_CTRL_OVERRIDE_LINK_LED;
7641 else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS)
7642 LedCtrl_Reg |= (LED_CTRL_OVERRIDE_LINK_LED | LED_CTRL_100MBPS_LED_ON);
7643 else /* LM_LINE_SPEED_1000MBPS */
7644 LedCtrl_Reg |= (LED_CTRL_OVERRIDE_LINK_LED | LED_CTRL_1000MBPS_LED_ON);
7645
7646 REG_WR(pDevice, MacCtrl.LedCtrl, LedCtrl_Reg);
7647
7648 MM_Wait(40);
7649 }
7650
7651 /* Set the MAC to operate in the appropriate duplex mode. */
7652 pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX;
7653 if(pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)
7654 {
7655 pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
7656 }
7657
7658 /* Set the link polarity bit. */
7659 pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
7660 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
7661 {
7662 if((pDevice->LedCtrl == LED_CTRL_PHY_MODE_2) ||
7663 (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE &&
7664 pDevice->LineSpeed == LM_LINE_SPEED_10MBPS))
7665 {
7666 pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
7667 }
7668 }
7669 else
7670 {
7671 if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
7672 {
7673 pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
7674 }
7675 }
7676
7677 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7678
7679 /* Enable auto polling. */
7680 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
7681 {
7682 pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE;
7683 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
7684 }
7685 /* if using MAC led mode and not using auto polling, need to configure */
7686 /* mi status register */
7687 else if ((pDevice->LedCtrl &
7688 (LED_CTRL_PHY_MODE_1 | LED_CTRL_PHY_MODE_2)) == 0)
7689 {
7690 if (CurrentLinkStatus != LM_STATUS_LINK_ACTIVE)
7691 {
7692 REG_WR(pDevice, MacCtrl.MiStatus, 0);
7693 }
7694 else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
7695 {
7696 REG_WR(pDevice, MacCtrl.MiStatus,
7697 MI_STATUS_ENABLE_LINK_STATUS_ATTN | MI_STATUS_10MBPS);
7698 }
7699 else
7700 {
7701 REG_WR(pDevice, MacCtrl.MiStatus,
7702 MI_STATUS_ENABLE_LINK_STATUS_ATTN);
7703 }
7704 }
7705
7706 /* Enable phy link change attention. */
7707 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
7708 {
7709 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT);
7710 }
7711 else
7712 {
7713 REG_WR(pDevice, MacCtrl.MacEvent,
7714 MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
7715 }
7716 if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) &&
7717 (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
7718 (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
7719 (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) &&
7720 (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) ||
7721 !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)))
7722 {
7723 MM_Wait(120);
7724 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7725 MAC_STATUS_CFG_CHANGED);
7726 MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX,
7727 T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE);
7728 }
7729
7730 /* Indicate link status. */
7731 if (pDevice->LinkStatus != CurrentLinkStatus) {
7732 pDevice->LinkStatus = CurrentLinkStatus;
7733 MM_IndicateStatus(pDevice, CurrentLinkStatus);
7734 }
7735
7736 return LM_STATUS_SUCCESS;
7737 } /* LM_SetupCopperPhy */
7738
7739
7740 void
7741 LM_5714_FamForceFiber(
7742 PLM_DEVICE_BLOCK pDevice)
7743 {
7744 LM_UINT32 Creg, new_bmcr;
7745 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Creg);
7746
7747 new_bmcr = Creg & ~PHY_CTRL_AUTO_NEG_ENABLE;
7748
7749 if ( pDevice->RequestedDuplexMode == 0 ||
7750 pDevice->RequestedDuplexMode == LM_DUPLEX_MODE_FULL){
7751
7752 new_bmcr |= PHY_CTRL_FULL_DUPLEX_MODE;
7753 }
7754
7755 if(Creg == new_bmcr)
7756 return;
7757
7758 new_bmcr |= PHY_CTRL_SPEED_SELECT_1000MBPS; /* Reserve bit */
7759
7760 /* Force a linkdown */
7761 LM_WritePhy(pDevice, PHY_AN_AD_REG, 0);
7762 LM_WritePhy(pDevice, PHY_CTRL_REG, new_bmcr |
7763 PHY_CTRL_RESTART_AUTO_NEG |
7764 PHY_CTRL_AUTO_NEG_ENABLE |
7765 PHY_CTRL_SPEED_SELECT_1000MBPS);
7766 MM_Wait(10);
7767
7768 /* Force it */
7769 LM_WritePhy(pDevice, PHY_CTRL_REG, new_bmcr);
7770 MM_Wait(10);
7771
7772 return;
7773
7774 }/* LM_5714_FamForceFiber */
7775
7776
7777 void
7778 LM_5714_FamGoFiberAutoNeg(
7779 PLM_DEVICE_BLOCK pDevice)
7780 {
7781 LM_UINT32 adv,Creg,new;
7782
7783 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Creg);
7784 LM_ReadPhy(pDevice,PHY_AN_AD_REG, &adv);
7785
7786 new = adv & ~( PHY_AN_AD_1000XFULL |
7787 PHY_AN_AD_1000XHALF |
7788 PHY_AN_AD_1000XPAUSE |
7789 PHY_AN_AD_1000XPSE_ASYM |
7790 0x1f);
7791
7792 new |= PHY_AN_AD_1000XPAUSE;
7793
7794 new |= PHY_AN_AD_1000XFULL;
7795 new |= PHY_AN_AD_1000XHALF;
7796
7797 if ((new != adv) || !(Creg & PHY_CTRL_AUTO_NEG_ENABLE)){
7798 LM_WritePhy(pDevice, PHY_AN_AD_REG, new);
7799 MM_Wait(5);
7800 pDevice->AutoNegJustInited=1;
7801 LM_WritePhy(pDevice, PHY_CTRL_REG, (Creg |
7802 PHY_CTRL_RESTART_AUTO_NEG |
7803 PHY_CTRL_SPEED_SELECT_1000MBPS |
7804 PHY_CTRL_AUTO_NEG_ENABLE) );
7805 }
7806
7807 return;
7808 } /* 5714_FamGoFiberAutoNeg */
7809
7810
7811 void
7812 LM_5714_FamDoFiberLoopback(PLM_DEVICE_BLOCK pDevice)
7813 {
7814 LM_UINT32 Value32;
7815
7816 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
7817
7818 if( !(Value32 & PHY_CTRL_LOOPBACK_MODE) )
7819 {
7820 LM_WritePhy(pDevice, PHY_CTRL_REG, 0x4140);
7821
7822 /* Prevent the interrupt handling from being called. */
7823 pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
7824 (pDevice->pStatusBlkVirt->Status &
7825 ~STATUS_BLOCK_LINK_CHANGED_STATUS);
7826 }
7827
7828 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
7829 MM_IndicateStatus(pDevice, LM_STATUS_LINK_ACTIVE);
7830
7831 return;
7832
7833 }/* 5714_FamDoFiberLoopBack */
7834
7835
7836 /******************************************************************************/
7837 /* Description: */
7838 /* */
7839 /* Return: */
7840 /******************************************************************************/
7841
7842 LM_STATUS
7843 LM_SetupNewFiberPhy(
7844 PLM_DEVICE_BLOCK pDevice)
7845 {
7846 LM_STATUS LmStatus = LM_STATUS_SUCCESS;
7847 LM_UINT32 Creg,Sreg,rsav;
7848
7849 rsav = pDevice->LinkStatus;
7850
7851 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7852 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7853 MM_Wait(40);
7854
7855 /* Disable phy link change attention. */
7856 REG_WR(pDevice, MacCtrl.MacEvent, 0);
7857
7858 /* Clear link change attention. */
7859 REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
7860 MAC_STATUS_CFG_CHANGED | MAC_STATUS_MI_COMPLETION |
7861 MAC_STATUS_LINK_STATE_CHANGED);
7862
7863
7864 if( (pDevice->PhyFlags & PHY_FIBER_FALLBACK) &&
7865 ( pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) ){
7866
7867 /* do nothing */
7868 }else if ( pDevice->LoopBackMode == LM_MAC_LOOP_BACK_MODE){
7869
7870 LM_5714_FamDoFiberLoopback(pDevice);
7871 goto fiberloopbackreturn;
7872
7873 } else if( pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) {
7874
7875 LM_5714_FamGoFiberAutoNeg(pDevice);
7876
7877
7878 }else {
7879
7880 LM_5714_FamForceFiber(pDevice);
7881 }
7882 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Sreg);
7883 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Sreg);
7884
7885 if(Sreg & PHY_STATUS_LINK_PASS){
7886
7887 pDevice->LinkStatus = LM_STATUS_LINK_ACTIVE;
7888 pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
7889
7890 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Creg);
7891
7892 if(Creg & PHY_CTRL_FULL_DUPLEX_MODE) {
7893 pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
7894 }else{
7895 pDevice->DuplexMode = LM_DUPLEX_MODE_HALF;
7896 pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
7897 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7898 }
7899
7900 if(Creg & PHY_CTRL_AUTO_NEG_ENABLE){
7901 LM_UINT32 ours,partner;
7902
7903 LM_ReadPhy(pDevice,PHY_AN_AD_REG, &ours);
7904 LM_ReadPhy(pDevice,PHY_LINK_PARTNER_ABILITY_REG, &partner);
7905 LM_SetFlowControl(pDevice, ours, partner);
7906 }
7907
7908 }else{
7909 pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
7910 pDevice->LineSpeed = 0;
7911 }
7912
7913 if(rsav != pDevice->LinkStatus)
7914 MM_IndicateStatus(pDevice, pDevice->LinkStatus);
7915
7916 fiberloopbackreturn:
7917 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
7918 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
7919 MM_Wait(40);
7920 /* Enable link change interrupt. */
7921 REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
7922
7923 return LmStatus;
7924 } /* Setup New phy */
7925
7926 void
7927 LM_5714_FamFiberCheckLink(
7928 PLM_DEVICE_BLOCK pDevice)
7929 {
7930
7931 if(pDevice->AutoNegJustInited){
7932 pDevice->AutoNegJustInited=0;
7933 return;
7934 }
7935
7936 if ((pDevice->LinkStatus != LM_STATUS_LINK_ACTIVE) &&
7937 (pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO) &&
7938 !(pDevice->PhyFlags & PHY_FIBER_FALLBACK)){
7939 LM_UINT32 bmcr;
7940
7941 LM_ReadPhy(pDevice, PHY_CTRL_REG, &bmcr);
7942 if (bmcr & PHY_CTRL_AUTO_NEG_ENABLE) {
7943 LM_UINT32 phy1, phy2;
7944
7945 LM_WritePhy(pDevice, 0x1c, 0x7c00);
7946 LM_ReadPhy(pDevice, 0x1c, &phy1);
7947
7948 LM_WritePhy(pDevice, 0x17, 0x0f01);
7949 LM_ReadPhy(pDevice, 0x15, &phy2);
7950 LM_ReadPhy(pDevice, 0x15, &phy2);
7951
7952 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
7953
7954 /* We have signal detect and not receiving
7955 * configs.
7956 */
7957
7958 pDevice->PhyFlags |= PHY_FIBER_FALLBACK;
7959 LM_5714_FamForceFiber(pDevice);
7960 }
7961 }
7962 }
7963 else if ( (pDevice->PhyFlags & PHY_FIBER_FALLBACK) &&
7964 (pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)) {
7965 LM_UINT32 phy2;
7966
7967 LM_WritePhy(pDevice, 0x17, 0x0f01);
7968 LM_ReadPhy(pDevice, 0x15, &phy2);
7969 if (phy2 & 0x20) {
7970 /* Receiving configs. */
7971
7972 pDevice->PhyFlags &= ~PHY_FIBER_FALLBACK;
7973 LM_5714_FamGoFiberAutoNeg(pDevice);
7974 }
7975 }
7976
7977 } /* LM_5714_FamFiberCheckLink */
7978
7979
7980 /******************************************************************************/
7981 /* Description: */
7982 /* */
7983 /* Return: */
7984 /******************************************************************************/
7985 LM_STATUS
7986 LM_SetupPhy(
7987 PLM_DEVICE_BLOCK pDevice)
7988 {
7989 LM_STATUS LmStatus;
7990 LM_UINT32 Value32;
7991
7992 if(pDevice->PhyFlags & PHY_IS_FIBER)
7993 {
7994 LmStatus = LM_SetupNewFiberPhy(pDevice);
7995 }else
7996 #ifdef INCLUDE_TBI_SUPPORT
7997 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
7998 {
7999 LmStatus = LM_SetupFiberPhy(pDevice);
8000 }
8001 else
8002 #endif /* INCLUDE_TBI_SUPPORT */
8003 {
8004 LmStatus = LM_SetupCopperPhy(pDevice);
8005 }
8006 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
8007 {
8008 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
8009 {
8010 Value32 = REG_RD(pDevice, PciCfg.PciState);
8011 REG_WR(pDevice, PciCfg.PciState,
8012 Value32 | T3_PCI_STATE_RETRY_SAME_DMA);
8013 }
8014 }
8015 if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
8016 (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF))
8017 {
8018 REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff);
8019 }
8020 else
8021 {
8022 REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
8023 }
8024 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
8025 {
8026 if (pDevice->LinkStatus == LM_STATUS_LINK_DOWN)
8027 {
8028 REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks, 0);
8029 }
8030 else
8031 {
8032 REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks,
8033 pDevice->StatsCoalescingTicks);
8034 }
8035 }
8036
8037 return LmStatus;
8038 }
8039
8040
8041 /* test data pattern */
8042 static LM_UINT32 pattern[4][6] = {
8043 /* For 5703/04, each DFE TAP has 21-bits (low word 15, hi word 6)
8044 For 5705 , each DFE TAP has 19-bits (low word 15, hi word 4)
8045 For simplicity, we check only 19-bits, so we don't have to
8046 distinguish which chip it is.
8047 the LO word contains 15 bits, make sure pattern data is < 0x7fff
8048 the HI word contains 6 bits, make sure pattern data is < 0x003f */
8049 {0x00005555, 0x00000005, /* ch0, TAP 0, LO/HI pattern */
8050 0x00002aaa, 0x0000000a, /* ch0, TAP 1, LO/HI pattern */
8051 0x00003456, 0x00000003}, /* ch0, TAP 2, LO/HI pattern */
8052
8053 {0x00002aaa, 0x0000000a, /* ch1, TAP 0, LO/HI pattern */
8054 0x00003333, 0x00000003, /* ch1, TAP 1, LO/HI pattern */
8055 0x0000789a, 0x00000005}, /* ch1, TAP 2, LO/HI pattern */
8056
8057 {0x00005a5a, 0x00000005, /* ch2, TAP 0, LO/HI pattern */
8058 0x00002a6a, 0x0000000a, /* ch2, TAP 1, LO/HI pattern */
8059 0x00001bcd, 0x00000003}, /* ch2, TAP 2, LO/HI pattern */
8060
8061 {0x00002a5a, 0x0000000a, /* ch3, TAP 0, LO/HI pattern */
8062 0x000033c3, 0x00000003, /* ch3, TAP 1, LO/HI pattern */
8063 0x00002ef1, 0x00000005}, /* ch3, TAP 2, LO/HI pattern */
8064 };
8065
8066 /********************************************************/
8067 /* Routine to wait for PHY Macro Command to complete */
8068 /* */
8069 /* If PHY's Macro operation keeps stay busy, nothing we */
8070 /* can do anyway. The timeout is there so we won't */
8071 /* stay in this routine indefinitly. */
8072 /********************************************************/
8073 static LM_UINT32 LM_wait_macro_done(LM_DEVICE_BLOCK *pDevice);
8074
8075 static LM_UINT32
8076 LM_wait_macro_done(LM_DEVICE_BLOCK *pDevice)
8077 {
8078 LM_UINT32 timeout;
8079 LM_UINT32 val32;
8080
8081 timeout = 100;
8082 while (timeout--)
8083 {
8084 /* make sure the MACRO operation is complete */
8085 LM_ReadPhy(pDevice, 0x16, &val32);
8086 if ((val32 & 0x1000) == 0) break;
8087 }
8088
8089 return( timeout > 0 );
8090 }
8091
8092 /********************************************************/
8093 /* This routine resets the PHY on following chips: */
8094 /* 5703, 04, CIOB-E and 5705 */
8095 /* */
8096 /* This routine will issue PHY_RESET and check if */
8097 /* the reset is sucessful. If not, another PHY RESET */
8098 /* will be issued, until max "retry" reaches */
8099 /* */
8100 /* Input: */
8101 /* pDevice - device's context */
8102 /* retry - number of retries */
8103 /* reset - TRUE=will cause a PHY reset initially */
8104 /* FALSE = will not issue a PHY reset */
8105 /* unless TAP lockup detected */
8106 /* */
8107 /* Output: */
8108 /* TRUE - PHY Reset is done sucessfully */
8109 /* FALSE - PHY Reset had failed, after "retry" */
8110 /* has reached */
8111 /* */
8112 /* Dependencies: */
8113 /* void LM_wait_macro_done() */
8114 /* LM_UINT32 pattern[] */
8115 /* */
8116 /* Usage: */
8117 /* a. Before calling this routine, caller must */
8118 /* determine if the chip is a 5702/03/04 or */
8119 /* CIOB-E, and only call this routine if the */
8120 /* is one of these. */
8121 /* or its derivatives. */
8122 /* b. Instead of using MII register write to reset */
8123 /* the PHY, call this routine instead */
8124 /* c. Upon return from this routine, check return */
8125 /* value (TRUE/FALSE) to determine if PHY reset */
8126 /* is successful of not and "optionally" take */
8127 /* appropriate action (such as: event log) */
8128 /* d. Regardless of the return TRUE or FALSE, */
8129 /* proceed with PHY setup as you normally would */
8130 /* after a PHY_RESET. */
8131 /* e. It is recommended that the caller will give */
8132 /* 10 "retry", however, caller can change to a */
8133 /* different number, depending on you code. */
8134 /* */
8135 /********************************************************/
8136 LM_STATUS LM_ResetPhy_5703_4_5(LM_DEVICE_BLOCK *pDevice, int retry, int reset);
8137
8138 LM_STATUS
8139 LM_ResetPhy_5703_4_5(LM_DEVICE_BLOCK *pDevice, int retry, int reset)
8140 {
8141 LM_UINT32 val32, save9;
8142 LM_UINT32 dataLo, dataHi;
8143 int i, channel;
8144 int reset_success = LM_STATUS_FAILURE;
8145 int force_reset;
8146
8147 /* to actually do a PHY_RESET or not is dictated by the caller */
8148 force_reset = reset;
8149
8150 while (retry-- && (reset_success != LM_STATUS_SUCCESS))
8151 {
8152 if (force_reset)
8153 {
8154 /* issue a phy reset, and wait for reset to complete */
8155 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
8156 for(i = 0; i < 100; i++)
8157 {
8158 MM_Wait(10);
8159
8160 LM_ReadPhy(pDevice, PHY_CTRL_REG, &val32);
8161 if(val32 && !(val32 & PHY_CTRL_PHY_RESET))
8162 {
8163 MM_Wait(20);
8164 break;
8165 }
8166 }
8167
8168 /* no more phy reset unless lockup detected */
8169 force_reset = FALSE;
8170 }
8171
8172 /* assuming reset is successful first */
8173 reset_success = LM_STATUS_SUCCESS;
8174
8175 /* now go check the DFE TAPs to see if locked up, but
8176 first, we need to set up PHY so we can read DFE TAPs */
8177
8178 /* Disable Transmitter and Interrupt, while we play with
8179 the PHY registers, so the link partner won't see any
8180 strange data and the Driver won't see any interrupts. */
8181 LM_ReadPhy(pDevice, 0x10, &val32);
8182 LM_WritePhy(pDevice, 0x10, val32 | 0x3000);
8183
8184 /* Setup Full-Duplex, 1000 mbps */
8185 LM_WritePhy(pDevice, 0x0, 0x0140);
8186
8187 /* Set to Master mode */
8188 LM_ReadPhy(pDevice, 0x9, &save9);
8189 LM_WritePhy(pDevice, 0x9, 0x1800);
8190
8191 /* Enable SM_DSP_CLOCK & 6dB */
8192 LM_WritePhy(pDevice, 0x18, 0x0c00);
8193
8194 /* blocks the PHY control access */
8195 LM_WritePhy(pDevice, 0x17, 0x8005);
8196 LM_WritePhy(pDevice, 0x15, 0x0800);
8197
8198 /* check TAPs for all 4 channels, as soon
8199 as we see a lockup we'll stop checking */
8200 for (channel=0; (channel<4) && (reset_success == LM_STATUS_SUCCESS);
8201 channel++)
8202 {
8203 /* select channel and set TAP index to 0 */
8204 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
8205 /* freeze filter again just to be safe */
8206 LM_WritePhy(pDevice, 0x16, 0x0002);
8207
8208 /* write fixed pattern to the RAM, 3 TAPs for
8209 each channel, each TAP have 2 WORDs (LO/HI) */
8210 for (i=0; i<6; i++)
8211 LM_WritePhy(pDevice, 0x15, pattern[channel][i]);
8212
8213 /* Activate PHY's Macro operation to write DFE TAP from RAM,
8214 and wait for Macro to complete */
8215 LM_WritePhy(pDevice, 0x16, 0x0202);
8216 if (!LM_wait_macro_done(pDevice))
8217 {
8218 reset_success = LM_STATUS_FAILURE;
8219 force_reset = TRUE;
8220 break;
8221 }
8222
8223 /* --- done with write phase, now begin read phase --- */
8224
8225 /* select channel and set TAP index to 0 */
8226 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
8227
8228 /* Active PHY's Macro operation to load DFE TAP to RAM,
8229 and wait for Macro to complete */
8230 LM_WritePhy(pDevice, 0x16, 0x0082);
8231 if (!LM_wait_macro_done(pDevice))
8232 {
8233 reset_success = LM_STATUS_FAILURE;
8234 force_reset = TRUE;
8235 break;
8236 }
8237
8238 /* enable "pre-fetch" */
8239 LM_WritePhy(pDevice, 0x16, 0x0802);
8240 if (!LM_wait_macro_done(pDevice))
8241 {
8242 reset_success = LM_STATUS_FAILURE;
8243 force_reset = TRUE;
8244 break;
8245 }
8246
8247 /* read back the TAP values.
8248 3 TAPs for each channel, each TAP have 2 WORDs (LO/HI) */
8249 for (i=0; i<6; i+=2)
8250 {
8251 /* read Lo/Hi then wait for 'done' is faster */
8252 LM_ReadPhy(pDevice, 0x15, &dataLo);
8253 LM_ReadPhy(pDevice, 0x15, &dataHi);
8254 if (!LM_wait_macro_done(pDevice))
8255 {
8256 reset_success = LM_STATUS_FAILURE;
8257 force_reset = TRUE;
8258 break;
8259 }
8260
8261 /* For 5703/04, each DFE TAP has 21-bits (low word 15,
8262 * hi word 6) For 5705, each DFE TAP pas 19-bits (low word 15,
8263 * hi word 4) For simplicity, we check only 19-bits, so we
8264 * don't have to distinguish which chip it is. */
8265 dataLo &= 0x7fff;
8266 dataHi &= 0x000f;
8267
8268 /* check if what we wrote is what we read back */
8269 if ( (dataLo != pattern[channel][i]) || (dataHi != pattern[channel][i+1]) )
8270 {
8271 /* if failed, then the PHY is locked up,
8272 we need to do PHY reset again */
8273 reset_success = LM_STATUS_FAILURE;
8274 force_reset = TRUE;
8275 /* 04/25/2003. sb. do these writes before issueing a reset. */
8276 /* these steps will reduce the chance of back-to-back
8277 * phy lockup after reset */
8278 LM_WritePhy(pDevice, 0x17, 0x000B);
8279 LM_WritePhy(pDevice, 0x15, 0x4001);
8280 LM_WritePhy(pDevice, 0x15, 0x4005);
8281 break;
8282 }
8283 } /* for i */
8284 } /* for channel */
8285 } /* while */
8286
8287 /* restore dfe coeff back to zeros */
8288 for (channel=0; channel<4 ; channel++)
8289 {
8290 LM_WritePhy(pDevice, 0x17, (channel * 0x2000) | 0x0200);
8291 LM_WritePhy(pDevice, 0x16, 0x0002);
8292 for (i=0; i<6; i++)
8293 LM_WritePhy(pDevice, 0x15, 0x0000);
8294 LM_WritePhy(pDevice, 0x16, 0x0202);
8295 if (!LM_wait_macro_done(pDevice))
8296 {
8297 reset_success = LM_STATUS_FAILURE;
8298 break;
8299 }
8300 }
8301
8302 /* remove block phy control */
8303 LM_WritePhy(pDevice, 0x17, 0x8005);
8304 LM_WritePhy(pDevice, 0x15, 0x0000);
8305
8306 /* unfreeze DFE TAP filter for all channels */
8307 LM_WritePhy(pDevice, 0x17, 0x8200);
8308 LM_WritePhy(pDevice, 0x16, 0x0000);
8309
8310 /* Restore PHY back to operating state */
8311 LM_WritePhy(pDevice, 0x18, 0x0400);
8312
8313 /* Restore register 9 */
8314 LM_WritePhy(pDevice, 0x9, save9);
8315
8316 /* enable transmitter and interrupt */
8317 LM_ReadPhy(pDevice, 0x10, &val32);
8318 LM_WritePhy(pDevice, 0x10, (val32 & ~0x3000));
8319
8320 return reset_success;
8321 }
8322
8323 LM_VOID
8324 LM_ResetPhy(LM_DEVICE_BLOCK *pDevice)
8325 {
8326 int j;
8327 LM_UINT32 miireg;
8328
8329 if (pDevice->PhyFlags & PHY_CHECK_TAPS_AFTER_RESET)
8330 {
8331 LM_ResetPhy_5703_4_5(pDevice, 5, 1);
8332 }
8333 else
8334 {
8335 int wait_val = 100;
8336 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
8337
8338 if( pDevice->PhyFlags & PHY_IS_FIBER )
8339 wait_val = 5000;
8340
8341 for(j = 0; j < wait_val; j++)
8342 {
8343 MM_Wait(10);
8344
8345 LM_ReadPhy(pDevice, PHY_CTRL_REG, &miireg);
8346 if(miireg && !(miireg & PHY_CTRL_PHY_RESET))
8347 {
8348 MM_Wait(20);
8349 break;
8350 }
8351 }
8352
8353 LM_PhyTapPowerMgmt(pDevice);
8354 }
8355 if ( (pDevice->PhyFlags & PHY_ADC_FIX) &&
8356 !( pDevice->PhyFlags & PHY_IS_FIBER) )
8357 {
8358 LM_WritePhy(pDevice, 0x18, 0x0c00);
8359 LM_WritePhy(pDevice, 0x17, 0x201f);
8360 LM_WritePhy(pDevice, 0x15, 0x2aaa);
8361 LM_WritePhy(pDevice, 0x17, 0x000a);
8362 LM_WritePhy(pDevice, 0x15, 0x0323);
8363 LM_WritePhy(pDevice, 0x18, 0x0400);
8364 }
8365 if ( (pDevice->PhyFlags & PHY_5705_5750_FIX) &&
8366 !( pDevice->PhyFlags & PHY_IS_FIBER) )
8367 {
8368 LM_WritePhy(pDevice, 0x18, 0x0c00);
8369 LM_WritePhy(pDevice, 0x17, 0x000a);
8370 LM_WritePhy(pDevice, 0x15, 0x310b);
8371 LM_WritePhy(pDevice, 0x17, 0x201f);
8372 LM_WritePhy(pDevice, 0x15, 0x9506);
8373 LM_WritePhy(pDevice, 0x17, 0x401f);
8374 LM_WritePhy(pDevice, 0x15, 0x14e2);
8375 LM_WritePhy(pDevice, 0x18, 0x0400);
8376 }
8377 if ( (pDevice->PhyFlags & PHY_5704_A0_FIX) &&
8378 !( pDevice->PhyFlags & PHY_IS_FIBER) )
8379 {
8380 LM_WritePhy(pDevice, 0x1c, 0x8d68);
8381 LM_WritePhy(pDevice, 0x1c, 0x8d68);
8382 }
8383 if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
8384 {
8385 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &miireg);
8386 miireg |= 1; /* set tx elastic fifo */
8387 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, miireg);
8388
8389 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20);
8390 }
8391 else if (pDevice->Flags & JUMBO_CAPABLE_FLAG)
8392 {
8393 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0007);
8394 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &miireg);
8395 miireg |= 0x4000; /* set rx extended packet length */
8396 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, miireg);
8397
8398 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &miireg);
8399 miireg |= 1; /* set tx elastic fifo */
8400 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, miireg);
8401
8402 }
8403
8404 LM_SetEthWireSpeed(pDevice);
8405 pDevice->PhyFlags &= ~PHY_FIBER_FALLBACK;
8406 }
8407
8408 STATIC LM_VOID
8409 LM_SetEthWireSpeed(LM_DEVICE_BLOCK *pDevice)
8410 {
8411 LM_UINT32 Value32;
8412
8413 if( pDevice->PhyFlags & PHY_IS_FIBER)
8414 return;
8415
8416 /* Enable Ethernet@WireSpeed. */
8417 if (pDevice->PhyFlags & PHY_ETHERNET_WIRESPEED)
8418 {
8419 LM_WritePhy(pDevice, 0x18, 0x7007);
8420 LM_ReadPhy(pDevice, 0x18, &Value32);
8421 LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4);
8422 }
8423 }
8424
8425 STATIC LM_STATUS
8426 LM_PhyAdvertiseAll(LM_DEVICE_BLOCK *pDevice)
8427 {
8428 LM_UINT32 miireg;
8429
8430 LM_ReadPhy(pDevice, PHY_AN_AD_REG, &miireg);
8431 pDevice->advertising = miireg;
8432 if ((miireg & PHY_AN_AD_ALL_SPEEDS) != PHY_AN_AD_ALL_SPEEDS)
8433 {
8434 return LM_STATUS_FAILURE;
8435 }
8436
8437 LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &miireg);
8438 pDevice->advertising1000 = miireg;
8439
8440 if (!(pDevice->PhyFlags & PHY_NO_GIGABIT))
8441 {
8442 if ((miireg & BCM540X_AN_AD_ALL_1G_SPEEDS) !=
8443 BCM540X_AN_AD_ALL_1G_SPEEDS)
8444 {
8445 return LM_STATUS_FAILURE;
8446 }
8447 }else{
8448
8449 if(miireg)
8450 {
8451 return LM_STATUS_FAILURE;
8452 }
8453 }
8454 return LM_STATUS_SUCCESS;
8455 }
8456
8457 /******************************************************************************/
8458 /* Description: */
8459 /* */
8460 /* Return: */
8461 /******************************************************************************/
8462 LM_VOID
8463 LM_ReadPhy(
8464 PLM_DEVICE_BLOCK pDevice,
8465 LM_UINT32 PhyReg,
8466 PLM_UINT32 pData32) {
8467 LM_UINT32 Value32;
8468 LM_UINT32 j;
8469
8470 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8471 {
8472 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
8473 ~MI_MODE_AUTO_POLLING_ENABLE);
8474 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8475 MM_Wait(40);
8476 }
8477
8478 Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
8479 ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
8480 MI_COM_CMD_READ | MI_COM_START;
8481
8482 REG_WR(pDevice, MacCtrl.MiCom, Value32);
8483
8484 for(j = 0; j < 200; j++)
8485 {
8486 MM_Wait(1);
8487
8488 Value32 = REG_RD(pDevice, MacCtrl.MiCom);
8489
8490 if(!(Value32 & MI_COM_BUSY))
8491 {
8492 MM_Wait(5);
8493 Value32 = REG_RD(pDevice, MacCtrl.MiCom);
8494 Value32 &= MI_COM_PHY_DATA_MASK;
8495 break;
8496 }
8497 }
8498
8499 if(Value32 & MI_COM_BUSY)
8500 {
8501 Value32 = 0;
8502 }
8503
8504 *pData32 = Value32;
8505
8506 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8507 {
8508 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
8509 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8510 MM_Wait(40);
8511 }
8512 } /* LM_ReadPhy */
8513
8514
8515
8516 /******************************************************************************/
8517 /* Description: */
8518 /* */
8519 /* Return: */
8520 /******************************************************************************/
8521 LM_VOID
8522 LM_WritePhy(
8523 PLM_DEVICE_BLOCK pDevice,
8524 LM_UINT32 PhyReg,
8525 LM_UINT32 Data32) {
8526 LM_UINT32 Value32;
8527 LM_UINT32 j;
8528
8529 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8530 {
8531 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
8532 ~MI_MODE_AUTO_POLLING_ENABLE);
8533 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8534 MM_Wait(40);
8535 }
8536
8537 Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
8538 ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
8539 (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START;
8540
8541 REG_WR(pDevice, MacCtrl.MiCom, Value32);
8542
8543 for(j = 0; j < 200; j++)
8544 {
8545 MM_Wait(1);
8546
8547 Value32 = REG_RD(pDevice, MacCtrl.MiCom);
8548
8549 if(!(Value32 & MI_COM_BUSY))
8550 {
8551 MM_Wait(5);
8552 break;
8553 }
8554 }
8555
8556 if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
8557 {
8558 REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
8559 REG_RD_BACK(pDevice, MacCtrl.MiMode);
8560 MM_Wait(40);
8561 }
8562 } /* LM_WritePhy */
8563
8564 /* MII read/write functions to export to the robo support code */
8565 LM_UINT16
8566 robo_miird(void *h, int phyadd, int regoff)
8567 {
8568 PLM_DEVICE_BLOCK pdev = h;
8569 LM_UINT32 savephyaddr, val32;
8570
8571 savephyaddr = pdev->PhyAddr;
8572 pdev->PhyAddr = phyadd;
8573
8574 LM_ReadPhy(pdev, regoff, &val32);
8575
8576 pdev->PhyAddr = savephyaddr;
8577
8578 return ((LM_UINT16)(val32 & 0xffff));
8579 }
8580
8581 void
8582 robo_miiwr(void *h, int phyadd, int regoff, LM_UINT16 value)
8583 {
8584 PLM_DEVICE_BLOCK pdev = h;
8585 LM_UINT32 val32, savephyaddr;
8586
8587 savephyaddr = pdev->PhyAddr;
8588 pdev->PhyAddr = phyadd;
8589
8590 val32 = (LM_UINT32)value;
8591 LM_WritePhy(pdev, regoff, val32);
8592
8593 pdev->PhyAddr = savephyaddr;
8594 }
8595
8596 STATIC void
8597 LM_GetPhyId(LM_DEVICE_BLOCK *pDevice)
8598 {
8599 LM_UINT32 Value32;
8600
8601 LM_ReadPhy(pDevice, PHY_ID1_REG, &Value32);
8602 pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;
8603
8604 LM_ReadPhy(pDevice, PHY_ID2_REG, &Value32);
8605 pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
8606 (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
8607
8608 }
8609
8610 LM_STATUS
8611 LM_EnableMacLoopBack(PLM_DEVICE_BLOCK pDevice)
8612 {
8613 pDevice->LoopBackMode = LM_MAC_LOOP_BACK_MODE;
8614 pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
8615 pDevice->MacMode |= (MAC_MODE_PORT_INTERNAL_LOOPBACK |
8616 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII);
8617 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
8618 MM_Wait(40);
8619 LM_SetupPhy(pDevice);
8620 return LM_STATUS_SUCCESS;
8621 }
8622
8623 LM_STATUS
8624 LM_DisableMacLoopBack(PLM_DEVICE_BLOCK pDevice)
8625 {
8626 pDevice->LoopBackMode = 0;
8627
8628 pDevice->MacMode &= ~(MAC_MODE_PORT_INTERNAL_LOOPBACK |
8629 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_MASK);
8630 REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
8631 MM_Wait(40);
8632 if(pDevice->PhyFlags & PHY_IS_FIBER)
8633 LM_ResetPhy(pDevice);
8634
8635 LM_SetupPhy(pDevice);
8636 return LM_STATUS_SUCCESS;
8637 }
8638
8639 LM_STATUS
8640 LM_EnablePhyLoopBack(PLM_DEVICE_BLOCK pDevice)
8641 {
8642 pDevice->LoopBackMode = LM_PHY_LOOP_BACK_MODE;
8643 LM_SetupPhy(pDevice);
8644 return LM_STATUS_SUCCESS;
8645 }
8646
8647 LM_STATUS
8648 LM_DisablePhyLoopBack(PLM_DEVICE_BLOCK pDevice)
8649 {
8650 pDevice->LoopBackMode = 0;
8651 LM_SetupPhy(pDevice);
8652 return LM_STATUS_SUCCESS;
8653 }
8654
8655 LM_STATUS
8656 LM_EnableExtLoopBack(PLM_DEVICE_BLOCK pDevice, LM_LINE_SPEED LineSpeed)
8657 {
8658 pDevice->LoopBackMode = LM_EXT_LOOP_BACK_MODE;
8659
8660 pDevice->SavedDisableAutoNeg = pDevice->DisableAutoNeg;
8661 pDevice->SavedRequestedLineSpeed = pDevice->RequestedLineSpeed;
8662 pDevice->SavedRequestedDuplexMode = pDevice->RequestedDuplexMode;
8663
8664 pDevice->DisableAutoNeg = TRUE;
8665 pDevice->RequestedLineSpeed = LineSpeed;
8666 pDevice->RequestedDuplexMode = LM_DUPLEX_MODE_FULL;
8667 LM_SetupPhy(pDevice);
8668 return LM_STATUS_SUCCESS;
8669 }
8670
8671 LM_STATUS
8672 LM_DisableExtLoopBack(PLM_DEVICE_BLOCK pDevice)
8673 {
8674 pDevice->LoopBackMode = 0;
8675
8676 pDevice->DisableAutoNeg = pDevice->SavedDisableAutoNeg;
8677 pDevice->RequestedLineSpeed = pDevice->SavedRequestedLineSpeed;
8678 pDevice->RequestedDuplexMode = pDevice->SavedRequestedDuplexMode;
8679
8680 LM_SetupPhy(pDevice);
8681 return LM_STATUS_SUCCESS;
8682 }
8683
8684 /******************************************************************************/
8685 /* Description: */
8686 /* */
8687 /* Return: */
8688 /******************************************************************************/
8689 LM_STATUS
8690 LM_SetPowerState(
8691 PLM_DEVICE_BLOCK pDevice,
8692 LM_POWER_STATE PowerLevel)
8693 {
8694 #ifdef BCM_WOL
8695 LM_UINT32 PmeSupport;
8696 PLM_DEVICE_BLOCK pDevice2 = 0;
8697 int j;
8698 #endif
8699 LM_UINT32 Value32;
8700 LM_UINT32 PmCtrl;
8701
8702 /* make sureindirect accesses are enabled*/
8703 MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
8704
8705 /* Clear the PME_ASSERT bit and the power state bits. Also enable */
8706 /* the PME bit. */
8707 MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl);
8708
8709 PmCtrl |= T3_PM_PME_ASSERTED;
8710 PmCtrl &= ~T3_PM_POWER_STATE_MASK;
8711
8712 /* Set the appropriate power state. */
8713 if(PowerLevel == LM_POWER_STATE_D0)
8714 {
8715 /* Bring the card out of low power mode. */
8716 PmCtrl |= T3_PM_POWER_STATE_D0;
8717 MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
8718
8719 Value32 = REG_RD(pDevice, Grc.LocalCtrl);
8720
8721 if(T3_ASIC_5752(pDevice->ChipRevId)){
8722 Value32 |= (GRC_MISC_LOCAL_CTRL_GPIO_OE3 |
8723 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT3 |
8724 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8725 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8726 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8727 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8728 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8729 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8730 }
8731 else
8732 {
8733 Value32 &= ~(GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
8734 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
8735 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
8736 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
8737 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
8738 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
8739 }
8740
8741 RAW_REG_WR(pDevice, Grc.LocalCtrl, Value32);
8742
8743 MM_Wait(40); /* Required delay is about 20us. */
8744
8745 pDevice->PowerLevel = PowerLevel;
8746 return LM_STATUS_SUCCESS;
8747 }
8748 #ifdef BCM_WOL
8749 else if(PowerLevel == LM_POWER_STATE_D1)
8750 {
8751 PmCtrl |= T3_PM_POWER_STATE_D1;
8752 }
8753 else if(PowerLevel == LM_POWER_STATE_D2)
8754 {
8755 PmCtrl |= T3_PM_POWER_STATE_D2;
8756 }
8757 else if(PowerLevel == LM_POWER_STATE_D3)
8758 {
8759 PmCtrl |= T3_PM_POWER_STATE_D3;
8760 }
8761 else
8762 {
8763 return LM_STATUS_FAILURE;
8764 }
8765 PmCtrl |= T3_PM_PME_ENABLE;
8766
8767 /* Mask out all interrupts so LM_SetupPhy won't be called while we are */
8768 /* setting new line speed. */
8769 Value32 = REG_RD(pDevice, PciCfg.MiscHostCtrl);
8770 REG_WR(pDevice, PciCfg.MiscHostCtrl, Value32 | MISC_HOST_CTRL_MASK_PCI_INT);
8771
8772 if(!pDevice->RestoreOnWakeUp)
8773 {
8774 pDevice->RestoreOnWakeUp = TRUE;
8775 pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg;
8776 pDevice->WakeUpRequestedLineSpeed = pDevice->RequestedLineSpeed;
8777 pDevice->WakeUpRequestedDuplexMode = pDevice->RequestedDuplexMode;
8778 }
8779
8780 /* Force auto-negotiation to 10 line speed. */
8781 pDevice->DisableAutoNeg = FALSE;
8782
8783 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG))
8784 {
8785 pDevice->RequestedLineSpeed = LM_LINE_SPEED_10MBPS;
8786 LM_SetupPhy(pDevice);
8787 }
8788
8789 /* Put the driver in the initial state, and go through the power down */
8790 /* sequence. */
8791 LM_DoHalt(pDevice);
8792
8793 if (!(pDevice->AsfFlags & ASF_ENABLED))
8794 {
8795 for(j = 0; j < 20000; j++)
8796 {
8797 MM_Wait(10);
8798
8799 Value32 = MEM_RD_OFFSET(pDevice, T3_ASF_FW_STATUS_MAILBOX);
8800 if(Value32 == ~T3_MAGIC_NUM_FIRMWARE_INIT_DONE)
8801 {
8802 break;
8803 }
8804 }
8805 }
8806
8807 MEM_WR_OFFSET(pDevice, DRV_WOL_MAILBOX, DRV_WOL_SIGNATURE |
8808 DRV_DOWN_STATE_SHUTDOWN | 0x2 | DRV_WOL_SET_MAGIC_PKT);
8809
8810 MM_ReadConfig32(pDevice, T3_PCI_PM_CAP_REG, &PmeSupport);
8811
8812 if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)
8813 {
8814
8815 /* Enable WOL. */
8816 if (!(pDevice->TbiFlags & ENABLE_TBI_FLAG))
8817 {
8818 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a);
8819 MM_Wait(40);
8820 }
8821
8822 if (! T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId))
8823 {
8824 /* Let boot code deal with LED mode on shasta */
8825 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl);
8826 }
8827
8828 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
8829 {
8830 Value32 = MAC_MODE_PORT_MODE_TBI;
8831 }
8832 else
8833 {
8834 Value32 = MAC_MODE_PORT_MODE_MII;
8835 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
8836 {
8837 if(pDevice->LedCtrl == LED_CTRL_PHY_MODE_2 ||
8838 pDevice->WolSpeed == WOL_SPEED_10MB)
8839 {
8840 Value32 |= MAC_MODE_LINK_POLARITY;
8841 }
8842 }
8843 else
8844 {
8845 Value32 |= MAC_MODE_LINK_POLARITY;
8846 }
8847 }
8848 REG_WR(pDevice, MacCtrl.Mode, Value32);
8849 REG_RD_BACK(pDevice, MacCtrl.Mode);
8850 MM_Wait(40); MM_Wait(40); MM_Wait(40);
8851
8852 /* Always enable magic packet wake-up if we have vaux. */
8853 if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) &&
8854 (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET))
8855 {
8856 Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE;
8857 }
8858
8859 #ifdef BCM_ASF
8860 if (pDevice->AsfFlags & ASF_ENABLED)
8861 {
8862 Value32 &= ~MAC_MODE_ACPI_POWER_ON_ENABLE;
8863 }
8864 #endif
8865 REG_WR(pDevice, MacCtrl.Mode, Value32);
8866
8867 /* Enable the receiver. */
8868 REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE);
8869 }
8870 else if (!(pDevice->AsfFlags & ASF_ENABLED))
8871 {
8872 if (pDevice->TbiFlags & ENABLE_TBI_FLAG)
8873 {
8874 REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
8875 LED_CTRL_OVERRIDE_TRAFFIC_LED);
8876 }
8877 else
8878 {
8879 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
8880 BCM540X_EXT_CTRL_FORCE_LED_OFF);
8881 LM_WritePhy(pDevice, 0x18, 0x01b2);
8882 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
8883 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5704) &&
8884 !T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
8885 {
8886 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOWER_POWER_MODE);
8887 }
8888 }
8889 }
8890
8891 /* Disable tx/rx clocks, and select an alternate clock. */
8892 if (T3_ASIC_5714_FAMILY(pDevice->ChipRevId)){
8893 /* Do nothing */
8894 }
8895 else if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) ||
8896 ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) &&
8897 (pDevice->WolSpeed == WOL_SPEED_10MB)))
8898 {
8899 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8900 T3_PCI_SELECT_ALTERNATE_CLOCK |
8901 T3_PCI_POWER_DOWN_PCI_PLL133;
8902
8903 REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8904 }
8905 /* ASF on 5750 will not run properly on slow core clock */
8906 else if( !(T3_ASIC_IS_575X_PLUS(pDevice->ChipRevId) &&
8907 (pDevice->AsfFlags & ASF_ENABLED) ))
8908 {
8909 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8910 {
8911 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8912 T3_PCI_SELECT_ALTERNATE_CLOCK;
8913 }
8914 else if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
8915 {
8916 Value32 = T3_PCI_625_CORE_CLOCK;
8917 }
8918 else
8919 {
8920 Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK;
8921 }
8922 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8923
8924 MM_Wait(40);
8925
8926 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
8927 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8928 {
8929 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8930 T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK;
8931 }
8932 else if(T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) )
8933 {
8934 Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_625_CORE_CLOCK;
8935 }
8936 else if(!T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
8937 {
8938 Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK;
8939 }
8940
8941 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8942
8943 if (!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
8944 {
8945 MM_Wait(40);
8946
8947 if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
8948 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
8949 {
8950 Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
8951 T3_PCI_44MHZ_CORE_CLOCK;
8952 }
8953 else
8954 {
8955 Value32 = T3_PCI_44MHZ_CORE_CLOCK;
8956 }
8957
8958 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl | Value32);
8959 }
8960 }
8961
8962 MM_Wait(40);
8963
8964 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
8965 {
8966 pDevice2 = MM_FindPeerDev(pDevice);
8967 }
8968 if (!(pDevice->Flags & EEPROM_WP_FLAG))
8969 {
8970 LM_SwitchVaux(pDevice, pDevice2);
8971 }
8972
8973 LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET);
8974
8975 if((T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5750_AX) ||
8976 (T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5750_BX)) {
8977
8978 Value32= REG_RD_OFFSET(pDevice, 0x7d00);
8979 REG_WR_OFFSET(pDevice, 0x7d00,Value32 & ~(BIT_16 | BIT_4 | BIT_2 | BIT_1 | BIT_0));
8980
8981 if(!(pDevice->AsfFlags & ASF_ENABLED))
8982 LM_HaltCpu(pDevice, T3_RX_CPU_ID);
8983
8984 }
8985
8986 /* Put the the hardware in low power mode. */
8987 if (!(pDevice->Flags & DISABLE_D3HOT_FLAG))
8988 {
8989 MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
8990 MM_Wait(200); /* Wait 200us for state transition */
8991 }
8992
8993 pDevice->PowerLevel = PowerLevel;
8994
8995 #else
8996 LM_WritePostResetSignatures(pDevice, LM_SHUTDOWN_RESET);
8997 #endif /* BCM_WOL */
8998
8999 return LM_STATUS_SUCCESS;
9000 } /* LM_SetPowerState */
9001
9002
9003 LM_VOID
9004 LM_SwitchVaux(PLM_DEVICE_BLOCK pDevice, PLM_DEVICE_BLOCK pDevice2)
9005 {
9006 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
9007 return;
9008
9009 pDevice->GrcLocalCtrl &= ~(GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9010 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9011 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
9012 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
9013 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
9014 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
9015
9016 /* Switch adapter to auxilliary power if WOL enabled */
9017 if ((pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) ||
9018 (pDevice->AsfFlags & ASF_ENABLED) ||
9019 (pDevice2 && ((pDevice2->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) ||
9020 (pDevice2->AsfFlags & ASF_ENABLED))))
9021 {
9022 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
9023 T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
9024 {
9025 /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
9026 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9027 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9028 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9029 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
9030 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
9031 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9032 MM_Wait(40);
9033 }
9034 else
9035 {
9036 if (pDevice2 && pDevice2->InitDone)
9037 {
9038 return;
9039 }
9040
9041 /* On NICs GPIOs are used for vaux.
9042 The transition of GPIO0 from 0-1 causes vaux
9043 to power up. Transition of GPIO1 from 1-0 turns vaux off.
9044 GPIO2 transition from 1-0 enables a non-glitch vaux
9045 transition from one state to another.
9046 On certain designs we should not output GPIO2.
9047 */
9048 if(pDevice->Flags & GPIO2_DONOT_OUTPUT)
9049 {
9050 /* GPIO0 = 0, GPIO1 = 1. */
9051 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9052 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9053 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9054 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9055
9056 MM_Wait(40);
9057
9058 /* GPIO0 = 1, GPIO1 = 1. */
9059 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9060 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9061 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9062 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
9063 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9064
9065 MM_Wait(40);
9066 }
9067 else
9068 {
9069
9070 /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */
9071 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9072 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9073 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9074 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
9075 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
9076 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
9077
9078 MM_Wait(40);
9079
9080 /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */
9081 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9082 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9083 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9084 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
9085 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
9086 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
9087 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
9088 MM_Wait(40);
9089
9090 /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
9091 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9092 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
9093 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9094 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
9095 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
9096 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9097 MM_Wait(40);
9098 } /* GPIO2 OK */
9099 } /* Not 5700||5701 */
9100 } /* WOL disabled */
9101 else
9102 {
9103 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
9104 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701))
9105 {
9106 if (pDevice2 && pDevice2->InitDone)
9107 {
9108 return;
9109 }
9110
9111 /* GPIO1 = 1 */
9112 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9113 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9114 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9115 MM_Wait(40);
9116
9117 /* GPIO1 = 0 */
9118 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9119 GRC_MISC_LOCAL_CTRL_GPIO_OE1);
9120 MM_Wait(40);
9121
9122 /* GPIO1 = 1 */
9123 RAW_REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
9124 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
9125 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
9126 MM_Wait(40);
9127 }
9128 }
9129 }
9130
9131
9132 /******************************************************************************/
9133 /* Description: */
9134 /* */
9135 /* Return: */
9136 /******************************************************************************/
9137 static LM_UINT32
9138 GetPhyAdFlowCntrlSettings(
9139 PLM_DEVICE_BLOCK pDevice)
9140 {
9141 LM_UINT32 Value32;
9142
9143 Value32 = 0;
9144
9145 /* Auto negotiation flow control only when autonegotiation is enabled. */
9146 if(pDevice->DisableAutoNeg == FALSE ||
9147 pDevice->RequestedLineSpeed == LM_LINE_SPEED_AUTO)
9148 {
9149 if (T3_ASIC_5714_FAMILY(pDevice->ChipRevId) &&
9150 (pDevice->PhyFlags & PHY_IS_FIBER)) {
9151
9152 /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
9153 if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
9154 ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) &&
9155 (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)))
9156 {
9157 Value32 |=PHY_AN_AD_1000XPAUSE;
9158 }
9159 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
9160 {
9161 Value32 |= PHY_AN_AD_1000XPSE_ASYM;
9162 }
9163 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
9164 {
9165 Value32 |= (PHY_AN_AD_1000XPSE_ASYM | PHY_AN_AD_1000XPAUSE);
9166 }
9167
9168 }else{
9169
9170 /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
9171 if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
9172 ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) &&
9173 (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)))
9174 {
9175 Value32 |= PHY_AN_AD_PAUSE_CAPABLE;
9176 }
9177 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
9178 {
9179 Value32 |= PHY_AN_AD_ASYM_PAUSE;
9180 }
9181 else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
9182 {
9183 Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE;
9184 }
9185 }
9186 }
9187
9188 return Value32;
9189 }
9190
9191
9192
9193 /******************************************************************************/
9194 /* Description: */
9195 /* */
9196 /* Return: */
9197 /* LM_STATUS_FAILURE */
9198 /* LM_STATUS_SUCCESS */
9199 /* */
9200 /******************************************************************************/
9201 static LM_STATUS
9202 LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice)
9203 {
9204 LM_LINE_SPEED LineSpeed;
9205 LM_DUPLEX_MODE DuplexMode;
9206 LM_UINT32 NewPhyCtrl;
9207 LM_UINT32 Value32, PhyReg18;
9208 LM_UINT32 Cnt;
9209
9210 /* Get the interface type, line speed, and duplex mode. */
9211 LineSpeed = pDevice->RequestedLineSpeed;
9212 DuplexMode = pDevice->RequestedDuplexMode;
9213
9214 /* Exit ext. loop back, in case it was in ext. loopback mode */
9215 /* Set Extended packet length bit on chips that support jumbo frames */
9216 if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
9217 {
9218 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x4c20);
9219
9220 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &Value32);
9221 Value32 |= 1; /* set tx elastic fifo */
9222 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, Value32);
9223
9224 }
9225 else
9226 {
9227 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0007);
9228 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &PhyReg18);
9229 PhyReg18 &= ~0x8000; /* clear external loop back */
9230
9231 if (pDevice->Flags & JUMBO_CAPABLE_FLAG)
9232 {
9233 PhyReg18 |= 0x4000; /* set extended packet length */
9234 LM_ReadPhy(pDevice, BCM540X_EXT_CTRL_REG, &Value32);
9235 Value32 |= 1; /* set tx elastic fifo */
9236 LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, Value32);
9237 }
9238 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, PhyReg18);
9239 }
9240
9241 #ifdef BCM_WOL
9242 if (pDevice->RestoreOnWakeUp)
9243 {
9244 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9245 pDevice->advertising1000 = 0;
9246 Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF;
9247 if (pDevice->WolSpeed == WOL_SPEED_100MB)
9248 {
9249 Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
9250 }
9251 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9252 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9253 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9254 pDevice->advertising = Value32;
9255 }
9256 /* Setup the auto-negotiation advertisement register. */
9257 else if(LineSpeed == LM_LINE_SPEED_UNKNOWN)
9258 #else
9259 /* Setup the auto-negotiation advertisement register. */
9260 if(LineSpeed == LM_LINE_SPEED_UNKNOWN)
9261 #endif
9262 {
9263 /* Setup the 10/100 Mbps auto-negotiation advertisement register. */
9264 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | PHY_AN_AD_ALL_SPEEDS;
9265 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9266
9267 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9268 pDevice->advertising = Value32;
9269
9270 /* Advertise 1000Mbps */
9271 if (!(pDevice->PhyFlags & PHY_NO_GIGABIT))
9272 {
9273 Value32 = BCM540X_AN_AD_ALL_1G_SPEEDS;
9274
9275 #ifdef INCLUDE_5701_AX_FIX
9276 /* slave mode. This will force the PHY to operate in */
9277 /* master mode. */
9278 if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
9279 pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
9280 {
9281 Value32 |= BCM540X_CONFIG_AS_MASTER |
9282 BCM540X_ENABLE_CONFIG_AS_MASTER;
9283 }
9284 #endif
9285
9286 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
9287 pDevice->advertising1000 = Value32;
9288 }
9289 else
9290 {
9291 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9292 pDevice->advertising1000 = 0;
9293 }
9294 }
9295 else
9296 {
9297 if ((pDevice->PhyFlags & PHY_NO_GIGABIT) &&
9298 (LineSpeed == LM_LINE_SPEED_1000MBPS))
9299 {
9300 LineSpeed = LM_LINE_SPEED_100MBPS;
9301 }
9302 if(LineSpeed == LM_LINE_SPEED_1000MBPS)
9303 {
9304 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9305 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9306
9307 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9308 pDevice->advertising = Value32;
9309
9310 if(DuplexMode != LM_DUPLEX_MODE_FULL)
9311 {
9312 Value32 = BCM540X_AN_AD_1000BASET_HALF;
9313 }
9314 else
9315 {
9316 Value32 = BCM540X_AN_AD_1000BASET_FULL;
9317 }
9318
9319 #ifdef INCLUDE_5701_AX_FIX
9320 if ((pDevice->LoopBackMode == LM_EXT_LOOP_BACK_MODE) ||
9321 (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
9322 pDevice->ChipRevId == T3_CHIP_ID_5701_B0))
9323 #else
9324 if (pDevice->LoopBackMode == LM_EXT_LOOP_BACK_MODE)
9325 #endif
9326 {
9327 Value32 |= BCM540X_CONFIG_AS_MASTER |
9328 BCM540X_ENABLE_CONFIG_AS_MASTER;
9329 }
9330 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
9331 pDevice->advertising1000 = Value32;
9332 if (pDevice->LoopBackMode == LM_EXT_LOOP_BACK_MODE)
9333 {
9334 if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
9335 {
9336 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x8c20);
9337 }
9338 else
9339 {
9340 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0007);
9341 LM_ReadPhy(pDevice, BCM5401_AUX_CTRL, &PhyReg18);
9342 PhyReg18 |= 0x8000; /* set loop back */
9343 LM_WritePhy(pDevice, BCM5401_AUX_CTRL, PhyReg18);
9344 }
9345 }
9346 }
9347 else if(LineSpeed == LM_LINE_SPEED_100MBPS)
9348 {
9349 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9350 pDevice->advertising1000 = 0;
9351
9352 if(DuplexMode != LM_DUPLEX_MODE_FULL)
9353 {
9354 Value32 = PHY_AN_AD_100BASETX_HALF;
9355 }
9356 else
9357 {
9358 Value32 = PHY_AN_AD_100BASETX_FULL;
9359 }
9360
9361 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9362 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9363
9364 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9365 pDevice->advertising = Value32;
9366 }
9367 else if(LineSpeed == LM_LINE_SPEED_10MBPS)
9368 {
9369 LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
9370 pDevice->advertising1000 = 0;
9371
9372 if(DuplexMode != LM_DUPLEX_MODE_FULL)
9373 {
9374 Value32 = PHY_AN_AD_10BASET_HALF;
9375 }
9376 else
9377 {
9378 Value32 = PHY_AN_AD_10BASET_FULL;
9379 }
9380
9381 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
9382 Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
9383
9384 LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
9385 pDevice->advertising = Value32;
9386 }
9387 }
9388
9389 /* Force line speed if auto-negotiation is disabled. */
9390 if(pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN)
9391 {
9392 /* This code path is executed only when there is link. */
9393 pDevice->LineSpeed = LineSpeed;
9394 pDevice->DuplexMode = DuplexMode;
9395
9396 /* Force line seepd. */
9397 NewPhyCtrl = 0;
9398 switch(LineSpeed)
9399 {
9400 case LM_LINE_SPEED_10MBPS:
9401 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS;
9402 break;
9403 case LM_LINE_SPEED_100MBPS:
9404 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS;
9405 break;
9406 case LM_LINE_SPEED_1000MBPS:
9407 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
9408 break;
9409 default:
9410 NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
9411 break;
9412 }
9413
9414 if(DuplexMode == LM_DUPLEX_MODE_FULL)
9415 {
9416 NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE;
9417 }
9418
9419 /* Don't do anything if the PHY_CTRL is already what we wanted. */
9420 LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
9421 if(Value32 != NewPhyCtrl)
9422 {
9423 /* Temporary bring the link down before forcing line speed. */
9424 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE);
9425
9426 /* Wait for link to go down. */
9427 for(Cnt = 0; Cnt < 1500; Cnt++)
9428 {
9429 MM_Wait(10);
9430
9431 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
9432 LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
9433
9434 if(!(Value32 & PHY_STATUS_LINK_PASS))
9435 {
9436 MM_Wait(40);
9437 break;
9438 }
9439 }
9440
9441 LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl);
9442 MM_Wait(40);
9443 }
9444 }
9445 else
9446 {
9447 LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
9448 PHY_CTRL_RESTART_AUTO_NEG);
9449 }
9450
9451 return LM_STATUS_SUCCESS;
9452 } /* LM_ForceAutoNegBcm540xPhy */
9453
9454 /******************************************************************************/
9455 /* Description: */
9456 /* */
9457 /* Return: */
9458 /******************************************************************************/
9459 LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
9460 PT3_FWIMG_INFO pFwImg,
9461 LM_UINT32 LoadCpu,
9462 LM_UINT32 StartCpu)
9463 {
9464 LM_UINT32 i;
9465 LM_UINT32 address;
9466 LM_VOID (*Wr_fn)(PLM_DEVICE_BLOCK pDevice,LM_UINT32 Register,LM_UINT32 Value32);
9467 LM_UINT32 (*Rd_fn)(PLM_DEVICE_BLOCK pDevice,LM_UINT32 Register);
9468 LM_UINT32 len;
9469 LM_UINT32 base_addr;
9470
9471 /* BCM4785: Avoid all use of firmware. */
9472 if (pDevice->Flags & SB_CORE_FLAG)
9473 return LM_STATUS_FAILURE;
9474
9475 #ifdef INCLUDE_TCP_SEG_SUPPORT
9476 if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5705)
9477 {
9478 Wr_fn = LM_MemWrInd;
9479 Rd_fn = LM_MemRdInd;
9480 len = LM_GetStkOffLdFirmwareSize(pDevice);
9481 base_addr = T3_NIC_BCM5705_MBUF_POOL_ADDR;
9482 }
9483 else
9484 #endif
9485 {
9486 Wr_fn = LM_RegWrInd;
9487 Rd_fn = LM_RegRdInd;
9488 len = T3_RX_CPU_SPAD_SIZE;
9489 base_addr = T3_RX_CPU_SPAD_ADDR;
9490 }
9491
9492 if (LoadCpu & T3_RX_CPU_ID)
9493 {
9494 if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS)
9495 {
9496 return LM_STATUS_FAILURE;
9497 }
9498
9499 /* First of all clear scrach pad memory */
9500 for (i = 0; i < len; i+=4)
9501 {
9502 Wr_fn(pDevice,base_addr+i,0);
9503 }
9504
9505 /* Copy code first */
9506 address = base_addr + (pFwImg->Text.Offset & 0xffff);
9507 for (i = 0; i <= pFwImg->Text.Length; i+=4)
9508 {
9509 Wr_fn(pDevice,address+i,
9510 ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
9511 }
9512
9513 address = base_addr + (pFwImg->ROnlyData.Offset & 0xffff);
9514 for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4)
9515 {
9516 Wr_fn(pDevice,address+i,
9517 ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
9518 }
9519
9520 address = base_addr + (pFwImg->Data.Offset & 0xffff);
9521 for (i= 0; i <= pFwImg->Data.Length; i+=4)
9522 {
9523 Wr_fn(pDevice,address+i,
9524 ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
9525 }
9526 }
9527
9528 if ((LoadCpu & T3_TX_CPU_ID) &&
9529 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5705))
9530 {
9531 if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS)
9532 {
9533 return LM_STATUS_FAILURE;
9534 }
9535
9536 /* First of all clear scrach pad memory */
9537 for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4)
9538 {
9539 Wr_fn(pDevice,T3_TX_CPU_SPAD_ADDR+i,0);
9540 }
9541
9542 /* Copy code first */
9543 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
9544 for (i= 0; i <= pFwImg->Text.Length; i+=4)
9545 {
9546 Wr_fn(pDevice,address+i,
9547 ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
9548 }
9549
9550 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
9551 for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4)
9552 {
9553 Wr_fn(pDevice,address+i,
9554 ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
9555 }
9556
9557 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
9558 for (i= 0; i <= pFwImg->Data.Length; i+=4)
9559 {
9560 Wr_fn(pDevice,address+i,
9561 ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
9562 }
9563 }
9564
9565 if (StartCpu & T3_RX_CPU_ID)
9566 {
9567 /* Start Rx CPU */
9568 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9569 REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
9570 for (i = 0 ; i < 5; i++)
9571 {
9572 if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC))
9573 break;
9574
9575 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9576 REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
9577 REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
9578 REG_RD_BACK(pDevice,rxCpu.reg.PC);
9579 MM_Wait(1000);
9580 }
9581
9582 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9583 REG_WR(pDevice,rxCpu.reg.mode, 0);
9584 }
9585
9586 if ((StartCpu & T3_TX_CPU_ID) &&
9587 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5705))
9588 {
9589 /* Start Tx CPU */
9590 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9591 REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
9592 for (i = 0 ; i < 5; i++)
9593 {
9594 if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC))
9595 break;
9596
9597 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9598 REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
9599 REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
9600 REG_RD_BACK(pDevice,txCpu.reg.PC);
9601 MM_Wait(1000);
9602 }
9603
9604 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9605 REG_WR(pDevice,txCpu.reg.mode, 0);
9606 }
9607
9608 return LM_STATUS_SUCCESS;
9609 }
9610
9611 LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number)
9612 {
9613 LM_UINT32 i;
9614 LM_STATUS status;
9615
9616 status = LM_STATUS_SUCCESS;
9617
9618 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId) &&
9619 !(cpu_number & T3_RX_CPU_ID))
9620 {
9621 return status;
9622 }
9623
9624 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
9625 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701))
9626 {
9627 status = LM_NVRAM_AcquireLock(pDevice);
9628 }
9629
9630 if (cpu_number & T3_RX_CPU_ID)
9631 {
9632 for (i = 0 ; i < 10000; i++)
9633 {
9634 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9635 REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
9636
9637 if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT)
9638 break;
9639 }
9640
9641 REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
9642 REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
9643 REG_RD_BACK(pDevice,rxCpu.reg.mode);
9644 MM_Wait(10);
9645
9646 if (i == 10000)
9647 status = LM_STATUS_FAILURE;
9648 }
9649
9650 /*
9651 * BCM4785: There is only an Rx CPU for the 5750 derivative in
9652 * the 4785. Don't go any further in this code in order to
9653 * avoid access to the NVRAM arbitration register.
9654 */
9655 if (pDevice->Flags & SB_CORE_FLAG)
9656 return status;
9657
9658 if ((pDevice->Flags & T3_HAS_TWO_CPUS) &&
9659 (cpu_number & T3_TX_CPU_ID))
9660 {
9661 for (i = 0 ; i < 10000; i++)
9662 {
9663 REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
9664 REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
9665
9666 if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT)
9667 break;
9668 }
9669
9670 if (i == 10000)
9671 status = LM_STATUS_FAILURE;
9672 }
9673
9674 if ((T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700) &&
9675 (T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701))
9676 {
9677 if (status != LM_STATUS_SUCCESS)
9678 {
9679 /*
9680 * Some part of this operation failed.
9681 * Just undo our own actions.
9682 */
9683 LM_NVRAM_ReleaseLock(pDevice);
9684 }
9685 else if (!(pDevice->Flags & T3_HAS_TWO_CPUS) ||
9686 cpu_number == (T3_TX_CPU_ID | T3_RX_CPU_ID))
9687 {
9688 /*
9689 * Release our NVRAM arbitration grant along
9690 * with the firmware's arbitration request bit.
9691 */
9692 REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1 | SW_ARB_REQ_CLR0);
9693 REG_RD_BACK(pDevice, Nvram.SwArb);
9694 }
9695 else
9696 {
9697 LM_NVRAM_ReleaseLock(pDevice);
9698
9699 if (LM_NVRAM_AcquireLock(pDevice) == LM_STATUS_SUCCESS)
9700 {
9701 /* All is well. Release the arbitration and continue. */
9702 LM_NVRAM_ReleaseLock(pDevice);
9703 }
9704 else
9705 {
9706 /*
9707 * We've timed out while attempting to get the
9708 * NVRAM arbitration. Assume the cause is that
9709 * the NVRAM has requested arbitration after we
9710 * acquired arbitration the first time, but before
9711 * the CPU was actually halted.
9712 */
9713
9714 /*
9715 * Release our NVRAM arbitration grant along
9716 * with the firmware's arbitration request bit.
9717 */
9718 REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1 | SW_ARB_REQ_CLR0);
9719 REG_RD_BACK(pDevice, Nvram.SwArb);
9720 }
9721 }
9722 }
9723
9724 return status;
9725 }
9726
9727
9728 LM_STATUS
9729 LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
9730 {
9731 int j;
9732 int ret = LM_STATUS_SUCCESS;
9733
9734 if(BlinkDurationSec == 0)
9735 {
9736 BlinkDurationSec = 1;
9737 }
9738 if(BlinkDurationSec > 120)
9739 {
9740 BlinkDurationSec = 120;
9741 }
9742
9743 for(j = 0; j < BlinkDurationSec * 2; j++)
9744 {
9745 if(j % 2)
9746 {
9747 // Turn on the LEDs.
9748 REG_WR(pDevice, MacCtrl.LedCtrl,
9749 LED_CTRL_OVERRIDE_LINK_LED |
9750 LED_CTRL_1000MBPS_LED_ON |
9751 LED_CTRL_100MBPS_LED_ON |
9752 LED_CTRL_10MBPS_LED_ON |
9753 LED_CTRL_OVERRIDE_TRAFFIC_LED |
9754 LED_CTRL_BLINK_TRAFFIC_LED |
9755 LED_CTRL_TRAFFIC_LED);
9756 }
9757 else
9758 {
9759 // Turn off the LEDs.
9760 REG_WR(pDevice, MacCtrl.LedCtrl,
9761 LED_CTRL_OVERRIDE_LINK_LED |
9762 LED_CTRL_OVERRIDE_TRAFFIC_LED);
9763 }
9764 if (MM_Sleep(pDevice, 500) != LM_STATUS_SUCCESS)/* 0.5 second */
9765 {
9766 ret = LM_STATUS_FAILURE;
9767 break;
9768 }
9769 }
9770 REG_WR(pDevice, MacCtrl.LedCtrl, pDevice->LedCtrl);
9771 return ret;
9772 }
9773
9774 LM_STATUS
9775 LM_SwitchClocks(PLM_DEVICE_BLOCK pDevice)
9776 {
9777 LM_UINT32 ClockCtrl;
9778
9779 if(T3_ASIC_5714_FAMILY(pDevice->ChipRevId))
9780 return LM_STATUS_SUCCESS;
9781
9782 ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl);
9783 pDevice->ClockCtrl = ClockCtrl & (T3_PCI_FORCE_CLKRUN |
9784 T3_PCI_CLKRUN_OUTPUT_EN | 0x1f);
9785 if (T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
9786 {
9787 if (ClockCtrl & T3_PCI_625_CORE_CLOCK)
9788 {
9789 /* clear ALT clock first */
9790 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl |
9791 T3_PCI_625_CORE_CLOCK);
9792 MM_Wait(40); /* required delay is 27usec */
9793 }
9794 }
9795 else
9796 {
9797 if (ClockCtrl & T3_PCI_44MHZ_CORE_CLOCK)
9798 {
9799 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl |
9800 T3_PCI_44MHZ_CORE_CLOCK | T3_PCI_SELECT_ALTERNATE_CLOCK);
9801 MM_Wait(40); /* required delay is 27usec */
9802 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl |
9803 T3_PCI_SELECT_ALTERNATE_CLOCK);
9804 MM_Wait(40); /* required delay is 27usec */
9805 }
9806 }
9807
9808 RAW_REG_WR(pDevice, PciCfg.ClockCtrl, pDevice->ClockCtrl);
9809 MM_Wait(40); /* required delay is 27usec */
9810 return LM_STATUS_SUCCESS;
9811 }
9812
9813 int t3_do_dma(PLM_DEVICE_BLOCK pDevice,
9814 LM_PHYSICAL_ADDRESS host_addr_phy, int length,
9815 int dma_read)
9816 {
9817 T3_DMA_DESC dma_desc;
9818 int i;
9819 LM_UINT32 dma_desc_addr;
9820 LM_UINT32 value32;
9821
9822 REG_WR(pDevice, BufMgr.Mode, 0);
9823 REG_WR(pDevice, Ftq.Reset, 0);
9824
9825 dma_desc.host_addr.High = host_addr_phy.High;
9826 dma_desc.host_addr.Low = host_addr_phy.Low;
9827 dma_desc.nic_mbuf = 0x2100;
9828 dma_desc.len = length;
9829 dma_desc.flags = 0x00000005; /* Generate Rx-CPU event */
9830
9831 if (dma_read)
9832 {
9833 dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) |
9834 T3_QID_DMA_HIGH_PRI_READ;
9835 REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE);
9836 }
9837 else
9838 {
9839 dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) |
9840 T3_QID_DMA_HIGH_PRI_WRITE;
9841 REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE);
9842 }
9843
9844 dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR;
9845
9846 /* Writing this DMA descriptor to DMA memory */
9847 for (i = 0; i < sizeof(T3_DMA_DESC); i += 4)
9848 {
9849 value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i));
9850 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i);
9851 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG,
9852 MM_SWAP_LE32(value32));
9853 }
9854 MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0);
9855
9856 if (dma_read)
9857 REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr);
9858 else
9859 REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr);
9860
9861 for (i = 0; i < 40; i++)
9862 {
9863 if (dma_read)
9864 value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue);
9865 else
9866 value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue);
9867
9868 if ((value32 & 0xffff) == dma_desc_addr)
9869 break;
9870
9871 MM_Wait(10);
9872 }
9873
9874 return LM_STATUS_SUCCESS;
9875 }
9876
9877 STATIC LM_STATUS
9878 LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
9879 LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
9880 {
9881 int j;
9882 LM_UINT32 *ptr;
9883 int dma_success = 0;
9884 LM_STATUS ret = LM_STATUS_FAILURE;
9885
9886 if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
9887 T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
9888 {
9889 return LM_STATUS_SUCCESS;
9890 }
9891 while (!dma_success)
9892 {
9893 /* Fill data with incremental patterns */
9894 ptr = (LM_UINT32 *)pBufferVirt;
9895 for (j = 0; j < BufferSize/4; j++)
9896 *ptr++ = j;
9897
9898 if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE)
9899 {
9900 goto LM_DmaTestDone;
9901 }
9902
9903 MM_Wait(40);
9904 ptr = (LM_UINT32 *)pBufferVirt;
9905 /* Fill data with zero */
9906 for (j = 0; j < BufferSize/4; j++)
9907 *ptr++ = 0;
9908
9909 if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE)
9910 {
9911 goto LM_DmaTestDone;
9912 }
9913
9914 MM_Wait(40);
9915 /* Check for data */
9916 ptr = (LM_UINT32 *)pBufferVirt;
9917 for (j = 0; j < BufferSize/4; j++)
9918 {
9919 if (*ptr++ != j)
9920 {
9921 if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK)
9922 != DMA_CTRL_WRITE_BOUNDARY_16)
9923 {
9924 pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl &
9925 ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
9926 DMA_CTRL_WRITE_BOUNDARY_16;
9927 REG_WR(pDevice, PciCfg.DmaReadWriteCtrl,
9928 pDevice->DmaReadWriteCtrl);
9929 break;
9930 }
9931 else
9932 {
9933 goto LM_DmaTestDone;
9934 }
9935 }
9936 }
9937 if (j == (BufferSize/4))
9938 dma_success = 1;
9939 }
9940 ret = LM_STATUS_SUCCESS;
9941 LM_DmaTestDone:
9942 memset(pBufferVirt, 0, BufferSize);
9943 return ret;
9944 }
9945
9946 void
9947 LM_Add32To64Counter(LM_UINT32 Counter32, T3_64BIT_REGISTER *Counter64)
9948 {
9949 Counter64->Low += Counter32;
9950 if (Counter64->Low < Counter32)
9951 {
9952 Counter64->High++;
9953 }
9954 }
9955
9956 LM_STATUS
9957 LM_GetStats(PLM_DEVICE_BLOCK pDevice)
9958 {
9959 PT3_STATS_BLOCK pStats = (PT3_STATS_BLOCK) pDevice->pStatsBlkVirt;
9960
9961 if(!T3_ASIC_IS_5705_BEYOND(pDevice->ChipRevId))
9962 {
9963 return LM_STATUS_FAILURE;
9964 }
9965
9966 if (pStats == 0)
9967 {
9968 return LM_STATUS_FAILURE;
9969 }
9970 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutOctets),
9971 &pStats->ifHCOutOctets);
9972 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsCollisions),
9973 &pStats->etherStatsCollisions);
9974 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.outXonSent),
9975 &pStats->outXonSent);
9976 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.outXoffSent),
9977 &pStats->outXoffSent);
9978 LM_Add32To64Counter(REG_RD(pDevice,
9979 MacCtrl.dot3StatsInternalMacTransmitErrors),
9980 &pStats->dot3StatsInternalMacTransmitErrors);
9981 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsSingleCollisionFrames),
9982 &pStats->dot3StatsSingleCollisionFrames);
9983 LM_Add32To64Counter(REG_RD(pDevice,
9984 MacCtrl.dot3StatsMultipleCollisionFrames),
9985 &pStats->dot3StatsMultipleCollisionFrames);
9986 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsDeferredTransmissions),
9987 &pStats->dot3StatsDeferredTransmissions);
9988 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsExcessiveCollisions),
9989 &pStats->dot3StatsExcessiveCollisions);
9990 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsLateCollisions),
9991 &pStats->dot3StatsLateCollisions);
9992 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutUcastPkts),
9993 &pStats->ifHCOutUcastPkts);
9994 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutMulticastPkts),
9995 &pStats->ifHCOutMulticastPkts);
9996 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCOutBroadcastPkts),
9997 &pStats->ifHCOutBroadcastPkts);
9998 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInOctets),
9999 &pStats->ifHCInOctets);
10000 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsFragments),
10001 &pStats->etherStatsFragments);
10002 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInUcastPkts),
10003 &pStats->ifHCInUcastPkts);
10004 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInMulticastPkts),
10005 &pStats->ifHCInMulticastPkts);
10006 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.ifHCInBroadcastPkts),
10007 &pStats->ifHCInBroadcastPkts);
10008 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsFCSErrors),
10009 &pStats->dot3StatsFCSErrors);
10010 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsAlignmentErrors),
10011 &pStats->dot3StatsAlignmentErrors);
10012 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.xonPauseFramesReceived),
10013 &pStats->xonPauseFramesReceived);
10014 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.xoffPauseFramesReceived),
10015 &pStats->xoffPauseFramesReceived);
10016 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.macControlFramesReceived),
10017 &pStats->macControlFramesReceived);
10018 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.xoffStateEntered),
10019 &pStats->xoffStateEntered);
10020 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.dot3StatsFramesTooLong),
10021 &pStats->dot3StatsFramesTooLong);
10022 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsJabbers),
10023 &pStats->etherStatsJabbers);
10024 LM_Add32To64Counter(REG_RD(pDevice, MacCtrl.etherStatsUndersizePkts),
10025 &pStats->etherStatsUndersizePkts);
10026
10027 return LM_STATUS_SUCCESS;
10028 }
Tomato firmware and modifications.