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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / sound / sparc / dbri.c
blobe07085a7cfc340baafc170f3cd876c2f2980c694
1 /*
2 * Driver for DBRI sound chip found on Sparcs.
3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
4 *
5 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
6 *
7 * Based entirely upon drivers/sbus/audio/dbri.c which is:
8 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
9 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
10 *
11 * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
12 * on Sun SPARCstation 10, 20, LX and Voyager models.
13 *
14 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
15 * data time multiplexer with ISDN support (aka T7259)
16 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
17 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
18 * Documentation:
19 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from
20 * Sparc Technology Business (courtesy of Sun Support)
21 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
22 * available from the Lucent (formarly AT&T microelectronics) home
23 * page.
24 * - http://www.freesoft.org/Linux/DBRI/
25 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
26 * Interfaces: CHI, Audio In & Out, 2 bits parallel
27 * Documentation: from the Crystal Semiconductor home page.
28 *
29 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
30 * memory and a serial device (long pipes, nr 0-15) or between two serial
31 * devices (short pipes, nr 16-31), or simply send a fixed data to a serial
32 * device (short pipes).
33 * A timeslot defines the bit-offset and nr of bits read from a serial device.
34 * The timeslots are linked to 6 circular lists, one for each direction for
35 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
36 * (the second one is a monitor/tee pipe, valid only for serial input).
37 *
38 * The mmcodec is connected via the CHI bus and needs the data & some
39 * parameters (volume, output selection) timemultiplexed in 8 byte
40 * chunks. It also has a control mode, which serves for audio format setting.
41 *
42 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
43 * the same CHI bus, so I thought perhaps it is possible to use the onboard
44 * & the speakerbox codec simultanously, giving 2 (not very independent :-)
45 * audio devices. But the SUN HW group decided against it, at least on my
46 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
47 * connected.
48 *
49 * I've tried to stick to the following function naming conventions:
50 * snd_* ALSA stuff
51 * cs4215_* CS4215 codec specific stuff
52 * dbri_* DBRI high-level stuff
53 * other DBRI low-level stuff
54 */
55
56 #include <sound/driver.h>
57 #include <linux/interrupt.h>
58 #include <linux/delay.h>
59
60 #include <sound/core.h>
61 #include <sound/pcm.h>
62 #include <sound/pcm_params.h>
63 #include <sound/info.h>
64 #include <sound/control.h>
65 #include <sound/initval.h>
66
67 #include <asm/irq.h>
68 #include <asm/io.h>
69 #include <asm/sbus.h>
70 #include <asm/atomic.h>
71
72 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
73 MODULE_DESCRIPTION("Sun DBRI");
74 MODULE_LICENSE("GPL");
75 MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
76
77 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
78 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
79 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
80
81 module_param_array(index, int, NULL, 0444);
82 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
83 module_param_array(id, charp, NULL, 0444);
84 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
85 module_param_array(enable, bool, NULL, 0444);
86 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
87
88 #undef DBRI_DEBUG
89
90 #define D_INT (1<<0)
91 #define D_GEN (1<<1)
92 #define D_CMD (1<<2)
93 #define D_MM (1<<3)
94 #define D_USR (1<<4)
95 #define D_DESC (1<<5)
96
97 static int dbri_debug;
98 module_param(dbri_debug, int, 0644);
99 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
100
101 #ifdef DBRI_DEBUG
102 static char *cmds[] = {
103 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
104 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
105 };
106
107 #define dprintk(a, x...) if(dbri_debug & a) printk(KERN_DEBUG x)
108
109 #else
110 #define dprintk(a, x...) do { } while (0)
111
112 #endif /* DBRI_DEBUG */
113
114 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
115 (intr << 27) | \
116 value)
117
118 /***************************************************************************
119 CS4215 specific definitions and structures
120 ****************************************************************************/
121
122 struct cs4215 {
123 __u8 data[4]; /* Data mode: Time slots 5-8 */
124 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
125 __u8 onboard;
126 __u8 offset; /* Bit offset from frame sync to time slot 1 */
127 volatile __u32 status;
128 volatile __u32 version;
129 __u8 precision; /* In bits, either 8 or 16 */
130 __u8 channels; /* 1 or 2 */
131 };
132
133 /*
134 * Control mode first
135 */
136
137 /* Time Slot 1, Status register */
138 #define CS4215_CLB (1<<2) /* Control Latch Bit */
139 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
140 /* 0: line: 2.8V, speaker 8V */
141 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
142 #define CS4215_RSRVD_1 (1<<5)
143
144 /* Time Slot 2, Data Format Register */
145 #define CS4215_DFR_LINEAR16 0
146 #define CS4215_DFR_ULAW 1
147 #define CS4215_DFR_ALAW 2
148 #define CS4215_DFR_LINEAR8 3
149 #define CS4215_DFR_STEREO (1<<2)
150 static struct {
151 unsigned short freq;
152 unsigned char xtal;
153 unsigned char csval;
154 } CS4215_FREQ[] = {
155 { 8000, (1 << 4), (0 << 3) },
156 { 16000, (1 << 4), (1 << 3) },
157 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
158 { 32000, (1 << 4), (3 << 3) },
159 /* { NA, (1 << 4), (4 << 3) }, */
160 /* { NA, (1 << 4), (5 << 3) }, */
161 { 48000, (1 << 4), (6 << 3) },
162 { 9600, (1 << 4), (7 << 3) },
163 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
164 { 11025, (2 << 4), (1 << 3) },
165 { 18900, (2 << 4), (2 << 3) },
166 { 22050, (2 << 4), (3 << 3) },
167 { 37800, (2 << 4), (4 << 3) },
168 { 44100, (2 << 4), (5 << 3) },
169 { 33075, (2 << 4), (6 << 3) },
170 { 6615, (2 << 4), (7 << 3) },
171 { 0, 0, 0}
172 };
173
174 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
175
176 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
177
178 /* Time Slot 3, Serial Port Control register */
179 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
180 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
181 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
182 #define CS4215_BSEL_128 (1<<2)
183 #define CS4215_BSEL_256 (2<<2)
184 #define CS4215_MCK_MAST (0<<4) /* Master clock */
185 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
186 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
187 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
188 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
189
190 /* Time Slot 4, Test Register */
191 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
192 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
193
194 /* Time Slot 5, Parallel Port Register */
195 /* Read only here and the same as the in data mode */
196
197 /* Time Slot 6, Reserved */
198
199 /* Time Slot 7, Version Register */
200 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
201
202 /* Time Slot 8, Reserved */
203
204 /*
205 * Data mode
206 */
207 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
208
209 /* Time Slot 5, Output Setting */
210 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
211 #define CS4215_LE (1<<6) /* Line Out Enable */
212 #define CS4215_HE (1<<7) /* Headphone Enable */
213
214 /* Time Slot 6, Output Setting */
215 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
216 #define CS4215_SE (1<<6) /* Speaker Enable */
217 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
218
219 /* Time Slot 7, Input Setting */
220 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
221 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
222 #define CS4215_OVR (1<<5) /* 1: Overrange condition occurred */
223 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
224 #define CS4215_PIO1 (1<<7)
225
226 /* Time Slot 8, Input Setting */
227 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
228 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
229
230 /***************************************************************************
231 DBRI specific definitions and structures
232 ****************************************************************************/
233
234 /* DBRI main registers */
235 #define REG0 0x00UL /* Status and Control */
236 #define REG1 0x04UL /* Mode and Interrupt */
237 #define REG2 0x08UL /* Parallel IO */
238 #define REG3 0x0cUL /* Test */
239 #define REG8 0x20UL /* Command Queue Pointer */
240 #define REG9 0x24UL /* Interrupt Queue Pointer */
241
242 #define DBRI_NO_CMDS 64
243 #define DBRI_INT_BLK 64
244 #define DBRI_NO_DESCS 64
245 #define DBRI_NO_PIPES 32
246 #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
247
248 #define DBRI_REC 0
249 #define DBRI_PLAY 1
250 #define DBRI_NO_STREAMS 2
251
252 /* One transmit/receive descriptor */
253 /* When ba != 0 descriptor is used */
254 struct dbri_mem {
255 volatile __u32 word1;
256 __u32 ba; /* Transmit/Receive Buffer Address */
257 __u32 nda; /* Next Descriptor Address */
258 volatile __u32 word4;
259 };
260
261 /* This structure is in a DMA region where it can accessed by both
262 * the CPU and the DBRI
263 */
264 struct dbri_dma {
265 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
266 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
267 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
268 };
269
270 #define dbri_dma_off(member, elem) \
271 ((u32)(unsigned long) \
272 (&(((struct dbri_dma *)0)->member[elem])))
273
274 enum in_or_out { PIPEinput, PIPEoutput };
275
276 struct dbri_pipe {
277 u32 sdp; /* SDP command word */
278 int nextpipe; /* Next pipe in linked list */
279 int length; /* Length of timeslot (bits) */
280 int first_desc; /* Index of first descriptor */
281 int desc; /* Index of active descriptor */
282 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
283 };
284
285 /* Per stream (playback or record) information */
286 struct dbri_streaminfo {
287 struct snd_pcm_substream *substream;
288 u32 dvma_buffer; /* Device view of Alsa DMA buffer */
289 int size; /* Size of DMA buffer */
290 size_t offset; /* offset in user buffer */
291 int pipe; /* Data pipe used */
292 int left_gain; /* mixer elements */
293 int right_gain;
294 };
295
296 /* This structure holds the information for both chips (DBRI & CS4215) */
297 struct snd_dbri {
298 struct snd_card *card; /* ALSA card */
299
300 int regs_size, irq; /* Needed for unload */
301 struct sbus_dev *sdev; /* SBUS device info */
302 spinlock_t lock;
303
304 struct dbri_dma *dma; /* Pointer to our DMA block */
305 u32 dma_dvma; /* DBRI visible DMA address */
306
307 void __iomem *regs; /* dbri HW regs */
308 int dbri_irqp; /* intr queue pointer */
309
310 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
311 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
312 spinlock_t cmdlock; /* Protects cmd queue accesses */
313 s32 *cmdptr; /* Pointer to the last queued cmd */
314
315 int chi_bpf;
316
317 struct cs4215 mm; /* mmcodec special info */
318 /* per stream (playback/record) info */
319 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
320
321 struct snd_dbri *next;
322 };
323
324 #define DBRI_MAX_VOLUME 63 /* Output volume */
325 #define DBRI_MAX_GAIN 15 /* Input gain */
326
327 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
328 #define D_P (1<<15) /* Program command & queue pointer valid */
329 #define D_G (1<<14) /* Allow 4-Word SBus Burst */
330 #define D_S (1<<13) /* Allow 16-Word SBus Burst */
331 #define D_E (1<<12) /* Allow 8-Word SBus Burst */
332 #define D_X (1<<7) /* Sanity Timer Disable */
333 #define D_T (1<<6) /* Permit activation of the TE interface */
334 #define D_N (1<<5) /* Permit activation of the NT interface */
335 #define D_C (1<<4) /* Permit activation of the CHI interface */
336 #define D_F (1<<3) /* Force Sanity Timer Time-Out */
337 #define D_D (1<<2) /* Disable Master Mode */
338 #define D_H (1<<1) /* Halt for Analysis */
339 #define D_R (1<<0) /* Soft Reset */
340
341 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
342 #define D_LITTLE_END (1<<8) /* Byte Order */
343 #define D_BIG_END (0<<8) /* Byte Order */
344 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (readonly) */
345 #define D_MLE (1<<3) /* Multiple Late Error on SBus (readonly) */
346 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (readonly) */
347 #define D_MBE (1<<1) /* Burst Error on SBus (readonly) */
348 #define D_IR (1<<0) /* Interrupt Indicator (readonly) */
349
350 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
351 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */
352 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */
353 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */
354 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */
355 #define D_ENPIO (0xf0) /* Enable all the pins */
356 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
357 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
358 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
359 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
360
361 /* DBRI Commands (Page 20) */
362 #define D_WAIT 0x0 /* Stop execution */
363 #define D_PAUSE 0x1 /* Flush long pipes */
364 #define D_JUMP 0x2 /* New command queue */
365 #define D_IIQ 0x3 /* Initialize Interrupt Queue */
366 #define D_REX 0x4 /* Report command execution via interrupt */
367 #define D_SDP 0x5 /* Setup Data Pipe */
368 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
369 #define D_DTS 0x7 /* Define Time Slot */
370 #define D_SSP 0x8 /* Set short Data Pipe */
371 #define D_CHI 0x9 /* Set CHI Global Mode */
372 #define D_NT 0xa /* NT Command */
373 #define D_TE 0xb /* TE Command */
374 #define D_CDEC 0xc /* Codec setup */
375 #define D_TEST 0xd /* No comment */
376 #define D_CDM 0xe /* CHI Data mode command */
377
378 /* Special bits for some commands */
379 #define D_PIPE(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
380
381 /* Setup Data Pipe */
382 /* IRM */
383 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value rcvd */
384 #define D_SDP_CHANGE (2<<18) /* Report any changes */
385 #define D_SDP_EVERY (3<<18) /* Report any changes */
386 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */
387 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
388
389 /* Pipe data MODE */
390 #define D_SDP_MEM (0<<13) /* To/from memory */
391 #define D_SDP_HDLC (2<<13)
392 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
393 #define D_SDP_SER (4<<13) /* Serial to serial */
394 #define D_SDP_FIXED (6<<13) /* Short only */
395 #define D_SDP_MODE(v) ((v)&(7<<13))
396
397 #define D_SDP_TO_SER (1<<12) /* Direction */
398 #define D_SDP_FROM_SER (0<<12) /* Direction */
399 #define D_SDP_MSB (1<<11) /* Bit order within Byte */
400 #define D_SDP_LSB (0<<11) /* Bit order within Byte */
401 #define D_SDP_P (1<<10) /* Pointer Valid */
402 #define D_SDP_A (1<<8) /* Abort */
403 #define D_SDP_C (1<<7) /* Clear */
404
405 /* Define Time Slot */
406 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
407 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
408 #define D_DTS_INS (1<<15) /* Insert Time Slot */
409 #define D_DTS_DEL (0<<15) /* Delete Time Slot */
410 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
411 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
412
413 /* Time Slot defines */
414 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
415 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
416 #define D_TS_DI (1<<13) /* Data Invert */
417 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
418 #define D_TS_MONITOR (2<<10) /* Monitor pipe */
419 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
420 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */
421 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
422 #define D_TS_NEXT(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
423
424 /* Concentration Highway Interface Modes */
425 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
426 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
427 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
428 #define D_CHI_OD (1<<13) /* Open Drain Enable */
429 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
430 #define D_CHI_FD (1<<11) /* Frame Drive */
431 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
432
433 /* NT: These are here for completeness */
434 #define D_NT_FBIT (1<<17) /* Frame Bit */
435 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
436 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
437 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
438 #define D_NT_ISNT (1<<13) /* Configfure interface as NT */
439 #define D_NT_FT (1<<12) /* Fixed Timing */
440 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
441 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */
442 #define D_NT_ACT (1<<9) /* Activate Interface */
443 #define D_NT_MFE (1<<8) /* Multiframe Enable */
444 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
445 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
446 #define D_NT_FACT (1<<1) /* Force Activation */
447 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
448
449 /* Codec Setup */
450 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
451 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
452 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
453
454 /* Test */
455 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
456 #define D_TEST_SIZE(v) ((v)<<11) /* */
457 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
458 #define D_TEST_PROC 0x6 /* MicroProcessor test */
459 #define D_TEST_SER 0x7 /* Serial-Controller test */
460 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
461 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
462 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
463 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
464 #define D_TEST_DUMP 0xe /* ROM Dump */
465
466 /* CHI Data Mode */
467 #define D_CDM_THI (1<<8) /* Transmit Data on CHIDR Pin */
468 #define D_CDM_RHI (1<<7) /* Receive Data on CHIDX Pin */
469 #define D_CDM_RCE (1<<6) /* Receive on Rising Edge of CHICK */
470 #define D_CDM_XCE (1<<2) /* Transmit Data on Rising Edge of CHICK */
471 #define D_CDM_XEN (1<<1) /* Transmit Highway Enable */
472 #define D_CDM_REN (1<<0) /* Receive Highway Enable */
473
474 /* The Interrupts */
475 #define D_INTR_BRDY 1 /* Buffer Ready for processing */
476 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
477 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
478 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
479 #define D_INTR_EOL 5 /* End of List */
480 #define D_INTR_CMDI 6 /* Command has bean read */
481 #define D_INTR_XCMP 8 /* Transmission of frame complete */
482 #define D_INTR_SBRI 9 /* BRI status change info */
483 #define D_INTR_FXDT 10 /* Fixed data change */
484 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
485 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
486 #define D_INTR_DBYT 12 /* Dropped by frame slip */
487 #define D_INTR_RBYT 13 /* Repeated by frame slip */
488 #define D_INTR_LINT 14 /* Lost Interrupt */
489 #define D_INTR_UNDR 15 /* DMA underrun */
490
491 #define D_INTR_TE 32
492 #define D_INTR_NT 34
493 #define D_INTR_CHI 36
494 #define D_INTR_CMD 38
495
496 #define D_INTR_GETCHAN(v) (((v)>>24) & 0x3f)
497 #define D_INTR_GETCODE(v) (((v)>>20) & 0xf)
498 #define D_INTR_GETCMD(v) (((v)>>16) & 0xf)
499 #define D_INTR_GETVAL(v) ((v) & 0xffff)
500 #define D_INTR_GETRVAL(v) ((v) & 0xfffff)
501
502 #define D_P_0 0 /* TE receive anchor */
503 #define D_P_1 1 /* TE transmit anchor */
504 #define D_P_2 2 /* NT transmit anchor */
505 #define D_P_3 3 /* NT receive anchor */
506 #define D_P_4 4 /* CHI send data */
507 #define D_P_5 5 /* CHI receive data */
508 #define D_P_6 6 /* */
509 #define D_P_7 7 /* */
510 #define D_P_8 8 /* */
511 #define D_P_9 9 /* */
512 #define D_P_10 10 /* */
513 #define D_P_11 11 /* */
514 #define D_P_12 12 /* */
515 #define D_P_13 13 /* */
516 #define D_P_14 14 /* */
517 #define D_P_15 15 /* */
518 #define D_P_16 16 /* CHI anchor pipe */
519 #define D_P_17 17 /* CHI send */
520 #define D_P_18 18 /* CHI receive */
521 #define D_P_19 19 /* CHI receive */
522 #define D_P_20 20 /* CHI receive */
523 #define D_P_21 21 /* */
524 #define D_P_22 22 /* */
525 #define D_P_23 23 /* */
526 #define D_P_24 24 /* */
527 #define D_P_25 25 /* */
528 #define D_P_26 26 /* */
529 #define D_P_27 27 /* */
530 #define D_P_28 28 /* */
531 #define D_P_29 29 /* */
532 #define D_P_30 30 /* */
533 #define D_P_31 31 /* */
534
535 /* Transmit descriptor defines */
536 #define DBRI_TD_F (1<<31) /* End of Frame */
537 #define DBRI_TD_D (1<<30) /* Do not append CRC */
538 #define DBRI_TD_CNT(v) ((v)<<16) /* Number of valid bytes in the buffer */
539 #define DBRI_TD_B (1<<15) /* Final interrupt */
540 #define DBRI_TD_M (1<<14) /* Marker interrupt */
541 #define DBRI_TD_I (1<<13) /* Transmit Idle Characters */
542 #define DBRI_TD_FCNT(v) (v) /* Flag Count */
543 #define DBRI_TD_UNR (1<<3) /* Underrun: transmitter is out of data */
544 #define DBRI_TD_ABT (1<<2) /* Abort: frame aborted */
545 #define DBRI_TD_TBC (1<<0) /* Transmit buffer Complete */
546 #define DBRI_TD_STATUS(v) ((v)&0xff) /* Transmit status */
547 /* Maximum buffer size per TD: almost 8Kb */
548 #define DBRI_TD_MAXCNT ((1 << 13) - 4)
549
550 /* Receive descriptor defines */
551 #define DBRI_RD_F (1<<31) /* End of Frame */
552 #define DBRI_RD_C (1<<30) /* Completed buffer */
553 #define DBRI_RD_B (1<<15) /* Final interrupt */
554 #define DBRI_RD_M (1<<14) /* Marker interrupt */
555 #define DBRI_RD_BCNT(v) (v) /* Buffer size */
556 #define DBRI_RD_CRC (1<<7) /* 0: CRC is correct */
557 #define DBRI_RD_BBC (1<<6) /* 1: Bad Byte received */
558 #define DBRI_RD_ABT (1<<5) /* Abort: frame aborted */
559 #define DBRI_RD_OVRN (1<<3) /* Overrun: data lost */
560 #define DBRI_RD_STATUS(v) ((v)&0xff) /* Receive status */
561 #define DBRI_RD_CNT(v) (((v)>>16)&0x1fff) /* Valid bytes in the buffer */
562
563 /* stream_info[] access */
564 /* Translate the ALSA direction into the array index */
565 #define DBRI_STREAMNO(substream) \
566 (substream->stream == \
567 SNDRV_PCM_STREAM_PLAYBACK? DBRI_PLAY: DBRI_REC)
568
569 /* Return a pointer to dbri_streaminfo */
570 #define DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)]
571
572 static struct snd_dbri *dbri_list; /* All DBRI devices */
573
574 /*
575 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
576 * So we have to reverse the bits. Note: not all bit lengths are supported
577 */
578 static __u32 reverse_bytes(__u32 b, int len)
579 {
580 switch (len) {
581 case 32:
582 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
583 case 16:
584 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
585 case 8:
586 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
587 case 4:
588 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
589 case 2:
590 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
591 case 1:
592 case 0:
593 break;
594 default:
595 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
596 };
597
598 return b;
599 }
600
601 /*
602 ****************************************************************************
603 ************** DBRI initialization and command synchronization *************
604 ****************************************************************************
605
606 Commands are sent to the DBRI by building a list of them in memory,
607 then writing the address of the first list item to DBRI register 8.
608 The list is terminated with a WAIT command, which generates a
609 CPU interrupt to signal completion.
610
611 Since the DBRI can run in parallel with the CPU, several means of
612 synchronization present themselves. The method implemented here is only
613 use of the dbri_cmdwait() to wait for execution of batch of sent commands.
614
615 A circular command buffer is used here. A new command is being added
616 while another can be executed. The scheme works by adding two WAIT commands
617 after each sent batch of commands. When the next batch is prepared it is
618 added after the WAIT commands then the WAITs are replaced with single JUMP
619 command to the new batch. The the DBRI is forced to reread the last WAIT
620 command (replaced by the JUMP by then). If the DBRI is still executing
621 previous commands the request to reread the WAIT command is ignored.
622
623 Every time a routine wants to write commands to the DBRI, it must
624 first call dbri_cmdlock() and get pointer to a free space in
625 dbri->dma->cmd buffer. After this, the commands can be written to
626 the buffer, and dbri_cmdsend() is called with the final pointer value
627 to send them to the DBRI.
628
629 */
630
631 #define MAXLOOPS 20
632 /*
633 * Wait for the current command string to execute
634 */
635 static void dbri_cmdwait(struct snd_dbri *dbri)
636 {
637 int maxloops = MAXLOOPS;
638 unsigned long flags;
639
640 /* Delay if previous commands are still being processed */
641 spin_lock_irqsave(&dbri->lock, flags);
642 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
643 spin_unlock_irqrestore(&dbri->lock, flags);
644 msleep_interruptible(1);
645 spin_lock_irqsave(&dbri->lock, flags);
646 }
647 spin_unlock_irqrestore(&dbri->lock, flags);
648
649 if (maxloops == 0) {
650 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
651 } else {
652 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
653 MAXLOOPS - maxloops - 1);
654 }
655 }
656 /*
657 * Lock the command queue and returns pointer to a space for len cmd words
658 * It locks the cmdlock spinlock.
659 */
660 static s32 *dbri_cmdlock(struct snd_dbri * dbri, int len)
661 {
662 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
663 len += 2;
664 spin_lock(&dbri->cmdlock);
665 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
666 return dbri->cmdptr + 2;
667 else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma)
668 return dbri->dma->cmd;
669 else
670 printk(KERN_ERR "DBRI: no space for commands.");
671
672 return NULL;
673 }
674
675 /*
676 * Send prepared cmd string. It works by writing a JUMP cmd into
677 * the last WAIT cmd and force DBRI to reread the cmd.
678 * The JUMP cmd points to the new cmd string.
679 * It also releases the cmdlock spinlock.
680 *
681 * Lock must be held before calling this.
682 */
683 static void dbri_cmdsend(struct snd_dbri * dbri, s32 * cmd,int len)
684 {
685 s32 tmp, addr;
686 static int wait_id = 0;
687
688 wait_id++;
689 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
690 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
691 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
692
693 /* Replace the last command with JUMP */
694 addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32);
695 *(dbri->cmdptr+1) = addr;
696 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
697
698 #ifdef DBRI_DEBUG
699 if (cmd > dbri->cmdptr) {
700 s32 *ptr;
701
702 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
703 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
704 } else {
705 s32 *ptr = dbri->cmdptr;
706
707 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
708 ptr++;
709 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
710 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++) {
711 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
712 }
713 }
714 #endif
715
716 /* Reread the last command */
717 tmp = sbus_readl(dbri->regs + REG0);
718 tmp |= D_P;
719 sbus_writel(tmp, dbri->regs + REG0);
720
721 dbri->cmdptr = cmd;
722 spin_unlock(&dbri->cmdlock);
723 }
724
725 /* Lock must be held when calling this */
726 static void dbri_reset(struct snd_dbri * dbri)
727 {
728 int i;
729 u32 tmp;
730
731 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
732 sbus_readl(dbri->regs + REG0),
733 sbus_readl(dbri->regs + REG2),
734 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
735
736 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
737 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
738 udelay(10);
739
740 /* A brute approach - DBRI falls back to working burst size by itself
741 * On SS20 D_S does not work, so do not try so high. */
742 tmp = sbus_readl(dbri->regs + REG0);
743 tmp |= D_G | D_E;
744 tmp &= ~D_S;
745 sbus_writel(tmp, dbri->regs + REG0);
746 }
747
748 /* Lock must not be held before calling this */
749 static void dbri_initialize(struct snd_dbri * dbri)
750 {
751 s32 *cmd;
752 u32 dma_addr;
753 unsigned long flags;
754 int n;
755
756 spin_lock_irqsave(&dbri->lock, flags);
757
758 dbri_reset(dbri);
759
760 /* Initialize pipes */
761 for (n = 0; n < DBRI_NO_PIPES; n++)
762 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
763
764 spin_lock_init(&dbri->cmdlock);
765 /*
766 * Initialize the interrupt ringbuffer.
767 */
768 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
769 dbri->dma->intr[0] = dma_addr;
770 dbri->dbri_irqp = 1;
771 /*
772 * Set up the interrupt queue
773 */
774 spin_lock(&dbri->cmdlock);
775 cmd = dbri->cmdptr = dbri->dma->cmd;
776 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
777 *(cmd++) = dma_addr;
778 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
779 dbri->cmdptr = cmd;
780 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
781 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
782 dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0);
783 sbus_writel(dma_addr, dbri->regs + REG8);
784 spin_unlock(&dbri->cmdlock);
785
786 spin_unlock_irqrestore(&dbri->lock, flags);
787 dbri_cmdwait(dbri);
788 }
789
790 /*
791 ****************************************************************************
792 ************************** DBRI data pipe management ***********************
793 ****************************************************************************
794
795 While DBRI control functions use the command and interrupt buffers, the
796 main data path takes the form of data pipes, which can be short (command
797 and interrupt driven), or long (attached to DMA buffers). These functions
798 provide a rudimentary means of setting up and managing the DBRI's pipes,
799 but the calling functions have to make sure they respect the pipes' linked
800 list ordering, among other things. The transmit and receive functions
801 here interface closely with the transmit and receive interrupt code.
802
803 */
804 static int pipe_active(struct snd_dbri * dbri, int pipe)
805 {
806 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
807 }
808
809 /* reset_pipe(dbri, pipe)
810 *
811 * Called on an in-use pipe to clear anything being transmitted or received
812 * Lock must be held before calling this.
813 */
814 static void reset_pipe(struct snd_dbri * dbri, int pipe)
815 {
816 int sdp;
817 int desc;
818 s32 *cmd;
819
820 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
821 printk(KERN_ERR "DBRI: reset_pipe called with illegal pipe number\n");
822 return;
823 }
824
825 sdp = dbri->pipes[pipe].sdp;
826 if (sdp == 0) {
827 printk(KERN_ERR "DBRI: reset_pipe called on uninitialized pipe\n");
828 return;
829 }
830
831 cmd = dbri_cmdlock(dbri, 3);
832 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
833 *(cmd++) = 0;
834 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
835 dbri_cmdsend(dbri, cmd, 3);
836
837 desc = dbri->pipes[pipe].first_desc;
838 if ( desc >= 0)
839 do {
840 dbri->dma->desc[desc].nda = dbri->dma->desc[desc].ba = 0;
841 desc = dbri->next_desc[desc];
842 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
843
844 dbri->pipes[pipe].desc = -1;
845 dbri->pipes[pipe].first_desc = -1;
846 }
847
848 /*
849 * Lock must be held before calling this.
850 */
851 static void setup_pipe(struct snd_dbri * dbri, int pipe, int sdp)
852 {
853 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
854 printk(KERN_ERR "DBRI: setup_pipe called with illegal pipe number\n");
855 return;
856 }
857
858 if ((sdp & 0xf800) != sdp) {
859 printk(KERN_ERR "DBRI: setup_pipe called with strange SDP value\n");
860 /* sdp &= 0xf800; */
861 }
862
863 /* If this is a fixed receive pipe, arrange for an interrupt
864 * every time its data changes
865 */
866 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
867 sdp |= D_SDP_CHANGE;
868
869 sdp |= D_PIPE(pipe);
870 dbri->pipes[pipe].sdp = sdp;
871 dbri->pipes[pipe].desc = -1;
872 dbri->pipes[pipe].first_desc = -1;
873
874 reset_pipe(dbri, pipe);
875 }
876
877 /*
878 * Lock must be held before calling this.
879 */
880 static void link_time_slot(struct snd_dbri * dbri, int pipe,
881 int prevpipe, int nextpipe,
882 int length, int cycle)
883 {
884 s32 *cmd;
885 int val;
886
887 if (pipe < 0 || pipe > DBRI_MAX_PIPE
888 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
889 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
890 printk(KERN_ERR
891 "DBRI: link_time_slot called with illegal pipe number\n");
892 return;
893 }
894
895 if (dbri->pipes[pipe].sdp == 0
896 || dbri->pipes[prevpipe].sdp == 0
897 || dbri->pipes[nextpipe].sdp == 0) {
898 printk(KERN_ERR "DBRI: link_time_slot called on uninitialized pipe\n");
899 return;
900 }
901
902 dbri->pipes[prevpipe].nextpipe = pipe;
903 dbri->pipes[pipe].nextpipe = nextpipe;
904 dbri->pipes[pipe].length = length;
905
906 cmd = dbri_cmdlock(dbri, 4);
907
908 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
909 /* Deal with CHI special case:
910 * "If transmission on edges 0 or 1 is desired, then cycle n
911 * (where n = # of bit times per frame...) must be used."
912 * - DBRI data sheet, page 11
913 */
914 if (prevpipe == 16 && cycle == 0)
915 cycle = dbri->chi_bpf;
916
917 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
918 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
919 *(cmd++) = 0;
920 *(cmd++) =
921 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
922 } else {
923 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
924 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
925 *(cmd++) =
926 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
927 *(cmd++) = 0;
928 }
929 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
930
931 dbri_cmdsend(dbri, cmd, 4);
932 }
933
934 #if 0
935 /*
936 * Lock must be held before calling this.
937 */
938 static void unlink_time_slot(struct snd_dbri * dbri, int pipe,
939 enum in_or_out direction, int prevpipe,
940 int nextpipe)
941 {
942 s32 *cmd;
943 int val;
944
945 if (pipe < 0 || pipe > DBRI_MAX_PIPE
946 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
947 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
948 printk(KERN_ERR
949 "DBRI: unlink_time_slot called with illegal pipe number\n");
950 return;
951 }
952
953 cmd = dbri_cmdlock(dbri, 4);
954
955 if (direction == PIPEinput) {
956 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
957 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
958 *(cmd++) = D_TS_NEXT(nextpipe);
959 *(cmd++) = 0;
960 } else {
961 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
962 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
963 *(cmd++) = 0;
964 *(cmd++) = D_TS_NEXT(nextpipe);
965 }
966 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
967
968 dbri_cmdsend(dbri, cmd, 4);
969 }
970 #endif
971
972 /* xmit_fixed() / recv_fixed()
973 *
974 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
975 * expected to change much, and which we don't need to buffer.
976 * The DBRI only interrupts us when the data changes (receive pipes),
977 * or only changes the data when this function is called (transmit pipes).
978 * Only short pipes (numbers 16-31) can be used in fixed data mode.
979 *
980 * These function operate on a 32-bit field, no matter how large
981 * the actual time slot is. The interrupt handler takes care of bit
982 * ordering and alignment. An 8-bit time slot will always end up
983 * in the low-order 8 bits, filled either MSB-first or LSB-first,
984 * depending on the settings passed to setup_pipe().
985 *
986 * Lock must not be held before calling it.
987 */
988 static void xmit_fixed(struct snd_dbri * dbri, int pipe, unsigned int data)
989 {
990 s32 *cmd;
991 unsigned long flags;
992
993 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
994 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
995 return;
996 }
997
998 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
999 printk(KERN_ERR "DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe);
1000 return;
1001 }
1002
1003 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1004 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1005 return;
1006 }
1007
1008 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1009 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", pipe);
1010 return;
1011 }
1012
1013 /* DBRI short pipes always transmit LSB first */
1014
1015 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1016 data = reverse_bytes(data, dbri->pipes[pipe].length);
1017
1018 cmd = dbri_cmdlock(dbri, 3);
1019
1020 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1021 *(cmd++) = data;
1022 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1023
1024 spin_lock_irqsave(&dbri->lock, flags);
1025 dbri_cmdsend(dbri, cmd, 3);
1026 spin_unlock_irqrestore(&dbri->lock, flags);
1027 dbri_cmdwait(dbri);
1028
1029 }
1030
1031 static void recv_fixed(struct snd_dbri * dbri, int pipe, volatile __u32 * ptr)
1032 {
1033 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1034 printk(KERN_ERR "DBRI: recv_fixed called with illegal pipe number\n");
1035 return;
1036 }
1037
1038 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1039 printk(KERN_ERR "DBRI: recv_fixed called on non-fixed pipe %d\n", pipe);
1040 return;
1041 }
1042
1043 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1044 printk(KERN_ERR "DBRI: recv_fixed called on transmit pipe %d\n", pipe);
1045 return;
1046 }
1047
1048 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1049 }
1050
1051 /* setup_descs()
1052 *
1053 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1054 * with a DMA buffer.
1055 *
1056 * Only pipe numbers 0-15 can be used in this mode.
1057 *
1058 * This function takes a stream number pointing to a data buffer,
1059 * and work by building chains of descriptors which identify the
1060 * data buffers. Buffers too large for a single descriptor will
1061 * be spread across multiple descriptors.
1062 *
1063 * All descriptors create a ring buffer.
1064 *
1065 * Lock must be held before calling this.
1066 */
1067 static int setup_descs(struct snd_dbri * dbri, int streamno, unsigned int period)
1068 {
1069 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1070 __u32 dvma_buffer;
1071 int desc;
1072 int len;
1073 int first_desc = -1;
1074 int last_desc = -1;
1075
1076 if (info->pipe < 0 || info->pipe > 15) {
1077 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1078 return -2;
1079 }
1080
1081 if (dbri->pipes[info->pipe].sdp == 0) {
1082 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1083 info->pipe);
1084 return -2;
1085 }
1086
1087 dvma_buffer = info->dvma_buffer;
1088 len = info->size;
1089
1090 if (streamno == DBRI_PLAY) {
1091 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1092 printk(KERN_ERR "DBRI: setup_descs: Called on receive pipe %d\n",
1093 info->pipe);
1094 return -2;
1095 }
1096 } else {
1097 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1098 printk(KERN_ERR
1099 "DBRI: setup_descs: Called on transmit pipe %d\n",
1100 info->pipe);
1101 return -2;
1102 }
1103 /* Should be able to queue multiple buffers to receive on a pipe */
1104 if (pipe_active(dbri, info->pipe)) {
1105 printk(KERN_ERR "DBRI: recv_on_pipe: Called on active pipe %d\n",
1106 info->pipe);
1107 return -2;
1108 }
1109
1110 /* Make sure buffer size is multiple of four */
1111 len &= ~3;
1112 }
1113
1114 /* Free descriptors if pipe has any */
1115 desc = dbri->pipes[info->pipe].first_desc;
1116 if ( desc >= 0)
1117 do {
1118 dbri->dma->desc[desc].nda = dbri->dma->desc[desc].ba = 0;
1119 desc = dbri->next_desc[desc];
1120 } while (desc != -1 && desc != dbri->pipes[info->pipe].first_desc);
1121
1122 dbri->pipes[info->pipe].desc = -1;
1123 dbri->pipes[info->pipe].first_desc = -1;
1124
1125 desc = 0;
1126 while (len > 0) {
1127 int mylen;
1128
1129 for (; desc < DBRI_NO_DESCS; desc++) {
1130 if (!dbri->dma->desc[desc].ba)
1131 break;
1132 }
1133 if (desc == DBRI_NO_DESCS) {
1134 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1135 return -1;
1136 }
1137
1138 if (len > DBRI_TD_MAXCNT)
1139 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1140 else
1141 mylen = len;
1142
1143 if (mylen > period)
1144 mylen = period;
1145
1146 dbri->next_desc[desc] = -1;
1147 dbri->dma->desc[desc].ba = dvma_buffer;
1148 dbri->dma->desc[desc].nda = 0;
1149
1150 if (streamno == DBRI_PLAY) {
1151 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1152 dbri->dma->desc[desc].word4 = 0;
1153 dbri->dma->desc[desc].word1 |=
1154 DBRI_TD_F | DBRI_TD_B;
1155 } else {
1156 dbri->dma->desc[desc].word1 = 0;
1157 dbri->dma->desc[desc].word4 =
1158 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1159 }
1160
1161 if (first_desc == -1)
1162 first_desc = desc;
1163 else {
1164 dbri->next_desc[last_desc] = desc;
1165 dbri->dma->desc[last_desc].nda =
1166 dbri->dma_dvma + dbri_dma_off(desc, desc);
1167 }
1168
1169 last_desc = desc;
1170 dvma_buffer += mylen;
1171 len -= mylen;
1172 }
1173
1174 if (first_desc == -1 || last_desc == -1) {
1175 printk(KERN_ERR "DBRI: setup_descs: Not enough descriptors available\n");
1176 return -1;
1177 }
1178
1179 dbri->dma->desc[last_desc].nda =
1180 dbri->dma_dvma + dbri_dma_off(desc, first_desc);
1181 dbri->next_desc[last_desc] = first_desc;
1182 dbri->pipes[info->pipe].first_desc = first_desc;
1183 dbri->pipes[info->pipe].desc = first_desc;
1184
1185 #ifdef DBRI_DEBUG
1186 for (desc = first_desc; desc != -1; ) {
1187 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1188 desc,
1189 dbri->dma->desc[desc].word1,
1190 dbri->dma->desc[desc].ba,
1191 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1192 desc = dbri->next_desc[desc];
1193 if ( desc == first_desc )
1194 break;
1195 }
1196 #endif
1197 return 0;
1198 }
1199
1200 /*
1201 ****************************************************************************
1202 ************************** DBRI - CHI interface ****************************
1203 ****************************************************************************
1204
1205 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1206 multiplexed serial interface which the DBRI can operate in either master
1207 (give clock/frame sync) or slave (take clock/frame sync) mode.
1208
1209 */
1210
1211 enum master_or_slave { CHImaster, CHIslave };
1212
1213 /*
1214 * Lock must not be held before calling it.
1215 */
1216 static void reset_chi(struct snd_dbri * dbri, enum master_or_slave master_or_slave,
1217 int bits_per_frame)
1218 {
1219 s32 *cmd;
1220 int val;
1221
1222 /* Set CHI Anchor: Pipe 16 */
1223
1224 cmd = dbri_cmdlock(dbri, 4);
1225 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1226 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1227 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1228 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1229 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1230 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1231 dbri_cmdsend(dbri, cmd, 4);
1232
1233 dbri->pipes[16].sdp = 1;
1234 dbri->pipes[16].nextpipe = 16;
1235
1236 cmd = dbri_cmdlock(dbri, 4);
1237
1238 if (master_or_slave == CHIslave) {
1239 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1240 *
1241 * CHICM = 0 (slave mode, 8 kHz frame rate)
1242 * IR = give immediate CHI status interrupt
1243 * EN = give CHI status interrupt upon change
1244 */
1245 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1246 } else {
1247 /* Setup DBRI for CHI Master - generate clock, FS
1248 *
1249 * BPF = bits per 8 kHz frame
1250 * 12.288 MHz / CHICM_divisor = clock rate
1251 * FD = 1 - drive CHIFS on rising edge of CHICK
1252 */
1253 int clockrate = bits_per_frame * 8;
1254 int divisor = 12288 / clockrate;
1255
1256 if (divisor > 255 || divisor * clockrate != 12288)
1257 printk(KERN_ERR "DBRI: illegal bits_per_frame in setup_chi\n");
1258
1259 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1260 | D_CHI_BPF(bits_per_frame));
1261 }
1262
1263 dbri->chi_bpf = bits_per_frame;
1264
1265 /* CHI Data Mode
1266 *
1267 * RCE = 0 - receive on falling edge of CHICK
1268 * XCE = 1 - transmit on rising edge of CHICK
1269 * XEN = 1 - enable transmitter
1270 * REN = 1 - enable receiver
1271 */
1272
1273 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1274 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1275 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1276
1277 dbri_cmdsend(dbri, cmd, 4);
1278 }
1279
1280 /*
1281 ****************************************************************************
1282 *********************** CS4215 audio codec management **********************
1283 ****************************************************************************
1284
1285 In the standard SPARC audio configuration, the CS4215 codec is attached
1286 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1287
1288 * Lock must not be held before calling it.
1289
1290 */
1291 static void cs4215_setup_pipes(struct snd_dbri * dbri)
1292 {
1293 unsigned long flags;
1294
1295 spin_lock_irqsave(&dbri->lock, flags);
1296 /*
1297 * Data mode:
1298 * Pipe 4: Send timeslots 1-4 (audio data)
1299 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1300 * Pipe 6: Receive timeslots 1-4 (audio data)
1301 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1302 * interrupt, and the rest of the data (slot 5 and 8) is
1303 * not relevant for us (only for doublechecking).
1304 *
1305 * Control mode:
1306 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1307 * Pipe 18: Receive timeslot 1 (clb).
1308 * Pipe 19: Receive timeslot 7 (version).
1309 */
1310
1311 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1312 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1313 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1314 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1315
1316 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1317 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1318 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1319 spin_unlock_irqrestore(&dbri->lock, flags);
1320
1321 dbri_cmdwait(dbri);
1322 }
1323
1324 static int cs4215_init_data(struct cs4215 *mm)
1325 {
1326 /*
1327 * No action, memory resetting only.
1328 *
1329 * Data Time Slot 5-8
1330 * Speaker,Line and Headphone enable. Gain set to the half.
1331 * Input is mike.
1332 */
1333 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1334 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1335 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1336 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1337
1338 /*
1339 * Control Time Slot 1-4
1340 * 0: Default I/O voltage scale
1341 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1342 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1343 * 3: Tests disabled
1344 */
1345 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1346 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1347 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1348 mm->ctrl[3] = 0;
1349
1350 mm->status = 0;
1351 mm->version = 0xff;
1352 mm->precision = 8; /* For ULAW */
1353 mm->channels = 1;
1354
1355 return 0;
1356 }
1357
1358 static void cs4215_setdata(struct snd_dbri * dbri, int muted)
1359 {
1360 if (muted) {
1361 dbri->mm.data[0] |= 63;
1362 dbri->mm.data[1] |= 63;
1363 dbri->mm.data[2] &= ~15;
1364 dbri->mm.data[3] &= ~15;
1365 } else {
1366 /* Start by setting the playback attenuation. */
1367 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1368 int left_gain = info->left_gain & 0x3f;
1369 int right_gain = info->right_gain & 0x3f;
1370
1371 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1372 dbri->mm.data[1] &= ~0x3f;
1373 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1374 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1375
1376 /* Now set the recording gain. */
1377 info = &dbri->stream_info[DBRI_REC];
1378 left_gain = info->left_gain & 0xf;
1379 right_gain = info->right_gain & 0xf;
1380 dbri->mm.data[2] |= CS4215_LG(left_gain);
1381 dbri->mm.data[3] |= CS4215_RG(right_gain);
1382 }
1383
1384 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1385 }
1386
1387 /*
1388 * Set the CS4215 to data mode.
1389 */
1390 static void cs4215_open(struct snd_dbri * dbri)
1391 {
1392 int data_width;
1393 u32 tmp;
1394 unsigned long flags;
1395
1396 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1397 dbri->mm.channels, dbri->mm.precision);
1398
1399 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1400 * to make sure this takes. This avoids clicking noises.
1401 */
1402
1403 cs4215_setdata(dbri, 1);
1404 udelay(125);
1405
1406 /*
1407 * Data mode:
1408 * Pipe 4: Send timeslots 1-4 (audio data)
1409 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1410 * Pipe 6: Receive timeslots 1-4 (audio data)
1411 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1412 * interrupt, and the rest of the data (slot 5 and 8) is
1413 * not relevant for us (only for doublechecking).
1414 *
1415 * Just like in control mode, the time slots are all offset by eight
1416 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1417 * even if it's the CHI master. Don't ask me...
1418 */
1419 spin_lock_irqsave(&dbri->lock, flags);
1420 tmp = sbus_readl(dbri->regs + REG0);
1421 tmp &= ~(D_C); /* Disable CHI */
1422 sbus_writel(tmp, dbri->regs + REG0);
1423
1424 /* Switch CS4215 to data mode - set PIO3 to 1 */
1425 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1426 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1427
1428 reset_chi(dbri, CHIslave, 128);
1429
1430 /* Note: this next doesn't work for 8-bit stereo, because the two
1431 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1432 * (See CS4215 datasheet Fig 15)
1433 *
1434 * DBRI non-contiguous mode would be required to make this work.
1435 */
1436 data_width = dbri->mm.channels * dbri->mm.precision;
1437
1438 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1439 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1440 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1441 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1442
1443 /* FIXME: enable CHI after _setdata? */
1444 tmp = sbus_readl(dbri->regs + REG0);
1445 tmp |= D_C; /* Enable CHI */
1446 sbus_writel(tmp, dbri->regs + REG0);
1447 spin_unlock_irqrestore(&dbri->lock, flags);
1448
1449 cs4215_setdata(dbri, 0);
1450 }
1451
1452 /*
1453 * Send the control information (i.e. audio format)
1454 */
1455 static int cs4215_setctrl(struct snd_dbri * dbri)
1456 {
1457 int i, val;
1458 u32 tmp;
1459 unsigned long flags;
1460
1461 /* FIXME - let the CPU do something useful during these delays */
1462
1463 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1464 * to make sure this takes. This avoids clicking noises.
1465 */
1466 cs4215_setdata(dbri, 1);
1467 udelay(125);
1468
1469 /*
1470 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1471 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1472 */
1473 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1474 sbus_writel(val, dbri->regs + REG2);
1475 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1476 udelay(34);
1477
1478 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1479 * operate as CHI master, supplying clocking and frame synchronization.
1480 *
1481 * In Data mode, however, the CS4215 must be CHI master to insure
1482 * that its data stream is synchronous with its codec.
1483 *
1484 * The upshot of all this? We start by putting the DBRI into master
1485 * mode, program the CS4215 in Control mode, then switch the CS4215
1486 * into Data mode and put the DBRI into slave mode. Various timing
1487 * requirements must be observed along the way.
1488 *
1489 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1490 * others?), the addressing of the CS4215's time slots is
1491 * offset by eight bits, so we add eight to all the "cycle"
1492 * values in the Define Time Slot (DTS) commands. This is
1493 * done in hardware by a TI 248 that delays the DBRI->4215
1494 * frame sync signal by eight clock cycles. Anybody know why?
1495 */
1496 spin_lock_irqsave(&dbri->lock, flags);
1497 tmp = sbus_readl(dbri->regs + REG0);
1498 tmp &= ~D_C; /* Disable CHI */
1499 sbus_writel(tmp, dbri->regs + REG0);
1500
1501 reset_chi(dbri, CHImaster, 128);
1502
1503 /*
1504 * Control mode:
1505 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1506 * Pipe 18: Receive timeslot 1 (clb).
1507 * Pipe 19: Receive timeslot 7 (version).
1508 */
1509
1510 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1511 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1512 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1513 spin_unlock_irqrestore(&dbri->lock, flags);
1514
1515 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1516 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1517 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1518
1519 spin_lock_irqsave(&dbri->lock, flags);
1520 tmp = sbus_readl(dbri->regs + REG0);
1521 tmp |= D_C; /* Enable CHI */
1522 sbus_writel(tmp, dbri->regs + REG0);
1523 spin_unlock_irqrestore(&dbri->lock, flags);
1524
1525 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) {
1526 msleep_interruptible(1);
1527 }
1528 if (i == 0) {
1529 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1530 dbri->mm.status);
1531 return -1;
1532 }
1533
1534 /* Disable changes to our copy of the version number, as we are about
1535 * to leave control mode.
1536 */
1537 recv_fixed(dbri, 19, NULL);
1538
1539 /* Terminate CS4215 control mode - data sheet says
1540 * "Set CLB=1 and send two more frames of valid control info"
1541 */
1542 dbri->mm.ctrl[0] |= CS4215_CLB;
1543 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1544
1545 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1546 udelay(250);
1547
1548 cs4215_setdata(dbri, 0);
1549
1550 return 0;
1551 }
1552
1553 /*
1554 * Setup the codec with the sampling rate, audio format and number of
1555 * channels.
1556 * As part of the process we resend the settings for the data
1557 * timeslots as well.
1558 */
1559 static int cs4215_prepare(struct snd_dbri * dbri, unsigned int rate,
1560 snd_pcm_format_t format, unsigned int channels)
1561 {
1562 int freq_idx;
1563 int ret = 0;
1564
1565 /* Lookup index for this rate */
1566 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1567 if (CS4215_FREQ[freq_idx].freq == rate)
1568 break;
1569 }
1570 if (CS4215_FREQ[freq_idx].freq != rate) {
1571 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1572 return -1;
1573 }
1574
1575 switch (format) {
1576 case SNDRV_PCM_FORMAT_MU_LAW:
1577 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1578 dbri->mm.precision = 8;
1579 break;
1580 case SNDRV_PCM_FORMAT_A_LAW:
1581 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1582 dbri->mm.precision = 8;
1583 break;
1584 case SNDRV_PCM_FORMAT_U8:
1585 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1586 dbri->mm.precision = 8;
1587 break;
1588 case SNDRV_PCM_FORMAT_S16_BE:
1589 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1590 dbri->mm.precision = 16;
1591 break;
1592 default:
1593 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1594 return -1;
1595 }
1596
1597 /* Add rate parameters */
1598 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1599 dbri->mm.ctrl[2] = CS4215_XCLK |
1600 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1601
1602 dbri->mm.channels = channels;
1603 if (channels == 2)
1604 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1605
1606 ret = cs4215_setctrl(dbri);
1607 if (ret == 0)
1608 cs4215_open(dbri); /* set codec to data mode */
1609
1610 return ret;
1611 }
1612
1613 /*
1614 *
1615 */
1616 static int cs4215_init(struct snd_dbri * dbri)
1617 {
1618 u32 reg2 = sbus_readl(dbri->regs + REG2);
1619 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1620
1621 /* Look for the cs4215 chips */
1622 if (reg2 & D_PIO2) {
1623 dprintk(D_MM, "Onboard CS4215 detected\n");
1624 dbri->mm.onboard = 1;
1625 }
1626 if (reg2 & D_PIO0) {
1627 dprintk(D_MM, "Speakerbox detected\n");
1628 dbri->mm.onboard = 0;
1629
1630 if (reg2 & D_PIO2) {
1631 printk(KERN_INFO "DBRI: Using speakerbox / "
1632 "ignoring onboard mmcodec.\n");
1633 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1634 }
1635 }
1636
1637 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1638 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1639 return -EIO;
1640 }
1641
1642 cs4215_setup_pipes(dbri);
1643 cs4215_init_data(&dbri->mm);
1644
1645 /* Enable capture of the status & version timeslots. */
1646 recv_fixed(dbri, 18, &dbri->mm.status);
1647 recv_fixed(dbri, 19, &dbri->mm.version);
1648
1649 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1650 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1651 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1652 dbri->mm.offset);
1653 return -EIO;
1654 }
1655 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1656
1657 return 0;
1658 }
1659
1660 /*
1661 ****************************************************************************
1662 *************************** DBRI interrupt handler *************************
1663 ****************************************************************************
1664
1665 The DBRI communicates with the CPU mainly via a circular interrupt
1666 buffer. When an interrupt is signaled, the CPU walks through the
1667 buffer and calls dbri_process_one_interrupt() for each interrupt word.
1668 Complicated interrupts are handled by dedicated functions (which
1669 appear first in this file). Any pending interrupts can be serviced by
1670 calling dbri_process_interrupt_buffer(), which works even if the CPU's
1671 interrupts are disabled.
1672
1673 */
1674
1675 /* xmit_descs()
1676 *
1677 * Starts transmiting the current TD's for recording/playing.
1678 * For playback, ALSA has filled the DMA memory with new data (we hope).
1679 */
1680 static void xmit_descs(struct snd_dbri *dbri)
1681 {
1682 struct dbri_streaminfo *info;
1683 s32 *cmd;
1684 unsigned long flags;
1685 int first_td;
1686
1687 if (dbri == NULL)
1688 return; /* Disabled */
1689
1690 info = &dbri->stream_info[DBRI_REC];
1691 spin_lock_irqsave(&dbri->lock, flags);
1692
1693 if (info->pipe >= 0) {
1694 first_td = dbri->pipes[info->pipe].first_desc;
1695
1696 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1697
1698 /* Stream could be closed by the time we run. */
1699 if (first_td >= 0) {
1700 cmd = dbri_cmdlock(dbri, 2);
1701 *(cmd++) = DBRI_CMD(D_SDP, 0,
1702 dbri->pipes[info->pipe].sdp
1703 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1704 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1705 dbri_cmdsend(dbri, cmd, 2);
1706
1707 /* Reset our admin of the pipe. */
1708 dbri->pipes[info->pipe].desc = first_td;
1709 }
1710 }
1711
1712 info = &dbri->stream_info[DBRI_PLAY];
1713
1714 if (info->pipe >= 0) {
1715 first_td = dbri->pipes[info->pipe].first_desc;
1716
1717 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1718
1719 /* Stream could be closed by the time we run. */
1720 if (first_td >= 0) {
1721 cmd = dbri_cmdlock(dbri, 2);
1722 *(cmd++) = DBRI_CMD(D_SDP, 0,
1723 dbri->pipes[info->pipe].sdp
1724 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1725 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1726 dbri_cmdsend(dbri, cmd, 2);
1727
1728 /* Reset our admin of the pipe. */
1729 dbri->pipes[info->pipe].desc = first_td;
1730 }
1731 }
1732
1733 spin_unlock_irqrestore(&dbri->lock, flags);
1734 }
1735
1736 /* transmission_complete_intr()
1737 *
1738 * Called by main interrupt handler when DBRI signals transmission complete
1739 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1740 *
1741 * Walks through the pipe's list of transmit buffer descriptors and marks
1742 * them as available. Stops when the first descriptor is found without
1743 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1744 *
1745 * The DMA buffers are not released. They form a ring buffer and
1746 * they are filled by ALSA while others are transmitted by DMA.
1747 *
1748 */
1749
1750 static void transmission_complete_intr(struct snd_dbri * dbri, int pipe)
1751 {
1752 struct dbri_streaminfo *info;
1753 int td;
1754 int status;
1755
1756 info = &dbri->stream_info[DBRI_PLAY];
1757
1758 td = dbri->pipes[pipe].desc;
1759 while (td >= 0) {
1760 if (td >= DBRI_NO_DESCS) {
1761 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1762 return;
1763 }
1764
1765 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1766 if (!(status & DBRI_TD_TBC)) {
1767 break;
1768 }
1769
1770 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1771
1772 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1773 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1774
1775 td = dbri->next_desc[td];
1776 dbri->pipes[pipe].desc = td;
1777 }
1778
1779 /* Notify ALSA */
1780 if (spin_is_locked(&dbri->lock)) {
1781 spin_unlock(&dbri->lock);
1782 snd_pcm_period_elapsed(info->substream);
1783 spin_lock(&dbri->lock);
1784 } else
1785 snd_pcm_period_elapsed(info->substream);
1786 }
1787
1788 static void reception_complete_intr(struct snd_dbri * dbri, int pipe)
1789 {
1790 struct dbri_streaminfo *info;
1791 int rd = dbri->pipes[pipe].desc;
1792 s32 status;
1793
1794 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1795 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1796 return;
1797 }
1798
1799 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1800 status = dbri->dma->desc[rd].word1;
1801 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1802
1803 info = &dbri->stream_info[DBRI_REC];
1804 info->offset += DBRI_RD_CNT(status);
1805
1806 /* FIXME: Check status */
1807
1808 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1809 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1810
1811 /* Notify ALSA */
1812 if (spin_is_locked(&dbri->lock)) {
1813 spin_unlock(&dbri->lock);
1814 snd_pcm_period_elapsed(info->substream);
1815 spin_lock(&dbri->lock);
1816 } else
1817 snd_pcm_period_elapsed(info->substream);
1818 }
1819
1820 static void dbri_process_one_interrupt(struct snd_dbri * dbri, int x)
1821 {
1822 int val = D_INTR_GETVAL(x);
1823 int channel = D_INTR_GETCHAN(x);
1824 int command = D_INTR_GETCMD(x);
1825 int code = D_INTR_GETCODE(x);
1826 #ifdef DBRI_DEBUG
1827 int rval = D_INTR_GETRVAL(x);
1828 #endif
1829
1830 if (channel == D_INTR_CMD) {
1831 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1832 cmds[command], val);
1833 } else {
1834 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1835 channel, code, rval);
1836 }
1837
1838 switch (code) {
1839 case D_INTR_CMDI:
1840 if (command != D_WAIT)
1841 printk(KERN_ERR "DBRI: Command read interrupt\n");
1842 break;
1843 case D_INTR_BRDY:
1844 reception_complete_intr(dbri, channel);
1845 break;
1846 case D_INTR_XCMP:
1847 case D_INTR_MINT:
1848 transmission_complete_intr(dbri, channel);
1849 break;
1850 case D_INTR_UNDR:
1851 /* UNDR - Transmission underrun
1852 * resend SDP command with clear pipe bit (C) set
1853 */
1854 {
1855 /* FIXME: do something useful in case of underrun */
1856 printk(KERN_ERR "DBRI: Underrun error\n");
1857 #if 0
1858 s32 *cmd;
1859 int pipe = channel;
1860 int td = dbri->pipes[pipe].desc;
1861
1862 dbri->dma->desc[td].word4 = 0;
1863 cmd = dbri_cmdlock(dbri, NoGetLock);
1864 *(cmd++) = DBRI_CMD(D_SDP, 0,
1865 dbri->pipes[pipe].sdp
1866 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1867 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1868 dbri_cmdsend(dbri, cmd);
1869 #endif
1870 }
1871 break;
1872 case D_INTR_FXDT:
1873 /* FXDT - Fixed data change */
1874 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1875 val = reverse_bytes(val, dbri->pipes[channel].length);
1876
1877 if (dbri->pipes[channel].recv_fixed_ptr)
1878 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1879 break;
1880 default:
1881 if (channel != D_INTR_CMD)
1882 printk(KERN_WARNING
1883 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1884 }
1885 }
1886
1887 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1888 * buffer until it finds a zero word (indicating nothing more to do
1889 * right now). Non-zero words require processing and are handed off
1890 * to dbri_process_one_interrupt AFTER advancing the pointer.
1891 */
1892 static void dbri_process_interrupt_buffer(struct snd_dbri * dbri)
1893 {
1894 s32 x;
1895
1896 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1897 dbri->dma->intr[dbri->dbri_irqp] = 0;
1898 dbri->dbri_irqp++;
1899 if (dbri->dbri_irqp == DBRI_INT_BLK)
1900 dbri->dbri_irqp = 1;
1901
1902 dbri_process_one_interrupt(dbri, x);
1903 }
1904 }
1905
1906 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
1907 {
1908 struct snd_dbri *dbri = dev_id;
1909 static int errcnt = 0;
1910 int x;
1911
1912 if (dbri == NULL)
1913 return IRQ_NONE;
1914 spin_lock(&dbri->lock);
1915
1916 /*
1917 * Read it, so the interrupt goes away.
1918 */
1919 x = sbus_readl(dbri->regs + REG1);
1920
1921 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1922 u32 tmp;
1923
1924 if (x & D_MRR)
1925 printk(KERN_ERR
1926 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1927 x);
1928 if (x & D_MLE)
1929 printk(KERN_ERR
1930 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1931 x);
1932 if (x & D_LBG)
1933 printk(KERN_ERR
1934 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1935 if (x & D_MBE)
1936 printk(KERN_ERR
1937 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1938
1939 /* Some of these SBus errors cause the chip's SBus circuitry
1940 * to be disabled, so just re-enable and try to keep going.
1941 *
1942 * The only one I've seen is MRR, which will be triggered
1943 * if you let a transmit pipe underrun, then try to CDP it.
1944 *
1945 * If these things persist, we reset the chip.
1946 */
1947 if ((++errcnt) % 10 == 0) {
1948 dprintk(D_INT, "Interrupt errors exceeded.\n");
1949 dbri_reset(dbri);
1950 } else {
1951 tmp = sbus_readl(dbri->regs + REG0);
1952 tmp &= ~(D_D);
1953 sbus_writel(tmp, dbri->regs + REG0);
1954 }
1955 }
1956
1957 dbri_process_interrupt_buffer(dbri);
1958
1959 spin_unlock(&dbri->lock);
1960
1961 return IRQ_HANDLED;
1962 }
1963
1964 /****************************************************************************
1965 PCM Interface
1966 ****************************************************************************/
1967 static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1968 .info = (SNDRV_PCM_INFO_MMAP |
1969 SNDRV_PCM_INFO_INTERLEAVED |
1970 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1971 SNDRV_PCM_INFO_MMAP_VALID),
1972 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1973 SNDRV_PCM_FMTBIT_A_LAW |
1974 SNDRV_PCM_FMTBIT_U8 |
1975 SNDRV_PCM_FMTBIT_S16_BE,
1976 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
1977 .rate_min = 5512,
1978 .rate_max = 48000,
1979 .channels_min = 1,
1980 .channels_max = 2,
1981 .buffer_bytes_max = (64 * 1024),
1982 .period_bytes_min = 1,
1983 .period_bytes_max = DBRI_TD_MAXCNT,
1984 .periods_min = 1,
1985 .periods_max = 1024,
1986 };
1987
1988 static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
1989 struct snd_pcm_hw_rule *rule)
1990 {
1991 struct snd_interval *c = hw_param_interval(params,
1992 SNDRV_PCM_HW_PARAM_CHANNELS);
1993 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1994 struct snd_mask fmt;
1995
1996 snd_mask_any(&fmt);
1997 if (c->min > 1) {
1998 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
1999 return snd_mask_refine(f, &fmt);
2000 }
2001 return 0;
2002 }
2003
2004 static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2005 struct snd_pcm_hw_rule *rule)
2006 {
2007 struct snd_interval *c = hw_param_interval(params,
2008 SNDRV_PCM_HW_PARAM_CHANNELS);
2009 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2010 struct snd_interval ch;
2011
2012 snd_interval_any(&ch);
2013 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
2014 ch.min = ch.max = 1;
2015 ch.integer = 1;
2016 return snd_interval_refine(c, &ch);
2017 }
2018 return 0;
2019 }
2020
2021 static int snd_dbri_open(struct snd_pcm_substream *substream)
2022 {
2023 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2024 struct snd_pcm_runtime *runtime = substream->runtime;
2025 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2026 unsigned long flags;
2027
2028 dprintk(D_USR, "open audio output.\n");
2029 runtime->hw = snd_dbri_pcm_hw;
2030
2031 spin_lock_irqsave(&dbri->lock, flags);
2032 info->substream = substream;
2033 info->offset = 0;
2034 info->dvma_buffer = 0;
2035 info->pipe = -1;
2036 spin_unlock_irqrestore(&dbri->lock, flags);
2037
2038 snd_pcm_hw_rule_add(runtime,0,SNDRV_PCM_HW_PARAM_CHANNELS,
2039 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
2040 -1);
2041 snd_pcm_hw_rule_add(runtime,0,SNDRV_PCM_HW_PARAM_FORMAT,
2042 snd_hw_rule_channels, NULL,
2043 SNDRV_PCM_HW_PARAM_CHANNELS,
2044 -1);
2045
2046 cs4215_open(dbri);
2047
2048 return 0;
2049 }
2050
2051 static int snd_dbri_close(struct snd_pcm_substream *substream)
2052 {
2053 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2054 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2055
2056 dprintk(D_USR, "close audio output.\n");
2057 info->substream = NULL;
2058 info->offset = 0;
2059
2060 return 0;
2061 }
2062
2063 static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2064 struct snd_pcm_hw_params *hw_params)
2065 {
2066 struct snd_pcm_runtime *runtime = substream->runtime;
2067 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2068 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2069 int direction;
2070 int ret;
2071
2072 /* set sampling rate, audio format and number of channels */
2073 ret = cs4215_prepare(dbri, params_rate(hw_params),
2074 params_format(hw_params),
2075 params_channels(hw_params));
2076 if (ret != 0)
2077 return ret;
2078
2079 if ((ret = snd_pcm_lib_malloc_pages(substream,
2080 params_buffer_bytes(hw_params))) < 0) {
2081 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2082 return ret;
2083 }
2084
2085 /* hw_params can get called multiple times. Only map the DMA once.
2086 */
2087 if (info->dvma_buffer == 0) {
2088 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2089 direction = SBUS_DMA_TODEVICE;
2090 else
2091 direction = SBUS_DMA_FROMDEVICE;
2092
2093 info->dvma_buffer = sbus_map_single(dbri->sdev,
2094 runtime->dma_area,
2095 params_buffer_bytes(hw_params),
2096 direction);
2097 }
2098
2099 direction = params_buffer_bytes(hw_params);
2100 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2101 direction, info->dvma_buffer);
2102 return 0;
2103 }
2104
2105 static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2106 {
2107 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2108 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2109 int direction;
2110
2111 dprintk(D_USR, "hw_free.\n");
2112
2113 /* hw_free can get called multiple times. Only unmap the DMA once.
2114 */
2115 if (info->dvma_buffer) {
2116 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2117 direction = SBUS_DMA_TODEVICE;
2118 else
2119 direction = SBUS_DMA_FROMDEVICE;
2120
2121 sbus_unmap_single(dbri->sdev, info->dvma_buffer,
2122 substream->runtime->buffer_size, direction);
2123 info->dvma_buffer = 0;
2124 }
2125 if (info->pipe != -1) {
2126 reset_pipe(dbri, info->pipe);
2127 info->pipe = -1;
2128 }
2129
2130 return snd_pcm_lib_free_pages(substream);
2131 }
2132
2133 static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2134 {
2135 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2136 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2137 int ret;
2138
2139 info->size = snd_pcm_lib_buffer_bytes(substream);
2140 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2141 info->pipe = 4; /* Send pipe */
2142 else
2143 info->pipe = 6; /* Receive pipe */
2144
2145 spin_lock_irq(&dbri->lock);
2146 info->offset = 0;
2147
2148 /* Setup the all the transmit/receive desciptors to cover the
2149 * whole DMA buffer.
2150 */
2151 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2152 snd_pcm_lib_period_bytes(substream));
2153
2154 spin_unlock_irq(&dbri->lock);
2155
2156 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2157 return ret;
2158 }
2159
2160 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2161 {
2162 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2163 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2164 int ret = 0;
2165
2166 switch (cmd) {
2167 case SNDRV_PCM_TRIGGER_START:
2168 dprintk(D_USR, "start audio, period is %d bytes\n",
2169 (int)snd_pcm_lib_period_bytes(substream));
2170 /* Re-submit the TDs. */
2171 xmit_descs(dbri);
2172 break;
2173 case SNDRV_PCM_TRIGGER_STOP:
2174 dprintk(D_USR, "stop audio.\n");
2175 reset_pipe(dbri, info->pipe);
2176 break;
2177 default:
2178 ret = -EINVAL;
2179 }
2180
2181 return ret;
2182 }
2183
2184 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2185 {
2186 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2187 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2188 snd_pcm_uframes_t ret;
2189
2190 ret = bytes_to_frames(substream->runtime, info->offset)
2191 % substream->runtime->buffer_size;
2192 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2193 ret, substream->runtime->buffer_size);
2194 return ret;
2195 }
2196
2197 static struct snd_pcm_ops snd_dbri_ops = {
2198 .open = snd_dbri_open,
2199 .close = snd_dbri_close,
2200 .ioctl = snd_pcm_lib_ioctl,
2201 .hw_params = snd_dbri_hw_params,
2202 .hw_free = snd_dbri_hw_free,
2203 .prepare = snd_dbri_prepare,
2204 .trigger = snd_dbri_trigger,
2205 .pointer = snd_dbri_pointer,
2206 };
2207
2208 static int __devinit snd_dbri_pcm(struct snd_dbri * dbri)
2209 {
2210 struct snd_pcm *pcm;
2211 int err;
2212
2213 if ((err = snd_pcm_new(dbri->card,
2214 /* ID */ "sun_dbri",
2215 /* device */ 0,
2216 /* playback count */ 1,
2217 /* capture count */ 1, &pcm)) < 0)
2218 return err;
2219 snd_assert(pcm != NULL, return -EINVAL);
2220
2221 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2222 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2223
2224 pcm->private_data = dbri;
2225 pcm->info_flags = 0;
2226 strcpy(pcm->name, dbri->card->shortname);
2227
2228 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2229 SNDRV_DMA_TYPE_CONTINUOUS,
2230 snd_dma_continuous_data(GFP_KERNEL),
2231 64 * 1024, 64 * 1024)) < 0) {
2232 return err;
2233 }
2234
2235 return 0;
2236 }
2237
2238 /*****************************************************************************
2239 Mixer interface
2240 *****************************************************************************/
2241
2242 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2243 struct snd_ctl_elem_info *uinfo)
2244 {
2245 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2246 uinfo->count = 2;
2247 uinfo->value.integer.min = 0;
2248 if (kcontrol->private_value == DBRI_PLAY) {
2249 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2250 } else {
2251 uinfo->value.integer.max = DBRI_MAX_GAIN;
2252 }
2253 return 0;
2254 }
2255
2256 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2257 struct snd_ctl_elem_value *ucontrol)
2258 {
2259 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2260 struct dbri_streaminfo *info;
2261 snd_assert(dbri != NULL, return -EINVAL);
2262 info = &dbri->stream_info[kcontrol->private_value];
2263 snd_assert(info != NULL, return -EINVAL);
2264
2265 ucontrol->value.integer.value[0] = info->left_gain;
2266 ucontrol->value.integer.value[1] = info->right_gain;
2267 return 0;
2268 }
2269
2270 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2271 struct snd_ctl_elem_value *ucontrol)
2272 {
2273 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2274 struct dbri_streaminfo *info = &dbri->stream_info[kcontrol->private_value];
2275 int changed = 0;
2276
2277 if (info->left_gain != ucontrol->value.integer.value[0]) {
2278 info->left_gain = ucontrol->value.integer.value[0];
2279 changed = 1;
2280 }
2281 if (info->right_gain != ucontrol->value.integer.value[1]) {
2282 info->right_gain = ucontrol->value.integer.value[1];
2283 changed = 1;
2284 }
2285 if (changed == 1) {
2286 /* First mute outputs, and wait 1/8000 sec (125 us)
2287 * to make sure this takes. This avoids clicking noises.
2288 */
2289 cs4215_setdata(dbri, 1);
2290 udelay(125);
2291 cs4215_setdata(dbri, 0);
2292 }
2293 return changed;
2294 }
2295
2296 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2297 struct snd_ctl_elem_info *uinfo)
2298 {
2299 int mask = (kcontrol->private_value >> 16) & 0xff;
2300
2301 uinfo->type = (mask == 1) ?
2302 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2303 uinfo->count = 1;
2304 uinfo->value.integer.min = 0;
2305 uinfo->value.integer.max = mask;
2306 return 0;
2307 }
2308
2309 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2310 struct snd_ctl_elem_value *ucontrol)
2311 {
2312 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2313 int elem = kcontrol->private_value & 0xff;
2314 int shift = (kcontrol->private_value >> 8) & 0xff;
2315 int mask = (kcontrol->private_value >> 16) & 0xff;
2316 int invert = (kcontrol->private_value >> 24) & 1;
2317 snd_assert(dbri != NULL, return -EINVAL);
2318
2319 if (elem < 4) {
2320 ucontrol->value.integer.value[0] =
2321 (dbri->mm.data[elem] >> shift) & mask;
2322 } else {
2323 ucontrol->value.integer.value[0] =
2324 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2325 }
2326
2327 if (invert == 1) {
2328 ucontrol->value.integer.value[0] =
2329 mask - ucontrol->value.integer.value[0];
2330 }
2331 return 0;
2332 }
2333
2334 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2335 struct snd_ctl_elem_value *ucontrol)
2336 {
2337 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2338 int elem = kcontrol->private_value & 0xff;
2339 int shift = (kcontrol->private_value >> 8) & 0xff;
2340 int mask = (kcontrol->private_value >> 16) & 0xff;
2341 int invert = (kcontrol->private_value >> 24) & 1;
2342 int changed = 0;
2343 unsigned short val;
2344 snd_assert(dbri != NULL, return -EINVAL);
2345
2346 val = (ucontrol->value.integer.value[0] & mask);
2347 if (invert == 1)
2348 val = mask - val;
2349 val <<= shift;
2350
2351 if (elem < 4) {
2352 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2353 ~(mask << shift)) | val;
2354 changed = (val != dbri->mm.data[elem]);
2355 } else {
2356 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2357 ~(mask << shift)) | val;
2358 changed = (val != dbri->mm.ctrl[elem - 4]);
2359 }
2360
2361 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2362 "mixer-value=%ld, mm-value=0x%x\n",
2363 mask, changed, ucontrol->value.integer.value[0],
2364 dbri->mm.data[elem & 3]);
2365
2366 if (changed) {
2367 /* First mute outputs, and wait 1/8000 sec (125 us)
2368 * to make sure this takes. This avoids clicking noises.
2369 */
2370 cs4215_setdata(dbri, 1);
2371 udelay(125);
2372 cs4215_setdata(dbri, 0);
2373 }
2374 return changed;
2375 }
2376
2377 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2378 timeslots. Shift is the bit offset in the timeslot, mask defines the
2379 number of bits. invert is a boolean for use with attenuation.
2380 */
2381 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2382 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2383 .info = snd_cs4215_info_single, \
2384 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2385 .private_value = entry | (shift << 8) | (mask << 16) | (invert << 24) },
2386
2387 static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
2388 {
2389 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2390 .name = "Playback Volume",
2391 .info = snd_cs4215_info_volume,
2392 .get = snd_cs4215_get_volume,
2393 .put = snd_cs4215_put_volume,
2394 .private_value = DBRI_PLAY,
2395 },
2396 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2397 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2398 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2399 {
2400 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2401 .name = "Capture Volume",
2402 .info = snd_cs4215_info_volume,
2403 .get = snd_cs4215_get_volume,
2404 .put = snd_cs4215_put_volume,
2405 .private_value = DBRI_REC,
2406 },
2407 /* FIXME: mic/line switch */
2408 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2409 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2410 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2411 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2412 };
2413
2414 static int __init snd_dbri_mixer(struct snd_dbri * dbri)
2415 {
2416 struct snd_card *card;
2417 int idx, err;
2418
2419 snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL);
2420
2421 card = dbri->card;
2422 strcpy(card->mixername, card->shortname);
2423
2424 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
2425 if ((err = snd_ctl_add(card,
2426 snd_ctl_new1(&dbri_controls[idx], dbri))) < 0)
2427 return err;
2428 }
2429
2430 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2431 dbri->stream_info[idx].left_gain = 0;
2432 dbri->stream_info[idx].right_gain = 0;
2433 }
2434
2435 return 0;
2436 }
2437
2438 /****************************************************************************
2439 /proc interface
2440 ****************************************************************************/
2441 static void dbri_regs_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
2442 {
2443 struct snd_dbri *dbri = entry->private_data;
2444
2445 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2446 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2447 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2448 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2449 }
2450
2451 #ifdef DBRI_DEBUG
2452 static void dbri_debug_read(struct snd_info_entry * entry,
2453 struct snd_info_buffer *buffer)
2454 {
2455 struct snd_dbri *dbri = entry->private_data;
2456 int pipe;
2457 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2458
2459 for (pipe = 0; pipe < 32; pipe++) {
2460 if (pipe_active(dbri, pipe)) {
2461 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2462 snd_iprintf(buffer,
2463 "Pipe %d: %s SDP=0x%x desc=%d, "
2464 "len=%d next %d\n",
2465 pipe,
2466 ((pptr->sdp & D_SDP_TO_SER) ? "output" : "input"),
2467 pptr->sdp, pptr->desc,
2468 pptr->length, pptr->nextpipe);
2469 }
2470 }
2471 }
2472 #endif
2473
2474 void snd_dbri_proc(struct snd_dbri * dbri)
2475 {
2476 struct snd_info_entry *entry;
2477
2478 if (! snd_card_proc_new(dbri->card, "regs", &entry))
2479 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2480
2481 #ifdef DBRI_DEBUG
2482 if (! snd_card_proc_new(dbri->card, "debug", &entry)) {
2483 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2484 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2485 }
2486 #endif
2487 }
2488
2489 /*
2490 ****************************************************************************
2491 **************************** Initialization ********************************
2492 ****************************************************************************
2493 */
2494 static void snd_dbri_free(struct snd_dbri * dbri);
2495
2496 static int __init snd_dbri_create(struct snd_card *card,
2497 struct sbus_dev *sdev,
2498 struct linux_prom_irqs *irq, int dev)
2499 {
2500 struct snd_dbri *dbri = card->private_data;
2501 int err;
2502
2503 spin_lock_init(&dbri->lock);
2504 dbri->card = card;
2505 dbri->sdev = sdev;
2506 dbri->irq = irq->pri;
2507
2508 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
2509 &dbri->dma_dvma);
2510 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2511
2512 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2513 dbri->dma, dbri->dma_dvma);
2514
2515 /* Map the registers into memory. */
2516 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2517 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2518 dbri->regs_size, "DBRI Registers");
2519 if (!dbri->regs) {
2520 printk(KERN_ERR "DBRI: could not allocate registers\n");
2521 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2522 (void *)dbri->dma, dbri->dma_dvma);
2523 return -EIO;
2524 }
2525
2526 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2527 "DBRI audio", dbri);
2528 if (err) {
2529 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2530 sbus_iounmap(dbri->regs, dbri->regs_size);
2531 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2532 (void *)dbri->dma, dbri->dma_dvma);
2533 return err;
2534 }
2535
2536 /* Do low level initialization of the DBRI and CS4215 chips */
2537 dbri_initialize(dbri);
2538 err = cs4215_init(dbri);
2539 if (err) {
2540 snd_dbri_free(dbri);
2541 return err;
2542 }
2543
2544 dbri->next = dbri_list;
2545 dbri_list = dbri;
2546
2547 return 0;
2548 }
2549
2550 static void snd_dbri_free(struct snd_dbri * dbri)
2551 {
2552 dprintk(D_GEN, "snd_dbri_free\n");
2553 dbri_reset(dbri);
2554
2555 if (dbri->irq)
2556 free_irq(dbri->irq, dbri);
2557
2558 if (dbri->regs)
2559 sbus_iounmap(dbri->regs, dbri->regs_size);
2560
2561 if (dbri->dma)
2562 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
2563 (void *)dbri->dma, dbri->dma_dvma);
2564 }
2565
2566 static int __init dbri_attach(int prom_node, struct sbus_dev *sdev)
2567 {
2568 struct snd_dbri *dbri;
2569 struct linux_prom_irqs irq;
2570 struct resource *rp;
2571 struct snd_card *card;
2572 static int dev = 0;
2573 int err;
2574
2575 if (sdev->prom_name[9] < 'e') {
2576 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
2577 sdev->prom_name[9]);
2578 return -EIO;
2579 }
2580
2581 if (dev >= SNDRV_CARDS)
2582 return -ENODEV;
2583 if (!enable[dev]) {
2584 dev++;
2585 return -ENOENT;
2586 }
2587
2588 err = prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq));
2589 if (err < 0) {
2590 printk(KERN_ERR "DBRI-%d: Firmware node lacks IRQ property.\n", dev);
2591 return -ENODEV;
2592 }
2593
2594 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2595 sizeof(struct snd_dbri));
2596 if (card == NULL)
2597 return -ENOMEM;
2598
2599 strcpy(card->driver, "DBRI");
2600 strcpy(card->shortname, "Sun DBRI");
2601 rp = &sdev->resource[0];
2602 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2603 card->shortname,
2604 rp->flags & 0xffL, (unsigned long long)rp->start, irq.pri);
2605
2606 if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) {
2607 snd_card_free(card);
2608 return err;
2609 }
2610
2611 dbri = card->private_data;
2612 if ((err = snd_dbri_pcm(dbri)) < 0)
2613 goto _err;
2614
2615 if ((err = snd_dbri_mixer(dbri)) < 0)
2616 goto _err;
2617
2618 /* /proc file handling */
2619 snd_dbri_proc(dbri);
2620
2621 if ((err = snd_card_register(card)) < 0)
2622 goto _err;
2623
2624 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2625 dev, dbri->regs,
2626 dbri->irq, sdev->prom_name[9], dbri->mm.version);
2627 dev++;
2628
2629 return 0;
2630
2631 _err:
2632 snd_dbri_free(dbri);
2633 snd_card_free(card);
2634 return err;
2635 }
2636
2637 /* Probe for the dbri chip and then attach the driver. */
2638 static int __init dbri_init(void)
2639 {
2640 struct sbus_bus *sbus;
2641 struct sbus_dev *sdev;
2642 int found = 0;
2643
2644 /* Probe each SBUS for the DBRI chip(s). */
2645 for_all_sbusdev(sdev, sbus) {
2646 /*
2647 * The version is coded in the last character
2648 */
2649 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
2650 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
2651 sdev->prom_name, sdev->slot);
2652
2653 if (dbri_attach(sdev->prom_node, sdev) == 0)
2654 found++;
2655 }
2656 }
2657
2658 return (found > 0) ? 0 : -EIO;
2659 }
2660
2661 static void __exit dbri_exit(void)
2662 {
2663 struct snd_dbri *this = dbri_list;
2664
2665 while (this != NULL) {
2666 struct snd_dbri *next = this->next;
2667 struct snd_card *card = this->card;
2668
2669 snd_dbri_free(this);
2670 snd_card_free(card);
2671 this = next;
2672 }
2673 dbri_list = NULL;
2674 }
2675
2676 module_init(dbri_init);
2677 module_exit(dbri_exit);
Tomato firmware and modifications.