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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / include / linux / pci.h
blobe86668a8a5cff747958fadcb4e30c09838a679fb
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 /* Include the pci register defines */
21 #include <linux/pci_regs.h>
22
23 /*
24 * The PCI interface treats multi-function devices as independent
25 * devices. The slot/function address of each device is encoded
26 * in a single byte as follows:
27 *
28 * 7:3 = slot
29 * 2:0 = function
30 */
31 #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
32 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
33 #define PCI_FUNC(devfn) ((devfn) & 0x07)
34
35 /* Ioctls for /proc/bus/pci/X/Y nodes. */
36 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
37 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
38 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
39 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
40 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
41
42 #ifdef __KERNEL__
43
44 #include <linux/mod_devicetable.h>
45
46 #include <linux/types.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <asm/atomic.h>
52 #include <linux/device.h>
53
54 /* Include the ID list */
55 #include <linux/pci_ids.h>
56
57 /* File state for mmap()s on /proc/bus/pci/X/Y */
58 enum pci_mmap_state {
59 pci_mmap_io,
60 pci_mmap_mem
61 };
62
63 /* This defines the direction arg to the DMA mapping routines. */
64 #define PCI_DMA_BIDIRECTIONAL 0
65 #define PCI_DMA_TODEVICE 1
66 #define PCI_DMA_FROMDEVICE 2
67 #define PCI_DMA_NONE 3
68
69 #define DEVICE_COUNT_COMPATIBLE 4
70 #define DEVICE_COUNT_RESOURCE 12
71
72 typedef int __bitwise pci_power_t;
73
74 #define PCI_D0 ((pci_power_t __force) 0)
75 #define PCI_D1 ((pci_power_t __force) 1)
76 #define PCI_D2 ((pci_power_t __force) 2)
77 #define PCI_D3hot ((pci_power_t __force) 3)
78 #define PCI_D3cold ((pci_power_t __force) 4)
79 #define PCI_UNKNOWN ((pci_power_t __force) 5)
80 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
81
82 /** The pci_channel state describes connectivity between the CPU and
83 * the pci device. If some PCI bus between here and the pci device
84 * has crashed or locked up, this info is reflected here.
85 */
86 typedef unsigned int __bitwise pci_channel_state_t;
87
88 enum pci_channel_state {
89 /* I/O channel is in normal state */
90 pci_channel_io_normal = (__force pci_channel_state_t) 1,
91
92 /* I/O to channel is blocked */
93 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
94
95 /* PCI card is dead */
96 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
97 };
98
99 typedef unsigned int __bitwise pcie_reset_state_t;
100
101 enum pcie_reset_state {
102 /* Reset is NOT asserted (Use to deassert reset) */
103 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
104
105 /* Use #PERST to reset PCI-E device */
106 pcie_warm_reset = (__force pcie_reset_state_t) 2,
107
108 /* Use PCI-E Hot Reset to reset device */
109 pcie_hot_reset = (__force pcie_reset_state_t) 3
110 };
111
112 typedef unsigned short __bitwise pci_bus_flags_t;
113 enum pci_bus_flags {
114 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
115 };
116
117 struct pci_cap_saved_state {
118 struct hlist_node next;
119 char cap_nr;
120 u32 data[0];
121 };
122
123 /*
124 * The pci_dev structure is used to describe PCI devices.
125 */
126 struct pci_dev {
127 struct list_head global_list; /* node in list of all PCI devices */
128 struct list_head bus_list; /* node in per-bus list */
129 struct pci_bus *bus; /* bus this device is on */
130 struct pci_bus *subordinate; /* bus this device bridges to */
131
132 void *sysdata; /* hook for sys-specific extension */
133 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
134
135 unsigned int devfn; /* encoded device & function index */
136 unsigned short vendor;
137 unsigned short device;
138 unsigned short subsystem_vendor;
139 unsigned short subsystem_device;
140 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
141 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
142 u8 rom_base_reg; /* which config register controls the ROM */
143 u8 pin; /* which interrupt pin this device uses */
144
145 struct pci_driver *driver; /* which driver has allocated this device */
146 u64 dma_mask; /* Mask of the bits of bus address this
147 device implements. Normally this is
148 0xffffffff. You only need to change
149 this if your device has broken DMA
150 or supports 64-bit transfers. */
151
152 pci_power_t current_state; /* Current operating state. In ACPI-speak,
153 this is D0-D3, D0 being fully functional,
154 and D3 being off. */
155
156 pci_channel_state_t error_state; /* current connectivity state */
157 struct device dev; /* Generic device interface */
158
159 /* device is compatible with these IDs */
160 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
161 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
162
163 int cfg_size; /* Size of configuration space */
164
165 /*
166 * Instead of touching interrupt line and base address registers
167 * directly, use the values stored here. They might be different!
168 */
169 unsigned int irq;
170 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
171
172 /* These fields are used by common fixups */
173 unsigned int transparent:1; /* Transparent PCI bridge */
174 unsigned int multifunction:1;/* Part of multi-function device */
175 /* keep track of device state */
176 unsigned int is_busmaster:1; /* device is busmaster */
177 unsigned int no_msi:1; /* device may not use msi */
178 unsigned int no_d1d2:1; /* only allow d0 or d3 */
179 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
180 unsigned int broken_parity_status:1; /* Device generates false positive parity */
181 unsigned int msi_enabled:1;
182 unsigned int msix_enabled:1;
183 unsigned int is_managed:1;
184 atomic_t enable_cnt; /* pci_enable_device has been called */
185
186 u32 saved_config_space[16]; /* config space saved at suspend time */
187 struct hlist_head saved_cap_space;
188 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
189 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
190 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
191 #ifdef CONFIG_PCI_MSI
192 struct list_head msi_list;
193 #endif
194 };
195
196 extern struct pci_dev *alloc_pci_dev(void);
197
198 #define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
199 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
200 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
201 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
202
203 static inline int pci_channel_offline(struct pci_dev *pdev)
204 {
205 return (pdev->error_state != pci_channel_io_normal);
206 }
207
208 static inline struct pci_cap_saved_state *pci_find_saved_cap(
209 struct pci_dev *pci_dev,char cap)
210 {
211 struct pci_cap_saved_state *tmp;
212 struct hlist_node *pos;
213
214 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
215 if (tmp->cap_nr == cap)
216 return tmp;
217 }
218 return NULL;
219 }
220
221 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
222 struct pci_cap_saved_state *new_cap)
223 {
224 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
225 }
226
227 /*
228 * For PCI devices, the region numbers are assigned this way:
229 *
230 * 0-5 standard PCI regions
231 * 6 expansion ROM
232 * 7-10 bridges: address space assigned to buses behind the bridge
233 */
234
235 #define PCI_ROM_RESOURCE 6
236 #define PCI_BRIDGE_RESOURCES 7
237 #define PCI_NUM_RESOURCES 11
238
239 #ifndef PCI_BUS_NUM_RESOURCES
240 #define PCI_BUS_NUM_RESOURCES 8
241 #endif
242
243 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
244
245 struct pci_bus {
246 struct list_head node; /* node in list of buses */
247 struct pci_bus *parent; /* parent bus this bridge is on */
248 struct list_head children; /* list of child buses */
249 struct list_head devices; /* list of devices on this bus */
250 struct pci_dev *self; /* bridge device as seen by parent */
251 struct resource *resource[PCI_BUS_NUM_RESOURCES];
252 /* address space routed to this bus */
253
254 struct pci_ops *ops; /* configuration access functions */
255 void *sysdata; /* hook for sys-specific extension */
256 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
257
258 unsigned char number; /* bus number */
259 unsigned char primary; /* number of primary bridge */
260 unsigned char secondary; /* number of secondary bridge */
261 unsigned char subordinate; /* max number of subordinate buses */
262
263 char name[48];
264
265 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
266 pci_bus_flags_t bus_flags; /* Inherited by child busses */
267 struct device *bridge;
268 struct class_device class_dev;
269 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
270 struct bin_attribute *legacy_mem; /* legacy mem */
271 };
272
273 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
274 #define to_pci_bus(n) container_of(n, struct pci_bus, class_dev)
275
276 /*
277 * Error values that may be returned by PCI functions.
278 */
279 #define PCIBIOS_SUCCESSFUL 0x00
280 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
281 #define PCIBIOS_BAD_VENDOR_ID 0x83
282 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
283 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
284 #define PCIBIOS_SET_FAILED 0x88
285 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
286
287 /* Low-level architecture-dependent routines */
288
289 struct pci_ops {
290 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
291 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
292 };
293
294 struct pci_raw_ops {
295 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
296 int reg, int len, u32 *val);
297 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
298 int reg, int len, u32 val);
299 };
300
301 extern struct pci_raw_ops *raw_pci_ops;
302
303 struct pci_bus_region {
304 unsigned long start;
305 unsigned long end;
306 };
307
308 struct pci_dynids {
309 spinlock_t lock; /* protects list, index */
310 struct list_head list; /* for IDs added at runtime */
311 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
312 };
313
314 /* ---------------------------------------------------------------- */
315 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
316 * a set fof callbacks in struct pci_error_handlers, then that device driver
317 * will be notified of PCI bus errors, and will be driven to recovery
318 * when an error occurs.
319 */
320
321 typedef unsigned int __bitwise pci_ers_result_t;
322
323 enum pci_ers_result {
324 /* no result/none/not supported in device driver */
325 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
326
327 /* Device driver can recover without slot reset */
328 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
329
330 /* Device driver wants slot to be reset. */
331 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
332
333 /* Device has completely failed, is unrecoverable */
334 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
335
336 /* Device driver is fully recovered and operational */
337 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
338 };
339
340 /* PCI bus error event callbacks */
341 struct pci_error_handlers
342 {
343 /* PCI bus error detected on this device */
344 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
345 enum pci_channel_state error);
346
347 /* MMIO has been re-enabled, but not DMA */
348 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
349
350 /* PCI Express link has been reset */
351 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
352
353 /* PCI slot has been reset */
354 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
355
356 /* Device driver may resume normal operations */
357 void (*resume)(struct pci_dev *dev);
358 };
359
360 /* ---------------------------------------------------------------- */
361
362 struct module;
363 struct pci_driver {
364 struct list_head node;
365 char *name;
366 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
367 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
368 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
369 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
370 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
371 int (*resume_early) (struct pci_dev *dev);
372 int (*resume) (struct pci_dev *dev); /* Device woken up */
373 int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */
374 void (*shutdown) (struct pci_dev *dev);
375
376 struct pci_error_handlers *err_handler;
377 struct device_driver driver;
378 struct pci_dynids dynids;
379 };
380
381 #define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
382
383 /**
384 * PCI_DEVICE - macro used to describe a specific pci device
385 * @vend: the 16 bit PCI Vendor ID
386 * @dev: the 16 bit PCI Device ID
387 *
388 * This macro is used to create a struct pci_device_id that matches a
389 * specific device. The subvendor and subdevice fields will be set to
390 * PCI_ANY_ID.
391 */
392 #define PCI_DEVICE(vend,dev) \
393 .vendor = (vend), .device = (dev), \
394 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
395
396 /**
397 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
398 * @dev_class: the class, subclass, prog-if triple for this device
399 * @dev_class_mask: the class mask for this device
400 *
401 * This macro is used to create a struct pci_device_id that matches a
402 * specific PCI class. The vendor, device, subvendor, and subdevice
403 * fields will be set to PCI_ANY_ID.
404 */
405 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
406 .class = (dev_class), .class_mask = (dev_class_mask), \
407 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
408 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
409
410 /**
411 * PCI_VDEVICE - macro used to describe a specific pci device in short form
412 * @vend: the vendor name
413 * @dev: the 16 bit PCI Device ID
414 *
415 * This macro is used to create a struct pci_device_id that matches a
416 * specific PCI device. The subvendor, and subdevice fields will be set
417 * to PCI_ANY_ID. The macro allows the next field to follow as the device
418 * private data.
419 */
420
421 #define PCI_VDEVICE(vendor, device) \
422 PCI_VENDOR_ID_##vendor, (device), \
423 PCI_ANY_ID, PCI_ANY_ID, 0, 0
424
425 /* these external functions are only available when PCI support is enabled */
426 #ifdef CONFIG_PCI
427
428 extern struct bus_type pci_bus_type;
429
430 /* Do NOT directly access these two variables, unless you are arch specific pci
431 * code, or pci core code. */
432 extern struct list_head pci_root_buses; /* list of all known PCI buses */
433 extern struct list_head pci_devices; /* list of all devices */
434 /* Some device drivers need know if pci is initiated */
435 extern int no_pci_devices(void);
436
437 void pcibios_fixup_bus(struct pci_bus *);
438 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
439 char *pcibios_setup (char *str);
440
441 /* Used only when drivers/pci/setup.c is used */
442 void pcibios_align_resource(void *, struct resource *, resource_size_t,
443 resource_size_t);
444 void pcibios_update_irq(struct pci_dev *, int irq);
445
446 /* Generic PCI functions used internally */
447
448 extern struct pci_bus *pci_find_bus(int domain, int busnr);
449 void pci_bus_add_devices(struct pci_bus *bus);
450 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
451 static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
452 {
453 struct pci_bus *root_bus;
454 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
455 if (root_bus)
456 pci_bus_add_devices(root_bus);
457 return root_bus;
458 }
459 struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
460 struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr);
461 int pci_scan_slot(struct pci_bus *bus, int devfn);
462 struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
463 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
464 unsigned int pci_scan_child_bus(struct pci_bus *bus);
465 int __must_check pci_bus_add_device(struct pci_dev *dev);
466 void pci_read_bridge_bases(struct pci_bus *child);
467 struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
468 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
469 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
470 extern void pci_dev_put(struct pci_dev *dev);
471 extern void pci_remove_bus(struct pci_bus *b);
472 extern void pci_remove_bus_device(struct pci_dev *dev);
473 extern void pci_stop_bus_device(struct pci_dev *dev);
474 void pci_setup_cardbus(struct pci_bus *bus);
475 extern void pci_sort_breadthfirst(void);
476
477 /* Generic PCI functions exported to card drivers */
478
479 struct pci_dev __deprecated *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
480 struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
481 int pci_find_capability (struct pci_dev *dev, int cap);
482 int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap);
483 int pci_find_ext_capability (struct pci_dev *dev, int cap);
484 int pci_find_ht_capability (struct pci_dev *dev, int ht_cap);
485 int pci_find_next_ht_capability (struct pci_dev *dev, int pos, int ht_cap);
486 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
487
488 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
489 struct pci_dev *from);
490 struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device,
491 struct pci_dev *from);
492
493 struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
494 unsigned int ss_vendor, unsigned int ss_device,
495 struct pci_dev *from);
496 struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn);
497 struct pci_dev *pci_get_bus_and_slot (unsigned int bus, unsigned int devfn);
498 struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from);
499 int pci_dev_present(const struct pci_device_id *ids);
500 const struct pci_device_id *pci_find_present(const struct pci_device_id *ids);
501
502 int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
503 int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
504 int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
505 int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
506 int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
507 int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
508
509 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
510 {
511 return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
512 }
513 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
514 {
515 return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
516 }
517 static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
518 {
519 return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
520 }
521 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
522 {
523 return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
524 }
525 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
526 {
527 return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
528 }
529 static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
530 {
531 return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
532 }
533
534 int __must_check pci_enable_device(struct pci_dev *dev);
535 int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask);
536 int __must_check pcim_enable_device(struct pci_dev *pdev);
537 void pcim_pin_device(struct pci_dev *pdev);
538
539 static inline int pci_is_managed(struct pci_dev *pdev)
540 {
541 return pdev->is_managed;
542 }
543
544 void pci_disable_device(struct pci_dev *dev);
545 void pci_set_master(struct pci_dev *dev);
546 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
547 #define HAVE_PCI_SET_MWI
548 int __must_check pci_set_mwi(struct pci_dev *dev);
549 void pci_clear_mwi(struct pci_dev *dev);
550 void pci_intx(struct pci_dev *dev, int enable);
551 void pci_msi_off(struct pci_dev *dev);
552 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
553 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
554 void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
555 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
556 int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i);
557 void pci_restore_bars(struct pci_dev *dev);
558 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
559
560 /* ROM control related routines */
561 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
562 void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size);
563 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
564 void pci_remove_rom(struct pci_dev *pdev);
565
566 /* Power management related routines */
567 int pci_save_state(struct pci_dev *dev);
568 int pci_restore_state(struct pci_dev *dev);
569 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
570 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
571 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
572
573 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
574 void pci_bus_assign_resources(struct pci_bus *bus);
575 void pci_bus_size_bridges(struct pci_bus *bus);
576 int pci_claim_resource(struct pci_dev *, int);
577 void pci_assign_unassigned_resources(void);
578 void pdev_enable_device(struct pci_dev *);
579 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
580 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
581 int (*)(struct pci_dev *, u8, u8));
582 #define HAVE_PCI_REQ_REGIONS 2
583 int __must_check pci_request_regions(struct pci_dev *, const char *);
584 void pci_release_regions(struct pci_dev *);
585 int __must_check pci_request_region(struct pci_dev *, int, const char *);
586 void pci_release_region(struct pci_dev *, int);
587 int pci_request_selected_regions(struct pci_dev *, int, const char *);
588 void pci_release_selected_regions(struct pci_dev *, int);
589
590 /* drivers/pci/bus.c */
591 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
592 struct resource *res, resource_size_t size,
593 resource_size_t align, resource_size_t min,
594 unsigned int type_mask,
595 void (*alignf)(void *, struct resource *,
596 resource_size_t, resource_size_t),
597 void *alignf_data);
598 void pci_enable_bridges(struct pci_bus *bus);
599
600 /* Proper probing supporting hot-pluggable devices */
601 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
602 const char *mod_name);
603 static inline int __must_check pci_register_driver(struct pci_driver *driver)
604 {
605 return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME);
606 }
607
608 void pci_unregister_driver(struct pci_driver *);
609 void pci_remove_behind_bridge(struct pci_dev *);
610 struct pci_driver *pci_dev_driver(const struct pci_dev *);
611 const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_dev *dev);
612 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
613 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
614
615 void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
616 void *userdata);
617 int pci_cfg_space_size(struct pci_dev *dev);
618 unsigned char pci_bus_max_busnr(struct pci_bus* bus);
619
620 /* kmem_cache style wrapper around pci_alloc_consistent() */
621
622 #include <linux/dmapool.h>
623
624 #define pci_pool dma_pool
625 #define pci_pool_create(name, pdev, size, align, allocation) \
626 dma_pool_create(name, &pdev->dev, size, align, allocation)
627 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
628 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
629 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
630
631 enum pci_dma_burst_strategy {
632 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
633 strategy_parameter is N/A */
634 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
635 byte boundaries */
636 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
637 strategy_parameter byte boundaries */
638 };
639
640 struct msix_entry {
641 u16 vector; /* kernel uses to write allocated vector */
642 u16 entry; /* driver uses to specify entry, OS writes */
643 };
644
645
646 #ifndef CONFIG_PCI_MSI
647 static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
648 static inline void pci_disable_msi(struct pci_dev *dev) {}
649 static inline int pci_enable_msix(struct pci_dev* dev,
650 struct msix_entry *entries, int nvec) {return -1;}
651 static inline void pci_disable_msix(struct pci_dev *dev) {}
652 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
653 #else
654 extern int pci_enable_msi(struct pci_dev *dev);
655 extern void pci_disable_msi(struct pci_dev *dev);
656 extern int pci_enable_msix(struct pci_dev* dev,
657 struct msix_entry *entries, int nvec);
658 extern void pci_disable_msix(struct pci_dev *dev);
659 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
660 #endif
661
662 #ifdef CONFIG_HT_IRQ
663 /* The functions a driver should call */
664 int ht_create_irq(struct pci_dev *dev, int idx);
665 void ht_destroy_irq(unsigned int irq);
666 #endif /* CONFIG_HT_IRQ */
667
668 extern void pci_block_user_cfg_access(struct pci_dev *dev);
669 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
670
671 /*
672 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
673 * a PCI domain is defined to be a set of PCI busses which share
674 * configuration space.
675 */
676 #ifndef CONFIG_PCI_DOMAINS
677 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
678 static inline int pci_proc_domain(struct pci_bus *bus)
679 {
680 return 0;
681 }
682 #endif
683
684 #else /* CONFIG_PCI is not enabled */
685
686 /*
687 * If the system does not have PCI, clearly these return errors. Define
688 * these as simple inline functions to avoid hair in drivers.
689 */
690
691 #define _PCI_NOP(o,s,t) \
692 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
693 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
694 #define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
695 _PCI_NOP(o,word,u16 x) \
696 _PCI_NOP(o,dword,u32 x)
697 _PCI_NOP_ALL(read, *)
698 _PCI_NOP_ALL(write,)
699
700 static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
701 { return NULL; }
702
703 static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
704 { return NULL; }
705
706 static inline struct pci_dev *pci_get_device(unsigned int vendor,
707 unsigned int device, struct pci_dev *from)
708 { return NULL; }
709
710 static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor,
711 unsigned int device, struct pci_dev *from)
712 { return NULL; }
713
714 static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
715 unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
716 { return NULL; }
717
718 static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
719 { return NULL; }
720
721 #define pci_dev_present(ids) (0)
722 #define no_pci_devices() (1)
723 #define pci_find_present(ids) (NULL)
724 #define pci_dev_put(dev) do { } while (0)
725
726 static inline void pci_set_master(struct pci_dev *dev) { }
727 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
728 static inline void pci_disable_device(struct pci_dev *dev) { }
729 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
730 static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
731 static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;}
732 static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
733 static inline void pci_unregister_driver(struct pci_driver *drv) { }
734 static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
735 static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; }
736 static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
737 static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
738
739 /* Power management related routines */
740 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
741 static inline int pci_restore_state(struct pci_dev *dev) { return 0; }
742 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; }
743 static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; }
744 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; }
745
746 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) { return -EIO; }
747 static inline void pci_release_regions(struct pci_dev *dev) { }
748
749 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
750
751 static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
752 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
753
754 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
755 { return NULL; }
756
757 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
758 unsigned int devfn)
759 { return NULL; }
760
761 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
762 unsigned int devfn)
763 { return NULL; }
764
765 #endif /* CONFIG_PCI */
766
767 /* Include architecture-dependent settings and functions */
768
769 #include <asm/pci.h>
770
771 /* these helpers provide future and backwards compatibility
772 * for accessing popular PCI BAR info */
773 #define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
774 #define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
775 #define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
776 #define pci_resource_len(dev,bar) \
777 ((pci_resource_start((dev),(bar)) == 0 && \
778 pci_resource_end((dev),(bar)) == \
779 pci_resource_start((dev),(bar))) ? 0 : \
780 \
781 (pci_resource_end((dev),(bar)) - \
782 pci_resource_start((dev),(bar)) + 1))
783
784 /* Similar to the helpers above, these manipulate per-pci_dev
785 * driver-specific data. They are really just a wrapper around
786 * the generic device structure functions of these calls.
787 */
788 static inline void *pci_get_drvdata (struct pci_dev *pdev)
789 {
790 return dev_get_drvdata(&pdev->dev);
791 }
792
793 static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
794 {
795 dev_set_drvdata(&pdev->dev, data);
796 }
797
798 /* If you want to know what to call your pci_dev, ask this function.
799 * Again, it's a wrapper around the generic device.
800 */
801 static inline char *pci_name(struct pci_dev *pdev)
802 {
803 return pdev->dev.bus_id;
804 }
805
806
807 /* Some archs don't want to expose struct resource to userland as-is
808 * in sysfs and /proc
809 */
810 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
811 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
812 const struct resource *rsrc, resource_size_t *start,
813 resource_size_t *end)
814 {
815 *start = rsrc->start;
816 *end = rsrc->end;
817 }
818 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
819
820
821 /*
822 * The world is not perfect and supplies us with broken PCI devices.
823 * For at least a part of these bugs we need a work-around, so both
824 * generic (drivers/pci/quirks.c) and per-architecture code can define
825 * fixup hooks to be called for particular buggy devices.
826 */
827
828 struct pci_fixup {
829 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
830 void (*hook)(struct pci_dev *dev);
831 };
832
833 enum pci_fixup_pass {
834 pci_fixup_early, /* Before probing BARs */
835 pci_fixup_header, /* After reading configuration header */
836 pci_fixup_final, /* Final phase of device fixups */
837 pci_fixup_enable, /* pci_enable_device() time */
838 pci_fixup_resume, /* pci_enable_device() time */
839 };
840
841 /* Anonymous variables would be nice... */
842 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
843 static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
844 __attribute__((__section__(#section))) = { vendor, device, hook };
845 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
846 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
847 vendor##device##hook, vendor, device, hook)
848 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
849 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
850 vendor##device##hook, vendor, device, hook)
851 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
852 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
853 vendor##device##hook, vendor, device, hook)
854 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
855 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
856 vendor##device##hook, vendor, device, hook)
857 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
858 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
859 resume##vendor##device##hook, vendor, device, hook)
860
861
862 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
863
864 void __iomem * pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
865 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
866 void __iomem * const * pcim_iomap_table(struct pci_dev *pdev);
867 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
868 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
869
870 extern int pci_pci_problems;
871 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
872 #define PCIPCI_TRITON 2
873 #define PCIPCI_NATOMA 4
874 #define PCIPCI_VIAETBF 8
875 #define PCIPCI_VSFX 16
876 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
877 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
878
879 extern unsigned long pci_cardbus_io_size;
880 extern unsigned long pci_cardbus_mem_size;
881
882 #endif /* __KERNEL__ */
883 #endif /* LINUX_PCI_H */
Tomato firmware and modifications.