2 * linux/include/linux/mtd/nand.h
4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * $Id: nand.h,v 1.1.1.1 2007-08-03 18:53:44 $
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 * Contains standard defines and IDs for NAND flash devices
20 #ifndef __LINUX_MTD_NAND_H
21 #define __LINUX_MTD_NAND_H
23 #include <linux/wait.h>
24 #include <linux/spinlock.h>
25 #include <linux/mtd/mtd.h>
28 /* Scan and identify a NAND device */
29 extern int nand_scan (struct mtd_info
*mtd
, int max_chips
);
30 /* Separate phases of nand_scan(), allowing board driver to intervene
31 * and override command or ECC setup according to flash type */
32 extern int nand_scan_ident(struct mtd_info
*mtd
, int max_chips
);
33 extern int nand_scan_tail(struct mtd_info
*mtd
);
35 /* Free resources held by the NAND device */
36 extern void nand_release (struct mtd_info
*mtd
);
38 /* Internal helper for board drivers which need to override command function */
39 extern void nand_wait_ready(struct mtd_info
*mtd
);
41 /* The maximum number of NAND chips in an array */
42 #define NAND_MAX_CHIPS 8
44 /* This constant declares the max. oobsize / page, which
45 * is supported now. If you add a chip with bigger oobsize/page
46 * adjust this accordingly.
48 #ifdef CONFIG_MTD_BRCMNAND
49 #define NAND_MAX_OOBSIZE 128
50 #define NAND_MAX_PAGESIZE 4096
52 #define NAND_MAX_OOBSIZE 64
53 #define NAND_MAX_PAGESIZE 2048
54 #endif /* CONFIG_MTD_BRCMNAND */
57 * Constants for hardware specific CLE/ALE/NCE function
59 * These are bits which can be or'ed to set/clear multiple
62 /* Select the chip by setting nCE to low */
64 /* Select the command latch by setting CLE to high */
66 /* Select the address latch by setting ALE to high */
69 #ifdef CONFIG_MTD_BRCMNAND
70 # define NAND_ALE_COL 0x08
71 # define NAND_ALE_ROW 0x10
72 #endif /* CONFIG_MTD_BRCMNAND */
74 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
75 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
76 #define NAND_CTRL_CHANGE 0x80
79 * Standard NAND flash commands
81 #define NAND_CMD_READ0 0
82 #define NAND_CMD_READ1 1
83 #define NAND_CMD_RNDOUT 5
84 #define NAND_CMD_PAGEPROG 0x10
85 #define NAND_CMD_READOOB 0x50
86 #define NAND_CMD_ERASE1 0x60
87 #define NAND_CMD_STATUS 0x70
88 #define NAND_CMD_STATUS_MULTI 0x71
89 #define NAND_CMD_SEQIN 0x80
90 #define NAND_CMD_RNDIN 0x85
91 #define NAND_CMD_READID 0x90
92 #define NAND_CMD_ERASE2 0xd0
93 #define NAND_CMD_RESET 0xff
95 /* Extended commands for large page devices */
96 #define NAND_CMD_READSTART 0x30
97 #define NAND_CMD_RNDOUTSTART 0xE0
98 #define NAND_CMD_CACHEDPROG 0x15
100 /* Extended commands for AG-AND device */
102 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
103 * there is no way to distinguish that from NAND_CMD_READ0
104 * until the remaining sequence of commands has been completed
105 * so add a high order bit and mask it off in the command.
107 #define NAND_CMD_DEPLETE1 0x100
108 #define NAND_CMD_DEPLETE2 0x38
109 #define NAND_CMD_STATUS_MULTI 0x71
110 #define NAND_CMD_STATUS_ERROR 0x72
111 /* multi-bank error status (banks 0-3) */
112 #define NAND_CMD_STATUS_ERROR0 0x73
113 #define NAND_CMD_STATUS_ERROR1 0x74
114 #define NAND_CMD_STATUS_ERROR2 0x75
115 #define NAND_CMD_STATUS_ERROR3 0x76
116 #define NAND_CMD_STATUS_RESET 0x7f
117 #define NAND_CMD_STATUS_CLEAR 0xff
119 #define NAND_CMD_NONE -1
122 #define NAND_STATUS_FAIL 0x01
123 #define NAND_STATUS_FAIL_N1 0x02
124 #define NAND_STATUS_TRUE_READY 0x20
125 #define NAND_STATUS_READY 0x40
126 #define NAND_STATUS_WP 0x80
129 * Constants for ECC_MODES
135 NAND_ECC_HW_SYNDROME
,
139 * Constants for Hardware ECC
141 /* Reset Hardware ECC for read */
142 #define NAND_ECC_READ 0
143 /* Reset Hardware ECC for write */
144 #define NAND_ECC_WRITE 1
145 /* Enable Hardware ECC before syndrom is read back from flash */
146 #define NAND_ECC_READSYN 2
148 /* Bit mask for flags passed to do_nand_read_ecc */
149 #define NAND_GET_DEVICE 0x80
152 /* Option constants for bizarre disfunctionality and real
155 /* Chip can not auto increment pages */
156 #define NAND_NO_AUTOINCR 0x00000001
157 /* Buswitdh is 16 bit */
158 #define NAND_BUSWIDTH_16 0x00000002
159 /* Device supports partial programming without padding */
160 #define NAND_NO_PADDING 0x00000004
161 /* Chip has cache program function */
162 #define NAND_CACHEPRG 0x00000008
163 /* Chip has copy back function */
164 #define NAND_COPYBACK 0x00000010
165 /* AND Chip which has 4 banks and a confusing page / block
166 * assignment. See Renesas datasheet for further information */
167 #define NAND_IS_AND 0x00000020
168 /* Chip has a array of 4 pages which can be read without
169 * additional ready /busy waits */
170 #define NAND_4PAGE_ARRAY 0x00000040
171 /* Chip requires that BBT is periodically rewritten to prevent
172 * bits from adjacent blocks from 'leaking' in altering data.
173 * This happens with the Renesas AG-AND chips, possibly others. */
174 #define BBT_AUTO_REFRESH 0x00000080
175 /* Chip does not require ready check on read. True
176 * for all large page devices, as they do not support
178 #define NAND_NO_READRDY 0x00000100
179 /* Chip does not allow subpage writes */
180 #define NAND_NO_SUBPAGE_WRITE 0x00000200
183 /* Options valid for Samsung large page devices */
184 #define NAND_SAMSUNG_LP_OPTIONS \
185 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
187 /* Macros to identify the above */
188 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
189 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
190 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
191 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
193 /* Large page NAND with SOFT_ECC should support subpage reads */
194 /* It's patched from Linux 2.6.27.57 */
195 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
196 && (chip->page_shift > 9))
198 /* Mask to zero out the chip options, which come from the id table */
199 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
201 /* Non chip related options */
202 /* Use a flash based bad block table. This option is passed to the
203 * default bad block table function. */
204 #define NAND_USE_FLASH_BBT 0x00010000
205 /* This option skips the bbt scan during initialization. */
206 #define NAND_SKIP_BBTSCAN 0x00020000
207 /* This option is defined if the board driver allocates its own buffers
208 (e.g. because it needs them DMA-coherent */
209 #define NAND_OWN_BUFFERS 0x00040000
210 /* Options set by nand scan */
211 /* Nand scan has allocated controller struct */
212 #define NAND_CONTROLLER_ALLOC 0x80000000
214 /* Cell info constants */
215 #define NAND_CI_CHIPNR_MSK 0x03
216 #define NAND_CI_CELLTYPE_MSK 0x0C
218 #ifdef CONFIG_MTD_BRCMNAND
219 #define NAND_IS_MLC(chip) ((chip)->cellinfo & NAND_CI_CELLTYPE_MSK)
220 #endif /* CONFIG_MTD_BRCMNAND */
223 * nand_state_t - chip states
224 * Enumeration for NAND flash chip state
240 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
241 * @lock: protection lock
242 * @active: the mtd device which holds the controller currently
243 * @wq: wait queue to sleep on if a NAND operation is in progress
244 * used instead of the per chip wait queue when a hw controller is available
246 struct nand_hw_control
{
248 struct nand_chip
*active
;
249 wait_queue_head_t wq
;
253 * struct nand_ecc_ctrl - Control structure for ecc
255 * @steps: number of ecc steps per page
256 * @size: data bytes per ecc step
257 * @bytes: ecc bytes per step
258 * @total: total number of ecc bytes per page
259 * @prepad: padding information for syndrome based ecc generators
260 * @postpad: padding information for syndrome based ecc generators
261 * @layout: ECC layout control struct pointer
262 * @hwctl: function to control hardware ecc generator. Must only
263 * be provided if an hardware ECC is available
264 * @calculate: function for ecc calculation or readback from ecc hardware
265 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
266 * @read_page_raw: function to read a raw page without ECC
267 * @write_page_raw: function to write a raw page without ECC
268 * @read_page: function to read a page according to the ecc generator requirements
269 * @write_page: function to write a page according to the ecc generator requirements
270 * @read_oob: function to read chip OOB data
271 * @write_oob: function to write chip OOB data
273 struct nand_ecc_ctrl
{
274 nand_ecc_modes_t mode
;
275 #ifdef CONFIG_MTD_BRCMNAND
278 #endif /* CONFIG_MTD_BRCMNAND */
285 struct nand_ecclayout
*layout
;
286 void (*hwctl
)(struct mtd_info
*mtd
, int mode
);
287 int (*calculate
)(struct mtd_info
*mtd
,
290 int (*correct
)(struct mtd_info
*mtd
, uint8_t *dat
,
293 int (*read_page_raw
)(struct mtd_info
*mtd
,
294 struct nand_chip
*chip
,
296 void (*write_page_raw
)(struct mtd_info
*mtd
,
297 struct nand_chip
*chip
,
299 int (*read_page
)(struct mtd_info
*mtd
,
300 struct nand_chip
*chip
,
302 /* Patched from Linux 2.6.27.57 */
303 int (*read_subpage
)(struct mtd_info
*mtd
,
304 struct nand_chip
*chip
,
305 uint32_t offs
, uint32_t len
,
307 void (*write_page
)(struct mtd_info
*mtd
,
308 struct nand_chip
*chip
,
310 int (*read_oob
)(struct mtd_info
*mtd
,
311 struct nand_chip
*chip
,
314 int (*write_oob
)(struct mtd_info
*mtd
,
315 struct nand_chip
*chip
,
320 * struct nand_buffers - buffer structure for read/write
321 * @ecccalc: buffer for calculated ecc
322 * @ecccode: buffer for ecc read from flash
323 * @databuf: buffer for data - dynamically sized
325 * Do not change the order of buffers. databuf and oobrbuf must be in
328 struct nand_buffers
{
329 uint8_t ecccalc
[NAND_MAX_OOBSIZE
];
330 uint8_t ecccode
[NAND_MAX_OOBSIZE
];
331 uint8_t databuf
[NAND_MAX_PAGESIZE
+ NAND_MAX_OOBSIZE
];
335 * struct nand_chip - NAND Private Flash Chip Data
336 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
337 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
338 * @read_byte: [REPLACEABLE] read one byte from the chip
339 * @read_word: [REPLACEABLE] read one word from the chip
340 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
341 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
342 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
343 * @select_chip: [REPLACEABLE] select chip nr
344 * @block_bad: [REPLACEABLE] check, if the block is bad
345 * @block_markbad: [REPLACEABLE] mark the block bad
346 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
347 * ALE/CLE/nCE. Also used to write command and address
348 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
349 * If set to NULL no access to ready/busy is available and the ready/busy information
350 * is read from the chip status register
351 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
352 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
353 * @ecc: [BOARDSPECIFIC] ecc control ctructure
354 * @buffers: buffer structure for read/write
355 * @hwcontrol: platform-specific hardware control structure
356 * @ops: oob operation operands
357 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
358 * @scan_bbt: [REPLACEABLE] function to scan bad block table
359 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
360 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
361 * @state: [INTERN] the current state of the NAND device
362 * @oob_poi: poison value buffer
363 * @page_shift: [INTERN] number of address bits in a page (column address bits)
364 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
365 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
366 * @chip_shift: [INTERN] number of address bits in one chip
367 * @datbuf: [INTERN] internal buffer for one page + oob
368 * @oobbuf: [INTERN] oob buffer for one eraseblock
369 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
370 * @data_poi: [INTERN] pointer to a data buffer
371 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
372 * special functionality. See the defines for further explanation
373 * @badblockpos: [INTERN] position of the bad block marker in the oob area
374 * @cellinfo: [INTERN] MLC/multichip data from chip ident
375 * @numchips: [INTERN] number of physical chips
376 * @chipsize: [INTERN] the size of one chip for multichip arrays
377 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
378 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
379 * @subpagesize: [INTERN] holds the subpagesize
380 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
381 * @bbt: [INTERN] bad block table pointer
382 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
383 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
384 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
385 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
386 * which is shared among multiple independend devices
387 * @priv: [OPTIONAL] pointer to private chip date
388 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
389 * (determine if errors are correctable)
390 * @write_page: [REPLACEABLE] High-level page write function
394 void __iomem
*IO_ADDR_R
;
395 void __iomem
*IO_ADDR_W
;
397 uint8_t (*read_byte
)(struct mtd_info
*mtd
);
398 u16 (*read_word
)(struct mtd_info
*mtd
);
399 void (*write_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
400 void (*read_buf
)(struct mtd_info
*mtd
, uint8_t *buf
, int len
);
401 int (*verify_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
402 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
403 int (*block_bad
)(struct mtd_info
*mtd
, loff_t ofs
, int getchip
);
404 int (*block_markbad
)(struct mtd_info
*mtd
, loff_t ofs
);
405 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
,
407 int (*dev_ready
)(struct mtd_info
*mtd
);
408 void (*cmdfunc
)(struct mtd_info
*mtd
, unsigned command
, int column
, int page_addr
);
409 int (*waitfunc
)(struct mtd_info
*mtd
, struct nand_chip
*this);
410 void (*erase_cmd
)(struct mtd_info
*mtd
, int page
);
411 int (*scan_bbt
)(struct mtd_info
*mtd
);
412 #ifdef CONFIG_MTD_BRCMNAND
413 int (*erase_bbt
)(struct mtd_info
*mtd
, struct erase_info
*instr
, int allowbbt
);
414 int (*get_device
)(struct nand_chip
*chip
, struct mtd_info
*mtd
, int new_state
);
415 void (*release_device
)(struct mtd_info
*mtd
);
416 #endif /* CONFIG_MTD_BRCMNAND */
417 int (*errstat
)(struct mtd_info
*mtd
, struct nand_chip
*this, int state
, int status
, int page
);
418 int (*write_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
419 const uint8_t *buf
, int page
, int cached
, int raw
);
422 unsigned int options
;
425 int phys_erase_shift
;
429 unsigned long chipsize
;
435 #ifdef CONFIG_MTD_BRCMNAND
437 #endif /* CONFIG_MTD_BRCMNAND */
442 struct nand_hw_control
*controller
;
443 struct nand_ecclayout
*ecclayout
;
445 struct nand_ecc_ctrl ecc
;
446 struct nand_buffers
*buffers
;
447 struct nand_hw_control hwcontrol
;
449 struct mtd_oob_ops ops
;
452 struct nand_bbt_descr
*bbt_td
;
453 struct nand_bbt_descr
*bbt_md
;
455 struct nand_bbt_descr
*badblock_pattern
;
461 * NAND Flash Manufacturer ID Codes
463 #define NAND_MFR_TOSHIBA 0x98
464 #define NAND_MFR_SAMSUNG 0xec
465 #define NAND_MFR_FUJITSU 0x04
466 #define NAND_MFR_NATIONAL 0x8f
467 #define NAND_MFR_RENESAS 0x07
468 #define NAND_MFR_STMICRO 0x20
469 #define NAND_MFR_HYNIX 0xad
470 #define NAND_MFR_MICRON 0x2c
473 * struct nand_flash_dev - NAND Flash Device ID Structure
474 * @name: Identify the device type
475 * @id: device ID code
476 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
477 * If the pagesize is 0, then the real pagesize
478 * and the eraseize are determined from the
479 * extended id bytes in the chip
480 * @erasesize: Size of an erase block in the flash device.
481 * @chipsize: Total chipsize in Mega Bytes
482 * @options: Bitfield to store chip relevant options
484 struct nand_flash_dev
{
487 unsigned long pagesize
;
488 unsigned long chipsize
;
489 unsigned long erasesize
;
490 unsigned long options
;
494 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
495 * @name: Manufacturer name
496 * @id: manufacturer ID code of device.
498 struct nand_manufacturers
{
503 extern struct nand_flash_dev nand_flash_ids
[];
504 extern struct nand_manufacturers nand_manuf_ids
[];
507 * struct nand_bbt_descr - bad block table descriptor
508 * @options: options for this descriptor
509 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
510 * when bbt is searched, then we store the found bbts pages here.
511 * Its an array and supports up to 8 chips now
512 * @offs: offset of the pattern in the oob area of the page
513 * @veroffs: offset of the bbt version counter in the oob are of the page
514 * @version: version read from the bbt page during scan
515 * @len: length of the pattern, if 0 no pattern check is performed
516 * @maxblocks: maximum number of blocks to search for a bbt. This number of
517 * blocks is reserved at the end of the device where the tables are
519 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
520 * bad) block in the stored bbt
521 * @pattern: pattern to identify bad block table or factory marked good /
522 * bad blocks, can be NULL, if len = 0
524 * Descriptor for the bad block table marker and the descriptor for the
525 * pattern which identifies good and bad blocks. The assumption is made
526 * that the pattern and the version count are always located in the oob area
527 * of the first block.
529 struct nand_bbt_descr
{
531 int pages
[NAND_MAX_CHIPS
];
534 uint8_t version
[NAND_MAX_CHIPS
];
537 int reserved_block_code
;
541 /* Options for the bad block table descriptors */
543 /* The number of bits used per block in the bbt on the device */
544 #define NAND_BBT_NRBITS_MSK 0x0000000F
545 #define NAND_BBT_1BIT 0x00000001
546 #define NAND_BBT_2BIT 0x00000002
547 #define NAND_BBT_4BIT 0x00000004
548 #define NAND_BBT_8BIT 0x00000008
549 /* The bad block table is in the last good block of the device */
550 #define NAND_BBT_LASTBLOCK 0x00000010
551 /* The bbt is at the given page, else we must scan for the bbt */
552 #define NAND_BBT_ABSPAGE 0x00000020
553 /* The bbt is at the given page, else we must scan for the bbt */
554 #define NAND_BBT_SEARCH 0x00000040
555 /* bbt is stored per chip on multichip devices */
556 #define NAND_BBT_PERCHIP 0x00000080
557 /* bbt has a version counter at offset veroffs */
558 #define NAND_BBT_VERSION 0x00000100
559 /* Create a bbt if none axists */
560 #define NAND_BBT_CREATE 0x00000200
561 /* Search good / bad pattern through all pages of a block */
562 #define NAND_BBT_SCANALLPAGES 0x00000400
563 /* Scan block empty during good / bad block scan */
564 #define NAND_BBT_SCANEMPTY 0x00000800
565 /* Write bbt if neccecary */
566 #define NAND_BBT_WRITE 0x00001000
567 /* Read and write back block contents when writing bbt */
568 #define NAND_BBT_SAVECONTENT 0x00002000
569 /* Search good / bad pattern on the first and the second page */
570 #define NAND_BBT_SCAN2NDPAGE 0x00004000
572 /* The maximum number of blocks to scan for a bbt */
573 #define NAND_BBT_SCAN_MAXBLOCKS 4
575 extern int nand_scan_bbt(struct mtd_info
*mtd
, struct nand_bbt_descr
*bd
);
576 extern int nand_update_bbt(struct mtd_info
*mtd
, loff_t offs
);
577 extern int nand_default_bbt(struct mtd_info
*mtd
);
578 extern int nand_isbad_bbt(struct mtd_info
*mtd
, loff_t offs
, int allowbbt
);
579 extern int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
581 extern int nand_do_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
582 size_t * retlen
, uint8_t * buf
);
585 * Constants for oob configuration
587 #define NAND_SMALL_BADBLOCK_POS 5
588 #define NAND_LARGE_BADBLOCK_POS 0
591 * struct platform_nand_chip - chip level device structure
592 * @nr_chips: max. number of chips to scan for
593 * @chip_offset: chip number offset
594 * @nr_partitions: number of partitions pointed to by partitions (or zero)
595 * @partitions: mtd partition list
596 * @chip_delay: R/B delay value in us
597 * @options: Option flags, e.g. 16bit buswidth
598 * @ecclayout: ecc layout info structure
599 * @part_probe_types: NULL-terminated array of probe types
600 * @priv: hardware controller specific settings
602 struct platform_nand_chip
{
606 struct mtd_partition
*partitions
;
607 struct nand_ecclayout
*ecclayout
;
609 unsigned int options
;
610 const char **part_probe_types
;
615 * struct platform_nand_ctrl - controller level device structure
616 * @hwcontrol: platform specific hardware control structure
617 * @dev_ready: platform specific function to read ready/busy pin
618 * @select_chip: platform specific chip select function
619 * @cmd_ctrl: platform specific function for controlling
620 * ALE/CLE/nCE. Also used to write command and address
621 * @priv: private data to transport driver specific settings
623 * All fields are optional and depend on the hardware driver requirements
625 struct platform_nand_ctrl
{
626 void (*hwcontrol
)(struct mtd_info
*mtd
, int cmd
);
627 int (*dev_ready
)(struct mtd_info
*mtd
);
628 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
629 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
,
635 * struct platform_nand_data - container structure for platform-specific data
636 * @chip: chip level chip structure
637 * @ctrl: controller level device structure
639 struct platform_nand_data
{
640 struct platform_nand_chip chip
;
641 struct platform_nand_ctrl ctrl
;
644 /* Some helpers to access the data structures */
646 struct platform_nand_chip
*get_platform_nandchip(struct mtd_info
*mtd
)
648 struct nand_chip
*chip
= mtd
->priv
;
653 #endif /* __LINUX_MTD_NAND_H */