release/src-rt-6.x/linux/linux-2.6/include/asm-powerpc/pgtable-64k.h

   1 #ifndef _ASM_POWERPC_PGTABLE_64K_H
   2 #define _ASM_POWERPC_PGTABLE_64K_H
   3
   4 #include <asm-generic/pgtable-nopud.h>
   5
   6
   7 #define PTE_INDEX_SIZE  12
   8 #define PMD_INDEX_SIZE  12
   9 #define PUD_INDEX_SIZE  0
  10 #define PGD_INDEX_SIZE  4
  11
  12 #define PTE_TABLE_SIZE  (sizeof(real_pte_t) << PTE_INDEX_SIZE)
  13 #define PMD_TABLE_SIZE  (sizeof(pmd_t) << PMD_INDEX_SIZE)
  14 #define PGD_TABLE_SIZE  (sizeof(pgd_t) << PGD_INDEX_SIZE)
  15
  16 #define PTRS_PER_PTE    (1 << PTE_INDEX_SIZE)
  17 #define PTRS_PER_PMD    (1 << PMD_INDEX_SIZE)
  18 #define PTRS_PER_PGD    (1 << PGD_INDEX_SIZE)
  19
  20 /* With 4k base page size, hugepage PTEs go at the PMD level */
  21 #define MIN_HUGEPTE_SHIFT       PAGE_SHIFT
  22
  23 /* PMD_SHIFT determines what a second-level page table entry can map */
  24 #define PMD_SHIFT       (PAGE_SHIFT + PTE_INDEX_SIZE)
  25 #define PMD_SIZE        (1UL << PMD_SHIFT)
  26 #define PMD_MASK        (~(PMD_SIZE-1))
  27
  28 /* PGDIR_SHIFT determines what a third-level page table entry can map */
  29 #define PGDIR_SHIFT     (PMD_SHIFT + PMD_INDEX_SIZE)
  30 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  31 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  32
  33 /* Additional PTE bits (don't change without checking asm in hash_low.S) */
  34 #define _PAGE_HPTE_SUB  0x0ffff000 /* combo only: sub pages HPTE bits */
  35 #define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
  36 #define _PAGE_COMBO     0x10000000 /* this is a combo 4k page */
  37 #define _PAGE_4K_PFN    0x20000000 /* PFN is for a single 4k page */
  38
  39 /* Note the full page bits must be in the same location as for normal
  40  * 4k pages as the same asssembly will be used to insert 64K pages
  41  * wether the kernel has CONFIG_PPC_64K_PAGES or not
  42  */
  43 #define _PAGE_F_SECOND  0x00008000 /* full page: hidx bits */
  44 #define _PAGE_F_GIX     0x00007000 /* full page: hidx bits */
  45
  46 /* PTE flags to conserve for HPTE identification */
  47 #define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_HPTE_SUB |\
  48                          _PAGE_COMBO)
  49
  50 /* Shift to put page number into pte.
  51  *
  52  * That gives us a max RPN of 32 bits, which means a max of 48 bits
  53  * of addressable physical space.
  54  * We could get 3 more bits here by setting PTE_RPN_SHIFT to 29 but
  55  * 32 makes PTEs more readable for debugging for now :)
  56  */
  57 #define PTE_RPN_SHIFT   (32)
  58 #define PTE_RPN_MAX     (1UL << (64 - PTE_RPN_SHIFT))
  59 #define PTE_RPN_MASK    (~((1UL<<PTE_RPN_SHIFT)-1))
  60
  61 /* _PAGE_CHG_MASK masks of bits that are to be preserved accross
  62  * pgprot changes
  63  */
  64 #define _PAGE_CHG_MASK  (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
  65                          _PAGE_ACCESSED)
  66
  67 /* Bits to mask out from a PMD to get to the PTE page */
  68 #define PMD_MASKED_BITS         0x1ff
  69 /* Bits to mask out from a PGD/PUD to get to the PMD page */
  70 #define PUD_MASKED_BITS         0x1ff
  71
  72 /* Manipulate "rpte" values */
  73 #define __real_pte(e,p)         ((real_pte_t) { \
  74         (e), pte_val(*((p) + PTRS_PER_PTE)) })
  75 #define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
  76         (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
  77 #define __rpte_to_pte(r)        ((r).pte)
  78 #define __rpte_sub_valid(rpte, index) \
  79         (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
  80
  81
  82 /* Trick: we set __end to va + 64k, which happens works for
  83  * a 16M page as well as we want only one iteration
  84  */
  85 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)          \
  86         do {                                                                \
  87                 unsigned long __end = va + PAGE_SIZE;                       \
  88                 unsigned __split = (psize == MMU_PAGE_4K ||                 \
  89                                     psize == MMU_PAGE_64K_AP);              \
  90                 shift = mmu_psize_defs[psize].shift;                        \
  91                 for (index = 0; va < __end; index++, va += (1 << shift)) {  \
  92                         if (!__split || __rpte_sub_valid(rpte, index)) do { \
  93
  94 #define pte_iterate_hashed_end() } while(0); } } while(0)
  95
  96 #define pte_pagesize_index(mm, addr, pte)       \
  97         (((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
  98
  99 #define remap_4k_pfn(vma, addr, pfn, prot)                              \
 100         remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE,                \
 101                         __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
 102
 103 #endif /* _ASM_POWERPC_PGTABLE_64K_H */