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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / include / asm-mips / stackframe.h
blob6447b975bf27f686ff64a641eb6b66544e973b76
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
8 * Copyright (C) 1999 Silicon Graphics, Inc.
9 */
10 #ifndef _ASM_STACKFRAME_H
11 #define _ASM_STACKFRAME_H
12
13 #include <linux/threads.h>
14
15 #include <asm/asm.h>
16 #include <asm/asmmacro.h>
17 #include <asm/mipsregs.h>
18 #include <asm/asm-offsets.h>
19
20 /*
21 * For SMTC kernel, global IE should be left set, and interrupts
22 * controlled exclusively via IXMT.
23 */
24 #ifdef CONFIG_MIPS_MT_SMTC
25 #define STATMASK 0x1e
26 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
27 #define STATMASK 0x3f
28 #else
29 #define STATMASK 0x1f
30 #endif
31
32 #ifdef CONFIG_MIPS_MT_SMTC
33 #include <asm/mipsmtregs.h>
34 #endif /* CONFIG_MIPS_MT_SMTC */
35
36 .macro SAVE_AT
37 .set push
38 .set noat
39 LONG_S $1, PT_R1(sp)
40 .set pop
41 .endm
42
43 .macro SAVE_TEMP
44 #ifdef CONFIG_CPU_HAS_SMARTMIPS
45 mflhxu v1
46 LONG_S v1, PT_LO(sp)
47 mflhxu v1
48 LONG_S v1, PT_HI(sp)
49 mflhxu v1
50 LONG_S v1, PT_ACX(sp)
51 #else
52 mfhi v1
53 LONG_S v1, PT_HI(sp)
54 mflo v1
55 LONG_S v1, PT_LO(sp)
56 #endif
57 #ifdef CONFIG_32BIT
58 LONG_S $8, PT_R8(sp)
59 LONG_S $9, PT_R9(sp)
60 #endif
61 LONG_S $10, PT_R10(sp)
62 LONG_S $11, PT_R11(sp)
63 LONG_S $12, PT_R12(sp)
64 LONG_S $13, PT_R13(sp)
65 LONG_S $14, PT_R14(sp)
66 LONG_S $15, PT_R15(sp)
67 LONG_S $24, PT_R24(sp)
68 .endm
69
70 .macro SAVE_STATIC
71 LONG_S $16, PT_R16(sp)
72 LONG_S $17, PT_R17(sp)
73 LONG_S $18, PT_R18(sp)
74 LONG_S $19, PT_R19(sp)
75 LONG_S $20, PT_R20(sp)
76 LONG_S $21, PT_R21(sp)
77 LONG_S $22, PT_R22(sp)
78 LONG_S $23, PT_R23(sp)
79 LONG_S $30, PT_R30(sp)
80 .endm
81
82 #ifdef CONFIG_SMP
83 #ifdef CONFIG_MIPS_MT_SMTC
84 #define PTEBASE_SHIFT 19 /* TCBIND */
85 #else
86 #define PTEBASE_SHIFT 23 /* CONTEXT */
87 #endif
88 .macro get_saved_sp /* SMP variation */
89 #ifdef CONFIG_MIPS_MT_SMTC
90 mfc0 k0, CP0_TCBIND
91 #else
92 MFC0 k0, CP0_CONTEXT
93 #endif
94 #if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4)
95 lui k1, %highest(kernelsp)
96 daddiu k1, %higher(kernelsp)
97 dsll k1, 16
98 daddiu k1, %hi(kernelsp)
99 dsll k1, 16
100 #else
101 lui k1, %hi(kernelsp)
102 #endif
103 LONG_SRL k0, PTEBASE_SHIFT
104 LONG_ADDU k1, k0
105 LONG_L k1, %lo(kernelsp)(k1)
106 .endm
107
108 .macro set_saved_sp stackp temp temp2
109 #ifdef CONFIG_MIPS_MT_SMTC
110 mfc0 \temp, CP0_TCBIND
111 #else
112 MFC0 \temp, CP0_CONTEXT
113 #endif
114 LONG_SRL \temp, PTEBASE_SHIFT
115 LONG_S \stackp, kernelsp(\temp)
116 .endm
117 #else
118 .macro get_saved_sp /* Uniprocessor variation */
119 #if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4)
120 lui k1, %highest(kernelsp)
121 daddiu k1, %higher(kernelsp)
122 dsll k1, k1, 16
123 daddiu k1, %hi(kernelsp)
124 dsll k1, k1, 16
125 #else
126 lui k1, %hi(kernelsp)
127 #endif
128 LONG_L k1, %lo(kernelsp)(k1)
129 .endm
130
131 .macro set_saved_sp stackp temp temp2
132 LONG_S \stackp, kernelsp
133 .endm
134 #endif
135
136 .macro SAVE_SOME
137 .set push
138 .set noat
139 .set reorder
140 mfc0 k0, CP0_STATUS
141 sll k0, 3 /* extract cu0 bit */
142 .set noreorder
143 bltz k0, 8f
144 move k1, sp
145 .set reorder
146 /* Called from user mode, new stack. */
147 get_saved_sp
148 8: move k0, sp
149 PTR_SUBU sp, k1, PT_SIZE
150 LONG_S k0, PT_R29(sp)
151 LONG_S $3, PT_R3(sp)
152 /*
153 * You might think that you don't need to save $0,
154 * but the FPU emulator and gdb remote debug stub
155 * need it to operate correctly
156 */
157 LONG_S $0, PT_R0(sp)
158 mfc0 v1, CP0_STATUS
159 LONG_S $2, PT_R2(sp)
160 LONG_S v1, PT_STATUS(sp)
161 #ifdef CONFIG_MIPS_MT_SMTC
162 /*
163 * Ideally, these instructions would be shuffled in
164 * to cover the pipeline delay.
165 */
166 .set mips32
167 mfc0 v1, CP0_TCSTATUS
168 .set mips0
169 LONG_S v1, PT_TCSTATUS(sp)
170 #endif /* CONFIG_MIPS_MT_SMTC */
171 LONG_S $4, PT_R4(sp)
172 mfc0 v1, CP0_CAUSE
173 LONG_S $5, PT_R5(sp)
174 LONG_S v1, PT_CAUSE(sp)
175 LONG_S $6, PT_R6(sp)
176 MFC0 v1, CP0_EPC
177 LONG_S $7, PT_R7(sp)
178 #ifdef CONFIG_64BIT
179 LONG_S $8, PT_R8(sp)
180 LONG_S $9, PT_R9(sp)
181 #endif
182 LONG_S v1, PT_EPC(sp)
183 LONG_S $25, PT_R25(sp)
184 LONG_S $28, PT_R28(sp)
185 LONG_S $31, PT_R31(sp)
186 ori $28, sp, _THREAD_MASK
187 xori $28, _THREAD_MASK
188 .set pop
189 .endm
190
191 .macro SAVE_ALL
192 SAVE_SOME
193 SAVE_AT
194 SAVE_TEMP
195 SAVE_STATIC
196 .endm
197
198 .macro RESTORE_AT
199 .set push
200 .set noat
201 LONG_L $1, PT_R1(sp)
202 .set pop
203 .endm
204
205 .macro RESTORE_TEMP
206 #ifdef CONFIG_CPU_HAS_SMARTMIPS
207 LONG_L $24, PT_ACX(sp)
208 mtlhx $24
209 LONG_L $24, PT_HI(sp)
210 mtlhx $24
211 LONG_L $24, PT_LO(sp)
212 mtlhx $24
213 #else
214 LONG_L $24, PT_LO(sp)
215 mtlo $24
216 LONG_L $24, PT_HI(sp)
217 mthi $24
218 #endif
219 #ifdef CONFIG_32BIT
220 LONG_L $8, PT_R8(sp)
221 LONG_L $9, PT_R9(sp)
222 #endif
223 LONG_L $10, PT_R10(sp)
224 LONG_L $11, PT_R11(sp)
225 LONG_L $12, PT_R12(sp)
226 LONG_L $13, PT_R13(sp)
227 LONG_L $14, PT_R14(sp)
228 LONG_L $15, PT_R15(sp)
229 LONG_L $24, PT_R24(sp)
230 .endm
231
232 .macro RESTORE_STATIC
233 LONG_L $16, PT_R16(sp)
234 LONG_L $17, PT_R17(sp)
235 LONG_L $18, PT_R18(sp)
236 LONG_L $19, PT_R19(sp)
237 LONG_L $20, PT_R20(sp)
238 LONG_L $21, PT_R21(sp)
239 LONG_L $22, PT_R22(sp)
240 LONG_L $23, PT_R23(sp)
241 LONG_L $30, PT_R30(sp)
242 .endm
243
244 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
245
246 .macro RESTORE_SOME
247 .set push
248 .set reorder
249 .set noat
250 mfc0 a0, CP0_STATUS
251 li v1, 0xff00
252 ori a0, STATMASK
253 xori a0, STATMASK
254 mtc0 a0, CP0_STATUS
255 and a0, v1
256 LONG_L v0, PT_STATUS(sp)
257 nor v1, $0, v1
258 and v0, v1
259 or v0, a0
260 mtc0 v0, CP0_STATUS
261 LONG_L $31, PT_R31(sp)
262 LONG_L $28, PT_R28(sp)
263 LONG_L $25, PT_R25(sp)
264 LONG_L $7, PT_R7(sp)
265 LONG_L $6, PT_R6(sp)
266 LONG_L $5, PT_R5(sp)
267 LONG_L $4, PT_R4(sp)
268 LONG_L $3, PT_R3(sp)
269 LONG_L $2, PT_R2(sp)
270 .set pop
271 .endm
272
273 .macro RESTORE_SP_AND_RET
274 .set push
275 .set noreorder
276 LONG_L k0, PT_EPC(sp)
277 LONG_L sp, PT_R29(sp)
278 jr k0
279 rfe
280 .set pop
281 .endm
282
283 #else
284 .macro RESTORE_SOME
285 .set push
286 .set reorder
287 .set noat
288 #ifdef CONFIG_MIPS_MT_SMTC
289 .set mips32r2
290 /*
291 * We need to make sure the read-modify-write
292 * of Status below isn't perturbed by an interrupt
293 * or cross-TC access, so we need to do at least a DMT,
294 * protected by an interrupt-inhibit. But setting IXMT
295 * also creates a few-cycle window where an IPI could
296 * be queued and not be detected before potentially
297 * returning to a WAIT or user-mode loop. It must be
298 * replayed.
299 *
300 * We're in the middle of a context switch, and
301 * we can't dispatch it directly without trashing
302 * some registers, so we'll try to detect this unlikely
303 * case and program a software interrupt in the VPE,
304 * as would be done for a cross-VPE IPI. To accomodate
305 * the handling of that case, we're doing a DVPE instead
306 * of just a DMT here to protect against other threads.
307 * This is a lot of cruft to cover a tiny window.
308 * If you can find a better design, implement it!
309 *
310 */
311 mfc0 v0, CP0_TCSTATUS
312 ori v0, TCSTATUS_IXMT
313 mtc0 v0, CP0_TCSTATUS
314 _ehb
315 DVPE 5 # dvpe a1
316 jal mips_ihb
317 #endif /* CONFIG_MIPS_MT_SMTC */
318 mfc0 a0, CP0_STATUS
319 ori a0, STATMASK
320 xori a0, STATMASK
321 mtc0 a0, CP0_STATUS
322 li v1, 0xff00
323 and a0, v1
324 LONG_L v0, PT_STATUS(sp)
325 nor v1, $0, v1
326 and v0, v1
327 or v0, a0
328 mtc0 v0, CP0_STATUS
329 #ifdef CONFIG_MIPS_MT_SMTC
330 /*
331 * Only after EXL/ERL have been restored to status can we
332 * restore TCStatus.IXMT.
333 */
334 LONG_L v1, PT_TCSTATUS(sp)
335 _ehb
336 mfc0 a0, CP0_TCSTATUS
337 andi v1, TCSTATUS_IXMT
338 bnez v1, 0f
339
340 /*
341 * We'd like to detect any IPIs queued in the tiny window
342 * above and request an software interrupt to service them
343 * when we ERET.
344 *
345 * Computing the offset into the IPIQ array of the executing
346 * TC's IPI queue in-line would be tedious. We use part of
347 * the TCContext register to hold 16 bits of offset that we
348 * can add in-line to find the queue head.
349 */
350 mfc0 v0, CP0_TCCONTEXT
351 la a2, IPIQ
352 srl v0, v0, 16
353 addu a2, a2, v0
354 LONG_L v0, 0(a2)
355 beqz v0, 0f
356 /*
357 * If we have a queue, provoke dispatch within the VPE by setting C_SW1
358 */
359 mfc0 v0, CP0_CAUSE
360 ori v0, v0, C_SW1
361 mtc0 v0, CP0_CAUSE
362 0:
363 /*
364 * This test should really never branch but
365 * let's be prudent here. Having atomized
366 * the shared register modifications, we can
367 * now EVPE, and must do so before interrupts
368 * are potentially re-enabled.
369 */
370 andi a1, a1, MVPCONTROL_EVP
371 beqz a1, 1f
372 evpe
373 1:
374 /* We know that TCStatua.IXMT should be set from above */
375 xori a0, a0, TCSTATUS_IXMT
376 or a0, a0, v1
377 mtc0 a0, CP0_TCSTATUS
378 _ehb
379
380 .set mips0
381 #endif /* CONFIG_MIPS_MT_SMTC */
382 LONG_L v1, PT_EPC(sp)
383 MTC0 v1, CP0_EPC
384 LONG_L $31, PT_R31(sp)
385 LONG_L $28, PT_R28(sp)
386 LONG_L $25, PT_R25(sp)
387 #ifdef CONFIG_64BIT
388 LONG_L $8, PT_R8(sp)
389 LONG_L $9, PT_R9(sp)
390 #endif
391 LONG_L $7, PT_R7(sp)
392 LONG_L $6, PT_R6(sp)
393 LONG_L $5, PT_R5(sp)
394 LONG_L $4, PT_R4(sp)
395 LONG_L $3, PT_R3(sp)
396 LONG_L $2, PT_R2(sp)
397 .set pop
398 .endm
399
400 .macro RESTORE_SP_AND_RET
401 LONG_L sp, PT_R29(sp)
402 .set mips3
403 #ifdef CONFIG_BCM47XX
404 nop
405 nop
406 #endif /* CONFIG_BCM47XX */
407 eret
408 .set mips0
409 .endm
410
411 #endif
412
413 .macro RESTORE_SP
414 LONG_L sp, PT_R29(sp)
415 .endm
416
417 .macro RESTORE_ALL
418 RESTORE_TEMP
419 RESTORE_STATIC
420 RESTORE_AT
421 RESTORE_SOME
422 RESTORE_SP
423 .endm
424
425 .macro RESTORE_ALL_AND_RET
426 RESTORE_TEMP
427 RESTORE_STATIC
428 RESTORE_AT
429 RESTORE_SOME
430 RESTORE_SP_AND_RET
431 .endm
432
433 /*
434 * Move to kernel mode and disable interrupts.
435 * Set cp0 enable bit as sign that we're running on the kernel stack
436 */
437 .macro CLI
438 #if !defined(CONFIG_MIPS_MT_SMTC)
439 mfc0 t0, CP0_STATUS
440 li t1, ST0_CU0 | STATMASK
441 or t0, t1
442 xori t0, STATMASK
443 mtc0 t0, CP0_STATUS
444 #else /* CONFIG_MIPS_MT_SMTC */
445 /*
446 * For SMTC, we need to set privilege
447 * and disable interrupts only for the
448 * current TC, using the TCStatus register.
449 */
450 mfc0 t0,CP0_TCSTATUS
451 /* Fortunately CU 0 is in the same place in both registers */
452 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
453 li t1, ST0_CU0 | 0x08001c00
454 or t0,t1
455 /* Clear TKSU, leave IXMT */
456 xori t0, 0x00001800
457 mtc0 t0, CP0_TCSTATUS
458 _ehb
459 /* We need to leave the global IE bit set, but clear EXL...*/
460 mfc0 t0, CP0_STATUS
461 ori t0, ST0_EXL | ST0_ERL
462 xori t0, ST0_EXL | ST0_ERL
463 mtc0 t0, CP0_STATUS
464 #endif /* CONFIG_MIPS_MT_SMTC */
465 irq_disable_hazard
466 .endm
467
468 /*
469 * Move to kernel mode and enable interrupts.
470 * Set cp0 enable bit as sign that we're running on the kernel stack
471 */
472 .macro STI
473 #if !defined(CONFIG_MIPS_MT_SMTC)
474 mfc0 t0, CP0_STATUS
475 li t1, ST0_CU0 | STATMASK
476 or t0, t1
477 xori t0, STATMASK & ~1
478 mtc0 t0, CP0_STATUS
479 #else /* CONFIG_MIPS_MT_SMTC */
480 /*
481 * For SMTC, we need to set privilege
482 * and enable interrupts only for the
483 * current TC, using the TCStatus register.
484 */
485 _ehb
486 mfc0 t0,CP0_TCSTATUS
487 /* Fortunately CU 0 is in the same place in both registers */
488 /* Set TCU0, TKSU (for later inversion) and IXMT */
489 li t1, ST0_CU0 | 0x08001c00
490 or t0,t1
491 /* Clear TKSU *and* IXMT */
492 xori t0, 0x00001c00
493 mtc0 t0, CP0_TCSTATUS
494 _ehb
495 /* We need to leave the global IE bit set, but clear EXL...*/
496 mfc0 t0, CP0_STATUS
497 ori t0, ST0_EXL
498 xori t0, ST0_EXL
499 mtc0 t0, CP0_STATUS
500 /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
501 #endif /* CONFIG_MIPS_MT_SMTC */
502 irq_enable_hazard
503 .endm
504
505 /*
506 * Just move to kernel mode and leave interrupts as they are. Note
507 * for the R3000 this means copying the previous enable from IEp.
508 * Set cp0 enable bit as sign that we're running on the kernel stack
509 */
510 .macro KMODE
511 #ifdef CONFIG_MIPS_MT_SMTC
512 /*
513 * This gets baroque in SMTC. We want to
514 * protect the non-atomic clearing of EXL
515 * with DMT/EMT, but we don't want to take
516 * an interrupt while DMT is still in effect.
517 */
518
519 /* KMODE gets invoked from both reorder and noreorder code */
520 .set push
521 .set mips32r2
522 .set noreorder
523 mfc0 v0, CP0_TCSTATUS
524 andi v1, v0, TCSTATUS_IXMT
525 ori v0, TCSTATUS_IXMT
526 mtc0 v0, CP0_TCSTATUS
527 _ehb
528 DMT 2 # dmt v0
529 /*
530 * We don't know a priori if ra is "live"
531 */
532 move t0, ra
533 jal mips_ihb
534 nop /* delay slot */
535 move ra, t0
536 #endif /* CONFIG_MIPS_MT_SMTC */
537 mfc0 t0, CP0_STATUS
538 li t1, ST0_CU0 | (STATMASK & ~1)
539 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
540 andi t2, t0, ST0_IEP
541 srl t2, 2
542 or t0, t2
543 #endif
544 or t0, t1
545 xori t0, STATMASK & ~1
546 mtc0 t0, CP0_STATUS
547 #ifdef CONFIG_MIPS_MT_SMTC
548 _ehb
549 andi v0, v0, VPECONTROL_TE
550 beqz v0, 2f
551 nop /* delay slot */
552 emt
553 2:
554 mfc0 v0, CP0_TCSTATUS
555 /* Clear IXMT, then OR in previous value */
556 ori v0, TCSTATUS_IXMT
557 xori v0, TCSTATUS_IXMT
558 or v0, v1, v0
559 mtc0 v0, CP0_TCSTATUS
560 /*
561 * irq_disable_hazard below should expand to EHB
562 * on 24K/34K CPUS
563 */
564 .set pop
565 #endif /* CONFIG_MIPS_MT_SMTC */
566 irq_disable_hazard
567 .endm
568
569 #endif /* _ASM_STACKFRAME_H */
Tomato firmware and modifications.