2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com>
15 #include <linux/compiler.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
19 #include <asm/addrspace.h>
20 #include <asm/byteorder.h>
22 #include <asm/cpu-features.h>
23 #include <asm-generic/iomap.h>
25 #include <asm/pgtable-bits.h>
26 #include <asm/processor.h>
27 #include <asm/string.h>
30 #include <mangle-port.h>
33 * Slowdown I/O port space accesses for antique hardware.
35 #undef CONF_SLOWDOWN_IO
38 * Raw operations are never swapped in software. OTOH values that raw
39 * operations are working on may or may not have been swapped by the bus
40 * hardware. An example use would be for flash memory that's used for
43 # define __raw_ioswabb(a,x) (x)
44 # define __raw_ioswabw(a,x) (x)
45 # define __raw_ioswabl(a,x) (x)
46 # define __raw_ioswabq(a,x) (x)
47 # define ____raw_ioswabq(a,x) (x)
49 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
51 #define IO_SPACE_LIMIT 0xffff
54 * On MIPS I/O ports are memory mapped, so we access them using normal
55 * load/store instructions. mips_io_port_base is the virtual address to
56 * which all ports are being mapped. For sake of efficiency some code
57 * assumes that this is an address that can be loaded with a single lui
58 * instruction, so the lower 16 bits must be zero. Should be true on
59 * on any sane architecture; generic code does not use this assumption.
61 extern const unsigned long mips_io_port_base
;
64 * Gcc will generate code to load the value of mips_io_port_base after each
65 * function call which may be fairly wasteful in some cases. So we don't
66 * play quite by the book. We tell gcc mips_io_port_base is a long variable
67 * which solves the code generation issue. Now we need to violate the
68 * aliasing rules a little to make initialization possible and finally we
69 * will need the barrier() to fight side effects of the aliasing chat.
70 * This trickery will eventually collapse under gcc's optimizer. Oh well.
72 static inline void set_io_port_base(unsigned long base
)
74 * (unsigned long *) &mips_io_port_base
= base
;
79 * Thanks to James van Artsdalen for a better timing-fix than
80 * the two short jumps: using outb's to a nonexistent port seems
81 * to guarantee better timings even on fast machines.
83 * On the other hand, I'd like to be sure of a non-existent port:
84 * I feel a bit unsafe about using 0x80 (should be safe, though)
90 #define __SLOW_DOWN_IO \
91 __asm__ __volatile__( \
93 : : "r" (mips_io_port_base));
95 #ifdef CONF_SLOWDOWN_IO
97 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
99 #define SLOW_DOWN_IO __SLOW_DOWN_IO
106 * virt_to_phys - map virtual addresses to physical
107 * @address: address to remap
109 * The returned physical address is the physical (CPU) mapping for
110 * the memory address given. It is only valid to use this function on
111 * addresses directly mapped or allocated via kmalloc.
113 * This function does not give bus mappings for DMA transfers. In
114 * almost all conceivable cases a device driver should not be using
117 static inline unsigned long virt_to_phys(volatile const void *address
)
119 return (unsigned long)address
- PAGE_OFFSET
+ PHYS_OFFSET
;
123 * phys_to_virt - map physical address to virtual
124 * @address: address to remap
126 * The returned virtual address is a current CPU mapping for
127 * the memory address given. It is only valid to use this function on
128 * addresses that have a kernel mapping
130 * This function does not handle bus mappings for DMA transfers. In
131 * almost all conceivable cases a device driver should not be using
134 static inline void * phys_to_virt(unsigned long address
)
136 return (void *)(address
+ PAGE_OFFSET
- PHYS_OFFSET
);
140 * ISA I/O bus memory addresses are 1:1 with the physical address.
142 static inline unsigned long isa_virt_to_bus(volatile void * address
)
144 return (unsigned long)address
- PAGE_OFFSET
;
147 static inline void * isa_bus_to_virt(unsigned long address
)
149 return (void *)(address
+ PAGE_OFFSET
);
152 #define isa_page_to_bus page_to_phys
155 * However PCI ones are not necessarily 1:1 and therefore these interfaces
156 * are forbidden in portable PCI drivers.
158 * Allow them for x86 for legacy drivers, though.
160 #define virt_to_bus virt_to_phys
161 #define bus_to_virt phys_to_virt
164 * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
165 * for the processor. This implies the assumption that there is only
166 * one of these busses.
168 extern unsigned long isa_slot_offset
;
171 * Change "struct page" to physical address.
173 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
175 extern void __iomem
* __ioremap(phys_t offset
, phys_t size
, unsigned long flags
);
176 extern void __iounmap(const volatile void __iomem
*addr
);
178 static inline void __iomem
* __ioremap_mode(phys_t offset
, unsigned long size
,
181 #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
183 if (cpu_has_64bit_addresses
) {
184 u64 base
= UNCAC_BASE
;
187 * R10000 supports a 2 bit uncached attribute therefore
188 * UNCAC_BASE may not equal IO_BASE.
190 if (flags
== _CACHE_UNCACHED
)
191 base
= (u64
) IO_BASE
;
192 return (void __iomem
*) (unsigned long) (base
+ offset
);
193 } else if (__builtin_constant_p(offset
) &&
194 __builtin_constant_p(size
) && __builtin_constant_p(flags
)) {
195 phys_t phys_addr
, last_addr
;
197 phys_addr
= fixup_bigphys_addr(offset
, size
);
199 /* Don't allow wraparound or zero size. */
200 last_addr
= phys_addr
+ size
- 1;
201 if (!size
|| last_addr
< phys_addr
)
205 * Map uncached objects in the low 512MB of address
208 if (__IS_LOW512(phys_addr
) && __IS_LOW512(last_addr
) &&
209 flags
== _CACHE_UNCACHED
)
210 return (void __iomem
*)CKSEG1ADDR(phys_addr
);
213 return __ioremap(offset
, size
, flags
);
219 * ioremap - map bus memory into CPU space
220 * @offset: bus address of the memory
221 * @size: size of the resource to map
223 * ioremap performs a platform specific sequence of operations to
224 * make bus memory CPU accessible via the readb/readw/readl/writeb/
225 * writew/writel functions and the other mmio helpers. The returned
226 * address is not guaranteed to be usable directly as a virtual
229 #define ioremap(offset, size) \
230 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
233 * ioremap_nocache - map bus memory into CPU space
234 * @offset: bus address of the memory
235 * @size: size of the resource to map
237 * ioremap_nocache performs a platform specific sequence of operations to
238 * make bus memory CPU accessible via the readb/readw/readl/writeb/
239 * writew/writel functions and the other mmio helpers. The returned
240 * address is not guaranteed to be usable directly as a virtual
243 * This version of ioremap ensures that the memory is marked uncachable
244 * on the CPU as well as honouring existing caching rules from things like
245 * the PCI bus. Note that there are other caches and buffers on many
246 * busses. In paticular driver authors should read up on PCI writes
248 * It's useful if some control registers are in such an area and
249 * write combining or read caching is not desirable:
251 #define ioremap_nocache(offset, size) \
252 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
255 * ioremap_cachable - map bus memory into CPU space
256 * @offset: bus address of the memory
257 * @size: size of the resource to map
259 * ioremap_nocache performs a platform specific sequence of operations to
260 * make bus memory CPU accessible via the readb/readw/readl/writeb/
261 * writew/writel functions and the other mmio helpers. The returned
262 * address is not guaranteed to be usable directly as a virtual
265 * This version of ioremap ensures that the memory is marked cachable by
266 * the CPU. Also enables full write-combining. Useful for some
267 * memory-like regions on I/O busses.
269 #define ioremap_cachable(offset, size) \
270 __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)
273 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
274 * requests a cachable mapping, ioremap_uncached_accelerated requests a
275 * mapping using the uncached accelerated mode which isn't supported on
278 #define ioremap_cacheable_cow(offset, size) \
279 __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
280 #define ioremap_uncached_accelerated(offset, size) \
281 __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
283 static inline void iounmap(const volatile void __iomem
*addr
)
285 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
287 if (cpu_has_64bit_addresses
||
288 (__builtin_constant_p(addr
) && __IS_KSEG1(addr
)))
296 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
298 static inline void pfx##write##bwlq(type val, \
299 volatile void __iomem *mem) \
301 volatile type *__mem; \
304 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
306 __val = pfx##ioswab##bwlq(__mem, val); \
308 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
310 else if (cpu_has_64bits) { \
311 unsigned long __flags; \
315 local_irq_save(__flags); \
316 __asm__ __volatile__( \
317 ".set mips3" "\t\t# __writeq""\n\t" \
318 "dsll32 %L0, %L0, 0" "\n\t" \
319 "dsrl32 %L0, %L0, 0" "\n\t" \
320 "dsll32 %M0, %M0, 0" "\n\t" \
321 "or %L0, %L0, %M0" "\n\t" \
323 ".set noreorder" "\n\t" \
324 ".set nomacro" "\n\t" \
325 "sd %L0, %2" "\n\t" \
329 : "0" (__val), "R" (*__mem)); \
331 local_irq_restore(__flags); \
336 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
338 volatile type *__mem; \
341 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
343 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
345 else if (cpu_has_64bits) { \
346 unsigned long __flags; \
349 local_irq_save(__flags); \
350 __asm__ __volatile__( \
351 ".set mips3" "\t\t# __readq" "\n\t" \
353 ".set noreorder" "\n\t" \
354 ".set nomacro" "\n\t" \
355 "ld %L0, %1" "\n\t" \
357 "dsra32 %M0, %L0, 0" "\n\t" \
358 "sll %L0, %L0, 0" "\n\t" \
363 local_irq_restore(__flags); \
369 return pfx##ioswab##bwlq(__mem, __val); \
372 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
374 static inline void pfx##out##bwlq##p(type val, unsigned long port) \
376 volatile type *__addr; \
379 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
381 __val = pfx##ioswab##bwlq(__addr, val); \
383 /* Really, we want this to be atomic */ \
384 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
390 static inline type pfx##in##bwlq##p(unsigned long port) \
392 volatile type *__addr; \
395 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
397 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
402 return pfx##ioswab##bwlq(__addr, __val); \
405 #define __BUILD_MEMORY_PFX(bus, bwlq, type) \
407 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
409 #define BUILDIO_MEM(bwlq, type) \
411 __BUILD_MEMORY_PFX(__raw_, bwlq, type) \
412 __BUILD_MEMORY_PFX(, bwlq, type) \
413 __BUILD_MEMORY_PFX(__mem_, bwlq, type) \
420 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \
421 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
422 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
424 #define BUILDIO_IOPORT(bwlq, type) \
425 __BUILD_IOPORT_PFX(, bwlq, type) \
426 __BUILD_IOPORT_PFX(__mem_, bwlq, type)
428 BUILDIO_IOPORT(b
, u8
)
429 BUILDIO_IOPORT(w
, u16
)
430 BUILDIO_IOPORT(l
, u32
)
432 BUILDIO_IOPORT(q
, u64
)
435 #define __BUILDIO(bwlq, type) \
437 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
441 #define readb_relaxed readb
442 #define readw_relaxed readw
443 #define readl_relaxed readl
444 #define readq_relaxed readq
447 * Some code tests for these symbols
450 #define writeq writeq
452 #define __BUILD_MEMORY_STRING(bwlq, type) \
454 static inline void writes##bwlq(volatile void __iomem *mem, \
455 const void *addr, unsigned int count) \
457 const volatile type *__addr = addr; \
460 __mem_write##bwlq(*__addr, mem); \
465 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
466 unsigned int count) \
468 volatile type *__addr = addr; \
471 *__addr = __mem_read##bwlq(mem); \
476 #define __BUILD_IOPORT_STRING(bwlq, type) \
478 static inline void outs##bwlq(unsigned long port, const void *addr, \
479 unsigned int count) \
481 const volatile type *__addr = addr; \
484 __mem_out##bwlq(*__addr, port); \
489 static inline void ins##bwlq(unsigned long port, void *addr, \
490 unsigned int count) \
492 volatile type *__addr = addr; \
495 *__addr = __mem_in##bwlq(port); \
500 #define BUILDSTRING(bwlq, type) \
502 __BUILD_MEMORY_STRING(bwlq, type) \
503 __BUILD_IOPORT_STRING(bwlq, type)
513 /* Depends on MIPS II instruction set */
514 #define mmiowb() asm volatile ("sync" ::: "memory")
516 static inline void memset_io(volatile void __iomem
*addr
, unsigned char val
, int count
)
518 memset((void __force
*) addr
, val
, count
);
520 static inline void memcpy_fromio(void *dst
, const volatile void __iomem
*src
, int count
)
522 memcpy(dst
, (void __force
*) src
, count
);
524 static inline void memcpy_toio(volatile void __iomem
*dst
, const void *src
, int count
)
526 memcpy((void __force
*) dst
, src
, count
);
530 * ISA space is 'always mapped' on currently supported MIPS systems, no need
531 * to explicitly ioremap() it. The fact that the ISA IO space is mapped
532 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
533 * are physical addresses. The following constant pointer can be
534 * used as the IO-area pointer (it can be iounmapped as well, so the
535 * analogy with PCI is quite large):
537 #define __ISA_IO_base ((char *)(isa_slot_offset))
540 * The caches on some architectures aren't dma-coherent and have need to
541 * handle this in software. There are three types of operations that
542 * can be applied to dma buffers.
544 * - dma_cache_wback_inv(start, size) makes caches and coherent by
545 * writing the content of the caches back to memory, if necessary.
546 * The function also invalidates the affected part of the caches as
547 * necessary before DMA transfers from outside to memory.
548 * - dma_cache_wback(start, size) makes caches and coherent by
549 * writing the content of the caches back to memory, if necessary.
550 * The function also invalidates the affected part of the caches as
551 * necessary before DMA transfers from outside to memory.
552 * - dma_cache_inv(start, size) invalidates the affected parts of the
553 * caches. Dirty lines of the caches may be written back or simply
554 * be discarded. This operation is necessary before dma operations
557 #ifdef CONFIG_DMA_NONCOHERENT
559 extern void (*_dma_cache_wback_inv
)(unsigned long start
, unsigned long size
);
560 extern void (*_dma_cache_wback
)(unsigned long start
, unsigned long size
);
561 extern void (*_dma_cache_inv
)(unsigned long start
, unsigned long size
);
563 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size)
564 #define dma_cache_wback(start, size) _dma_cache_wback(start,size)
565 #define dma_cache_inv(start, size) _dma_cache_inv(start,size)
567 #else /* Sane hardware */
569 #define dma_cache_wback_inv(start,size) \
570 do { (void) (start); (void) (size); } while (0)
571 #define dma_cache_wback(start,size) \
572 do { (void) (start); (void) (size); } while (0)
573 #define dma_cache_inv(start,size) \
574 do { (void) (start); (void) (size); } while (0)
576 #endif /* CONFIG_DMA_NONCOHERENT */
579 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
580 * Avoid interrupt mucking, just adjust the address for 4-byte access.
581 * Assume the addresses are 8-byte aligned.
584 #define __CSR_32_ADJUST 4
586 #define __CSR_32_ADJUST 0
589 #define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
590 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
593 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
596 #define xlate_dev_mem_ptr(p) __va(p)
599 * Convert a virtual cached pointer to an uncached pointer
601 #define xlate_dev_kmem_ptr(p) p
603 #endif /* _ASM_IO_H */