2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) MIPS Technologies, Inc.
8 * written by Ralf Baechle <ralf@linux-mips.org>
10 #ifndef _ASM_HAZARDS_H
11 #define _ASM_HAZARDS_H
15 #define ASMMACRO(name, code...) .macro name; code; .endm
18 #include <asm/cpu-features.h>
20 #define ASMMACRO(name, code...) \
21 __asm__(".macro " #name "; " #code "; .endm"); \
23 static inline void name(void) \
25 __asm__ __volatile__ (#name); \
41 #if defined(CONFIG_CPU_MIPSR2)
44 * MIPSR2 defines ehb for hazard avoidance
47 ASMMACRO(mtc0_tlbw_hazard
,
50 ASMMACRO(tlbw_use_hazard
,
53 ASMMACRO(tlb_probe_hazard
,
56 ASMMACRO(irq_enable_hazard
,
59 ASMMACRO(irq_disable_hazard
,
62 ASMMACRO(back_to_back_c0_hazard
,
66 * gcc has a tradition of misscompiling the previous construct using the
67 * address of a label as argument to inline assembler. Gas otoh has the
68 * annoying difference between la and dla which are only usable for 32-bit
69 * rsp. 64-bit code, so can't be used without conditional compilation.
70 * The alterantive is switching the assembler to 64-bit code which happens
71 * to work right even for 32-bit code ...
73 #define instruction_hazard() \
77 __asm__ __volatile__( \
86 #elif defined(CONFIG_CPU_MIPSR1)
89 * These are slightly complicated by the fact that we guarantee R1 kernels to
90 * run fine on R2 processors.
92 ASMMACRO(mtc0_tlbw_hazard
,
95 ASMMACRO(tlbw_use_hazard
,
96 _ssnop
; _ssnop
; _ssnop
; _ehb
98 ASMMACRO(tlb_probe_hazard
,
99 _ssnop
; _ssnop
; _ssnop
; _ehb
101 ASMMACRO(irq_enable_hazard
,
102 _ssnop
; _ssnop
; _ssnop
; _ehb
104 ASMMACRO(irq_disable_hazard
,
105 _ssnop
; _ssnop
; _ssnop
; _ehb
107 ASMMACRO(back_to_back_c0_hazard
,
108 _ssnop
; _ssnop
; _ssnop
; _ehb
111 * gcc has a tradition of misscompiling the previous construct using the
112 * address of a label as argument to inline assembler. Gas otoh has the
113 * annoying difference between la and dla which are only usable for 32-bit
114 * rsp. 64-bit code, so can't be used without conditional compilation.
115 * The alterantive is switching the assembler to 64-bit code which happens
116 * to work right even for 32-bit code ...
118 #define __instruction_hazard() \
122 __asm__ __volatile__( \
123 " .set mips64r2 \n" \
131 #define instruction_hazard() \
133 if (cpu_has_mips_r2) \
134 __instruction_hazard(); \
137 #elif defined(CONFIG_CPU_R10000)
140 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
143 ASMMACRO(mtc0_tlbw_hazard
,
145 ASMMACRO(tlbw_use_hazard
,
147 ASMMACRO(tlb_probe_hazard
,
149 ASMMACRO(irq_enable_hazard
,
151 ASMMACRO(irq_disable_hazard
,
153 ASMMACRO(back_to_back_c0_hazard
,
155 #define instruction_hazard() do { } while (0)
157 #elif defined(CONFIG_CPU_RM9000)
160 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
161 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
162 * for data translations should not occur for 3 cpu cycles.
165 ASMMACRO(mtc0_tlbw_hazard
,
166 _ssnop
; _ssnop
; _ssnop
; _ssnop
168 ASMMACRO(tlbw_use_hazard
,
169 _ssnop
; _ssnop
; _ssnop
; _ssnop
171 ASMMACRO(tlb_probe_hazard
,
172 _ssnop
; _ssnop
; _ssnop
; _ssnop
174 ASMMACRO(irq_enable_hazard
,
176 ASMMACRO(irq_disable_hazard
,
178 ASMMACRO(back_to_back_c0_hazard
,
180 #define instruction_hazard() do { } while (0)
182 #elif defined(CONFIG_CPU_SB1)
185 * Mostly like R4000 for historic reasons
187 ASMMACRO(mtc0_tlbw_hazard
,
189 ASMMACRO(tlbw_use_hazard
,
191 ASMMACRO(tlb_probe_hazard
,
193 ASMMACRO(irq_enable_hazard
,
195 ASMMACRO(irq_disable_hazard
,
196 _ssnop
; _ssnop
; _ssnop
198 ASMMACRO(back_to_back_c0_hazard
,
200 #define instruction_hazard() do { } while (0)
205 * Finally the catchall case for all other processors including R4000, R4400,
206 * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
208 * The taken branch will result in a two cycle penalty for the two killed
209 * instructions on R4000 / R4400. Other processors only have a single cycle
210 * hazard so this is nice trick to have an optimal code for a range of
212 * Make it compatible with Mips32r2 processors
214 ASMMACRO(mtc0_tlbw_hazard
,
217 ASMMACRO(tlbw_use_hazard
,
220 ASMMACRO(tlb_probe_hazard
,
223 ASMMACRO(irq_enable_hazard
,
226 ASMMACRO(irq_disable_hazard
,
229 ASMMACRO(back_to_back_c0_hazard
,
230 _ssnop
; _ssnop
; _ssnop
; _ehb
232 #define instruction_hazard() do { } while (0)
239 #if defined(CONFIG_CPU_SB1)
240 ASMMACRO(enable_fpu_hazard
,
249 ASMMACRO(disable_fpu_hazard
,
252 #elif defined(CONFIG_CPU_MIPSR2)
253 ASMMACRO(enable_fpu_hazard
,
256 ASMMACRO(disable_fpu_hazard
,
260 ASMMACRO(enable_fpu_hazard
,
261 nop
; nop
; nop
; nop
; _ehb
263 ASMMACRO(disable_fpu_hazard
,
268 #endif /* _ASM_HAZARDS_H */