release/src-rt-6.x/linux/linux-2.6/include/asm-mips/ddb5xxx/ddb5477.h

   1 /***********************************************************************
   2  *
   3  * Copyright 2001 MontaVista Software Inc.
   4  * Author: jsun@mvista.com or jsun@junsun.net
   5  *
   6  * include/asm-mips/ddb5xxx/ddb5477.h
   7  *     DDB 5477 specific definitions and macros.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  *
  14  ***********************************************************************
  15  */
  16
  17 #ifndef __ASM_DDB5XXX_DDB5477_H
  18 #define __ASM_DDB5XXX_DDB5477_H
  19
  20 #include <irq.h>
  21
  22 /*
  23  * This contains macros that are specific to DDB5477 or renamed from
  24  * DDB5476.
  25  */
  26
  27 /*
  28  * renamed PADRs
  29  */
  30 #define DDB_LCS0        DDB_DCS2
  31 #define DDB_LCS1        DDB_DCS3
  32 #define DDB_LCS2        DDB_DCS4
  33 #define DDB_VRC5477     DDB_INTCS
  34
  35 /*
  36  * New CPU interface registers
  37  */
  38 #define DDB_INTCTRL0    0x0400  /* Interrupt Control 0 */
  39 #define DDB_INTCTRL1    0x0404  /* Interrupt Control 1 */
  40 #define DDB_INTCTRL2    0x0408  /* Interrupt Control 2 */
  41 #define DDB_INTCTRL3    0x040c  /* Interrupt Control 3 */
  42
  43 #define DDB_INT0STAT    0x0420  /* INT0 Status [R] */
  44 #define DDB_INT1STAT    0x0428  /* INT1 Status [R] */
  45 #define DDB_INT2STAT    0x0430  /* INT2 Status [R] */
  46 #define DDB_INT3STAT    0x0438  /* INT3 Status [R] */
  47 #define DDB_INT4STAT    0x0440  /* INT4 Status [R] */
  48 #define DDB_NMISTAT     0x0450  /* NMI Status [R] */
  49
  50 #define DDB_INTCLR32    0x0468  /* Interrupt Clear */
  51
  52 #define DDB_INTPPES0    0x0470  /* PCI0 Interrupt Control */
  53 #define DDB_INTPPES1    0x0478  /* PCI1 Interrupt Control */
  54
  55 #undef  DDB_CPUSTAT             /* duplicate in Vrc-5477 */
  56 #define DDB_CPUSTAT     0x0480  /* CPU Status [R] */
  57 #define DDB_BUSCTRL     0x0488  /* Internal Bus Control */
  58
  59
  60 /*
  61  * Timer registers
  62  */
  63 #define DDB_REFCTRL_L   DDB_T0CTRL
  64 #define DDB_REFCTRL_H   (DDB_T0CTRL+4)
  65 #define DDB_REFCNTR     DDB_T0CNTR
  66 #define DDB_SPT0CTRL_L  DDB_T1CTRL
  67 #define DDB_SPT0CTRL_H  (DDB_T1CTRL+4)
  68 #define DDB_SPT1CTRL_L  DDB_T2CTRL
  69 #define DDB_SPT1CTRL_H  (DDB_T2CTRL+4)
  70 #define DDB_SPT1CNTR    DDB_T1CTRL
  71 #define DDB_WDTCTRL_L   DDB_T3CTRL
  72 #define DDB_WDTCTRL_H   (DDB_T3CTRL+4)
  73 #define DDB_WDTCNTR     DDB_T3CNTR
  74
  75 /*
  76  * DMA registers are moved.  We don't care about it for now. TODO.
  77  */
  78
  79 /*
  80  * BARs for ext PCI (PCI0)
  81  */
  82 #undef  DDB_BARC
  83 #undef  DDB_BARB
  84
  85 #define DDB_BARC0       0x0210  /* PCI0 Control */
  86 #define DDB_BARM010     0x0218  /* PCI0 SDRAM bank01 */
  87 #define DDB_BARM230     0x0220  /* PCI0 SDRAM bank23 */
  88 #define DDB_BAR00       0x0240  /* PCI0 LDCS0 */
  89 #define DDB_BAR10       0x0248  /* PCI0 LDCS1 */
  90 #define DDB_BAR20       0x0250  /* PCI0 LDCS2 */
  91 #define DDB_BAR30       0x0258  /* PCI0 LDCS3 */
  92 #define DDB_BAR40       0x0260  /* PCI0 LDCS4 */
  93 #define DDB_BAR50       0x0268  /* PCI0 LDCS5 */
  94 #define DDB_BARB0       0x0280  /* PCI0 BOOT */
  95 #define DDB_BARP00      0x0290  /* PCI0 for IOPCI Window0 */
  96 #define DDB_BARP10      0x0298  /* PCI0 for IOPCI Window1 */
  97
  98 /*
  99  * BARs for IOPIC (PCI1)
 100  */
 101 #define DDB_BARC1       0x0610  /* PCI1 Control */
 102 #define DDB_BARM011     0x0618  /* PCI1 SDRAM bank01 */
 103 #define DDB_BARM231     0x0620  /* PCI1 SDRAM bank23 */
 104 #define DDB_BAR01       0x0640  /* PCI1 LDCS0 */
 105 #define DDB_BAR11       0x0648  /* PCI1 LDCS1 */
 106 #define DDB_BAR21       0x0650  /* PCI1 LDCS2 */
 107 #define DDB_BAR31       0x0658  /* PCI1 LDCS3 */
 108 #define DDB_BAR41       0x0660  /* PCI1 LDCS4 */
 109 #define DDB_BAR51       0x0668  /* PCI1 LDCS5 */
 110 #define DDB_BARB1       0x0680  /* PCI1 BOOT */
 111 #define DDB_BARP01      0x0690  /* PCI1 for ext PCI Window0 */
 112 #define DDB_BARP11      0x0698  /* PCI1 for ext PCI Window1 */
 113
 114 /*
 115  * Other registers for ext PCI (PCI0)
 116  */
 117 #define DDB_PCIINIT00   0x02f0  /* PCI0 Initiator 0 */
 118 #define DDB_PCIINIT10   0x02f8  /* PCI0 Initiator 1 */
 119
 120 #define DDB_PCISWP0     0x02b0  /* PCI0 Swap */
 121 #define DDB_PCIERR0     0x02b8  /* PCI0 Error */
 122
 123 #define DDB_PCICTL0_L   0x02e0  /* PCI0 Control-L */
 124 #define DDB_PCICTL0_H   0x02e4  /* PCI0 Control-H */
 125 #define DDB_PCIARB0_L   0x02e8  /* PCI0 Arbitration-L */
 126 #define DDB_PCIARB0_H   0x02ec  /* PCI0 Arbitration-H */
 127
 128 /*
 129  * Other registers for IOPCI (PCI1)
 130  */
 131 #define DDB_IOPCIW0     0x00d0  /* PCI Address Window 0 [R/W] */
 132 #define DDB_IOPCIW1     0x00d8  /* PCI Address Window 1 [R/W] */
 133
 134 #define DDB_PCIINIT01   0x06f0  /* PCI1 Initiator 0 */
 135 #define DDB_PCIINIT11   0x06f8  /* PCI1 Initiator 1 */
 136
 137 #define DDB_PCISWP1     0x06b0  /* PCI1 Swap */
 138 #define DDB_PCIERR1     0x06b8  /* PCI1 Error */
 139
 140 #define DDB_PCICTL1_L   0x06e0  /* PCI1 Control-L */
 141 #define DDB_PCICTL1_H   0x06e4  /* PCI1 Control-H */
 142 #define DDB_PCIARB1_L   0x06e8  /* PCI1 Arbitration-L */
 143 #define DDB_PCIARB1_H   0x06ec  /* PCI1 Arbitration-H */
 144
 145 /*
 146  * Local Bus
 147  */
 148 #define DDB_LCST0       0x0110  /* LB Chip Select Timing 0 */
 149 #define DDB_LCST1       0x0118  /* LB Chip Select Timing 1 */
 150 #undef DDB_LCST2
 151 #define DDB_LCST2       0x0120  /* LB Chip Select Timing 2 */
 152 #undef DDB_LCST3
 153 #undef DDB_LCST4
 154 #undef DDB_LCST5
 155 #undef DDB_LCST6
 156 #undef DDB_LCST7
 157 #undef DDB_LCST8
 158 #define DDB_ERRADR      0x0150  /* Error Address Register */
 159 #define DDB_ERRCS       0x0160
 160 #define DDB_BTM         0x0170  /* Boot Time Mode value */
 161
 162 /*
 163  * MISC registers
 164  */
 165 #define DDB_GIUFUNSEL   0x4040  /* select dual-func pins */
 166 #define DDB_PIBMISC     0x0750  /* USB buffer enable / power saving */
 167
 168 /*
 169  *  Memory map (physical address)
 170  *
 171  *  Note most of the following address must be properly aligned by the
 172  *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
 173  *  PCI_IO_BASE must be aligned along 16MB boundary.
 174  */
 175
 176 /* the actual ram size is detected at run-time */
 177 #define DDB_SDRAM_BASE          0x00000000
 178 #define DDB_MAX_SDRAM_SIZE      0x08000000      /* less than 128MB */
 179
 180 #define DDB_PCI0_MEM_BASE       0x08000000
 181 #define DDB_PCI0_MEM_SIZE       0x08000000      /* 128 MB */
 182
 183 #define DDB_PCI1_MEM_BASE       0x10000000
 184 #define DDB_PCI1_MEM_SIZE       0x08000000      /* 128 MB */
 185
 186 #define DDB_PCI0_CONFIG_BASE    0x18000000
 187 #define DDB_PCI0_CONFIG_SIZE    0x01000000      /* 16 MB */
 188
 189 #define DDB_PCI1_CONFIG_BASE    0x19000000
 190 #define DDB_PCI1_CONFIG_SIZE    0x01000000      /* 16 MB */
 191
 192 #define DDB_PCI_IO_BASE         0x1a000000      /* we concatenate two IOs */
 193 #define DDB_PCI0_IO_BASE        0x1a000000
 194 #define DDB_PCI0_IO_SIZE        0x01000000      /* 16 MB */
 195 #define DDB_PCI1_IO_BASE        0x1b000000
 196 #define DDB_PCI1_IO_SIZE        0x01000000      /* 16 MB */
 197
 198 #define DDB_LCS0_BASE           0x1c000000      /* flash memory */
 199 #define DDB_LCS0_SIZE           0x01000000      /* 16 MB */
 200
 201 #define DDB_LCS1_BASE           0x1d000000      /* misc */
 202 #define DDB_LCS1_SIZE           0x01000000      /* 16 MB */
 203
 204 #define DDB_LCS2_BASE           0x1e000000      /* Mezzanine */
 205 #define DDB_LCS2_SIZE           0x01000000      /* 16 MB */
 206
 207 #define DDB_VRC5477_BASE        0x1fa00000      /* VRC5477 control regs */
 208 #define DDB_VRC5477_SIZE        0x00200000      /* 2MB */
 209
 210 #define DDB_BOOTCS_BASE         0x1fc00000      /* Boot ROM / EPROM /Flash */
 211 #define DDB_BOOTCS_SIZE         0x00200000      /* 2 MB - doc says 4MB */
 212
 213 #define DDB_LED                 DDB_LCS1_BASE + 0x10000
 214
 215
 216 /*
 217  * DDB5477 specific functions
 218  */
 219 #ifndef __ASSEMBLY__
 220 extern void ddb5477_irq_setup(void);
 221
 222 /* route irq to cpu int pin */
 223 extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip);
 224
 225 /* low-level routine for enabling vrc5477 irq, bypassing high-level */
 226 extern void ll_vrc5477_irq_enable(int vrc5477_irq);
 227 extern void ll_vrc5477_irq_disable(int vrc5477_irq);
 228 #endif /* !__ASSEMBLY__ */
 229
 230 /* PCI intr ack share PCIW0 with PCI IO */
 231 #define DDB_PCI_IACK_BASE       DDB_PCI_IO_BASE
 232
 233 /*
 234  * Interrupt mapping
 235  *
 236  * We have three interrupt controllers:
 237  *
 238  *   . CPU itself - 8 sources
 239  *   . i8259 - 16 sources
 240  *   . vrc5477 - 32 sources
 241  *
 242  *  They connected as follows:
 243  *    all vrc5477 interrupts are routed to cpu IP2 (by software setting)
 244  *    all i8359 are routed to INTC in vrc5477 (by hardware connection)
 245  *
 246  *  All VRC5477 PCI interrupts are level-triggered (no ack needed).
 247  *  All PCI irq but INTC are active low.
 248  */
 249
 250 /*
 251  * irq number block assignment
 252  */
 253
 254 #define NUM_CPU_IRQ             8
 255 #define NUM_VRC5477_IRQ         32
 256
 257 #define CPU_IRQ_BASE            MIPS_CPU_IRQ_BASE
 258 #define VRC5477_IRQ_BASE        (CPU_IRQ_BASE + NUM_CPU_IRQ)
 259
 260 /*
 261  * vrc5477 irq defs
 262  */
 263
 264 #define VRC5477_IRQ_CPCE        (0 + VRC5477_IRQ_BASE)  /* cpu parity error */
 265 #define VRC5477_IRQ_CNTD        (1 + VRC5477_IRQ_BASE)  /* cpu no target */
 266 #define VRC5477_IRQ_I2C         (2 + VRC5477_IRQ_BASE)  /* I2C */
 267 #define VRC5477_IRQ_DMA         (3 + VRC5477_IRQ_BASE)  /* DMA */
 268 #define VRC5477_IRQ_UART0       (4 + VRC5477_IRQ_BASE)
 269 #define VRC5477_IRQ_WDOG        (5 + VRC5477_IRQ_BASE)  /* watchdog timer */
 270 #define VRC5477_IRQ_SPT1        (6 + VRC5477_IRQ_BASE)    /* special purpose timer 1 */
 271 #define VRC5477_IRQ_LBRT        (7 + VRC5477_IRQ_BASE)  /* local bus read timeout */
 272 #define VRC5477_IRQ_INTA        (8 + VRC5477_IRQ_BASE)  /* PCI INT #A */
 273 #define VRC5477_IRQ_INTB        (9 + VRC5477_IRQ_BASE)  /* PCI INT #B */
 274 #define VRC5477_IRQ_INTC        (10 + VRC5477_IRQ_BASE) /* PCI INT #C */
 275 #define VRC5477_IRQ_INTD        (11 + VRC5477_IRQ_BASE) /* PCI INT #D */
 276 #define VRC5477_IRQ_INTE        (12 + VRC5477_IRQ_BASE) /* PCI INT #E */
 277 #define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved  */
 278 #define VRC5477_IRQ_PCIS        (14 + VRC5477_IRQ_BASE) /* PCI SERR #  */
 279 #define VRC5477_IRQ_PCI         (15 + VRC5477_IRQ_BASE) /* PCI internal error */
 280 #define VRC5477_IRQ_IOPCI_INTA  (16 + VRC5477_IRQ_BASE)      /* USB-H */
 281 #define VRC5477_IRQ_IOPCI_INTB  (17 + VRC5477_IRQ_BASE)      /* USB-P */
 282 #define VRC5477_IRQ_IOPCI_INTC  (18 + VRC5477_IRQ_BASE)      /* AC97 */
 283 #define VRC5477_IRQ_IOPCI_INTD  (19 + VRC5477_IRQ_BASE)      /* Reserved */
 284 #define VRC5477_IRQ_UART1       (20 + VRC5477_IRQ_BASE)
 285 #define VRC5477_IRQ_SPT0        (21 + VRC5477_IRQ_BASE)      /* special purpose timer 0 */
 286 #define VRC5477_IRQ_GPT0        (22 + VRC5477_IRQ_BASE)      /* general purpose timer 0 */
 287 #define VRC5477_IRQ_GPT1        (23 + VRC5477_IRQ_BASE)      /* general purpose timer 1 */
 288 #define VRC5477_IRQ_GPT2        (24 + VRC5477_IRQ_BASE)      /* general purpose timer 2 */
 289 #define VRC5477_IRQ_GPT3        (25 + VRC5477_IRQ_BASE)      /* general purpose timer 3 */
 290 #define VRC5477_IRQ_GPIO        (26 + VRC5477_IRQ_BASE)
 291 #define VRC5477_IRQ_SIO0        (27 + VRC5477_IRQ_BASE)
 292 #define VRC5477_IRQ_SIO1        (28 + VRC5477_IRQ_BASE)
 293 #define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE)      /* reserved */
 294 #define VRC5477_IRQ_IOPCISERR   (30 + VRC5477_IRQ_BASE)      /* IO PCI SERR # */
 295 #define VRC5477_IRQ_IOPCI       (31 + VRC5477_IRQ_BASE)
 296
 297 /*
 298  * i2859 irq assignment
 299  */
 300 #define I8259_IRQ_RESERVED_0    (0 + I8259A_IRQ_BASE)
 301 #define I8259_IRQ_KEYBOARD      (1 + I8259A_IRQ_BASE)   /* M1543 default */
 302 #define I8259_IRQ_CASCADE       (2 + I8259A_IRQ_BASE)
 303 #define I8259_IRQ_UART_B        (3 + I8259A_IRQ_BASE)   /* M1543 default, may conflict with RTC according to schematic diagram  */
 304 #define I8259_IRQ_UART_A        (4 + I8259A_IRQ_BASE)   /* M1543 default */
 305 #define I8259_IRQ_PARALLEL      (5 + I8259A_IRQ_BASE)   /* M1543 default */
 306 #define I8259_IRQ_RESERVED_6    (6 + I8259A_IRQ_BASE)
 307 #define I8259_IRQ_RESERVED_7    (7 + I8259A_IRQ_BASE)
 308 #define I8259_IRQ_RTC           (8 + I8259A_IRQ_BASE)   /* who set this? */
 309 #define I8259_IRQ_USB           (9 + I8259A_IRQ_BASE)   /* ddb_setup */
 310 #define I8259_IRQ_PMU           (10 + I8259A_IRQ_BASE)  /* ddb_setup */
 311 #define I8259_IRQ_RESERVED_11   (11 + I8259A_IRQ_BASE)
 312 #define I8259_IRQ_RESERVED_12   (12 + I8259A_IRQ_BASE)  /* m1543_irq_setup */
 313 #define I8259_IRQ_RESERVED_13   (13 + I8259A_IRQ_BASE)
 314 #define I8259_IRQ_HDC1          (14 + I8259A_IRQ_BASE)  /* default and ddb_setup */
 315 #define I8259_IRQ_HDC2          (15 + I8259A_IRQ_BASE)  /* default */
 316
 317
 318 /*
 319  * misc
 320  */
 321 #define VRC5477_I8259_CASCADE   (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE)
 322 #define CPU_VRC5477_CASCADE     2
 323
 324 /*
 325  * debug routines
 326  */
 327 #ifndef __ASSEMBLY__
 328 #if defined(CONFIG_RUNTIME_DEBUG)
 329 extern void vrc5477_show_pdar_regs(void);
 330 extern void vrc5477_show_pci_regs(void);
 331 extern void vrc5477_show_bar_regs(void);
 332 extern void vrc5477_show_int_regs(void);
 333 extern void vrc5477_show_all_regs(void);
 334 #endif
 335
 336 /*
 337  * RAM size
 338  */
 339 extern int board_ram_size;
 340 #endif /* !__ASSEMBLY__ */
 341
 342 #endif /* __ASM_DDB5XXX_DDB5477_H */