release/src-rt-6.x/linux/linux-2.6/include/asm-arm/arch-pxa/trizeps4.h

   1 /************************************************************************
   2  * Include file for TRIZEPS4 SoM and ConXS eval-board
   3  * Copyright (c) Jürgen Schindele
   4  * 2006
   5  ************************************************************************/
   6
   7 /*
   8  * Includes/Defines
   9  */
  10 #ifndef _TRIPEPS4_H_
  11 #define _TRIPEPS4_H_
  12
  13 /* physical memory regions */
  14 #define TRIZEPS4_FLASH_PHYS     (PXA_CS0_PHYS)  /* Flash region */
  15 #define TRIZEPS4_DISK_PHYS      (PXA_CS1_PHYS)  /* Disk On Chip region */
  16 #define TRIZEPS4_ETH_PHYS       (PXA_CS2_PHYS)  /* Ethernet DM9000 region */
  17 #define TRIZEPS4_PIC_PHYS       (PXA_CS3_PHYS)  /* Logic chip on ConXS-Board */
  18 #define TRIZEPS4_SDRAM_BASE     0xa0000000      /* SDRAM region */
  19
  20 #define TRIZEPS4_CFSR_PHYS      (PXA_CS3_PHYS)                  /* Logic chip on ConXS-Board CSFR register */
  21 #define TRIZEPS4_BOCR_PHYS      (PXA_CS3_PHYS+0x02000000)       /* Logic chip on ConXS-Board BOCR register */
  22 #define TRIZEPS4_IRCR_PHYS      (PXA_CS3_PHYS+0x02400000)       /* Logic chip on ConXS-Board IRCR register*/
  23 #define TRIZEPS4_UPSR_PHYS      (PXA_CS3_PHYS+0x02800000)       /* Logic chip on ConXS-Board UPSR register*/
  24 #define TRIZEPS4_DICR_PHYS      (PXA_CS3_PHYS+0x03800000)       /* Logic chip on ConXS-Board DICR register*/
  25
  26 /* virtual memory regions */
  27 #define TRIZEPS4_DISK_VIRT      0xF0000000      /* Disk On Chip region */
  28
  29 #define TRIZEPS4_PIC_VIRT       0xF0100000      /* not used */
  30 #define TRIZEPS4_CFSR_VIRT      0xF0100000
  31 #define TRIZEPS4_BOCR_VIRT      0xF0200000
  32 #define TRIZEPS4_DICR_VIRT      0xF0300000
  33 #define TRIZEPS4_IRCR_VIRT      0xF0400000
  34 #define TRIZEPS4_UPSR_VIRT      0xF0500000
  35
  36 /* size of flash */
  37 #define TRIZEPS4_FLASH_SIZE     0x02000000      /* Flash size 32 MB */
  38
  39 /* Ethernet Controller Davicom DM9000 */
  40 #define GPIO_DM9000             101
  41 #define TRIZEPS4_ETH_IRQ        IRQ_GPIO(GPIO_DM9000)
  42
  43 /* UCB1400 audio / TS-controller */
  44 #define GPIO_UCB1400            1
  45 #define TRIZEPS4_UCB1400_IRQ    IRQ_GPIO(GPIO_UCB1400)
  46
  47 /* PCMCIA socket Compact Flash */
  48 #define GPIO_PCD                11              /* PCMCIA Card Detect */
  49 #define TRIZEPS4_CD_IRQ         IRQ_GPIO(GPIO_PCD)
  50 #define GPIO_PRDY               13              /* READY / nINT */
  51 #define TRIZEPS4_READY_NINT     IRQ_GPIO(GPIO_PRDY)
  52
  53 /* MMC socket */
  54 #define GPIO_MMC_DET            12
  55 #define TRIZEPS4_MMC_IRQ        IRQ_GPIO(GPIO_MMC_DET)
  56
  57 /* LEDS using tx2 / rx2 */
  58 #define GPIO_SYS_BUSY_LED       46
  59 #define GPIO_HEARTBEAT_LED      47
  60
  61 /* Off-module PIC on ConXS board */
  62 #define GPIO_PIC                0
  63 #define TRIZEPS4_PIC_IRQ        IRQ_GPIO(GPIO_PIC)
  64
  65 #define CFSR_P2V(x)             ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
  66 #define CFSR_V2P(x)             ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
  67
  68 #define BCR_P2V(x)              ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
  69 #define BCR_V2P(x)              ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
  70
  71 #define DCR_P2V(x)              ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
  72 #define DCR_V2P(x)              ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
  73
  74 #ifndef __ASSEMBLY__
  75 #define ConXS_CFSR              (*((volatile unsigned short *)CFSR_P2V(0x0C000000)))
  76 #define ConXS_BCR               (*((volatile unsigned short *)BCR_P2V(0x0E000000)))
  77 #define ConXS_DCR               (*((volatile unsigned short *)DCR_P2V(0x0F800000)))
  78 #else
  79 #define ConXS_CFSR              CFSR_P2V(0x0C000000)
  80 #define ConXS_BCR               BCR_P2V(0x0E000000)
  81 #define ConXS_DCR               DCR_P2V(0x0F800000)
  82 #endif
  83
  84 #define ConXS_CFSR_BVD_MASK     0x0003
  85 #define ConXS_CFSR_BVD1         (1 << 0)
  86 #define ConXS_CFSR_BVD2         (1 << 1)
  87 #define ConXS_CFSR_VS_MASK      0x000C
  88 #define ConXS_CFSR_VS1          (1 << 2)
  89 #define ConXS_CFSR_VS2          (1 << 3)
  90 #define ConXS_CFSR_VS_5V        (0x3 << 2)
  91 #define ConXS_CFSR_VS_3V3       0x0
  92
  93 #define ConXS_BCR_S0_POW_EN0    (1 << 0)
  94 #define ConXS_BCR_S0_POW_EN1    (1 << 1)
  95 #define ConXS_BCR_L_DISP        (1 << 4)
  96 #define ConXS_BCR_CF_BUF_EN     (1 << 5)
  97 #define ConXS_BCR_CF_RESET      (1 << 7)
  98 #define ConXS_BCR_S0_VCC_3V3    0x1
  99 #define ConXS_BCR_S0_VCC_5V0    0x2
 100 #define ConXS_BCR_S0_VPP_12V    0x4
 101 #define ConXS_BCR_S0_VPP_3V3    0x8
 102
 103 #define ConXS_IRCR_MODE         (1 << 0)
 104 #define ConXS_IRCR_SD           (1 << 1)
 105
 106 #endif /* _TRIPEPS4_H_ */