release/src-rt-6.x/linux/linux-2.6/drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 #ifdef  __KERNEL__
  23 #ifndef BIT
  24 #define BIT(nr) (1UL << (nr))
  25 #endif
  26 #endif
  27
  28 /* definitions used for the EHCI driver */
  29
  30 /*
  31  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  32  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  33  * the host controller implementation.
  34  *
  35  * To facilitate the strongest possible byte-order checking from "sparse"
  36  * and so on, we use __leXX unless that's not practical.
  37  */
  38 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  39 typedef __u32 __bitwise __hc32;
  40 typedef __u16 __bitwise __hc16;
  41 #else
  42 #define __hc32  __le32
  43 #define __hc16  __le16
  44 #endif
  45
  46 /* statistics can be kept for for tuning/monitoring */
  47 struct ehci_stats {
  48         /* irq usage */
  49         unsigned long           normal;
  50         unsigned long           error;
  51         unsigned long           reclaim;
  52         unsigned long           lost_iaa;
  53
  54         /* termination of urbs from core */
  55         unsigned long           complete;
  56         unsigned long           unlink;
  57 };
  58
  59 /* ehci_hcd->lock guards shared data against other CPUs:
  60  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  61  *   usb_host_endpoint: hcpriv
  62  *   ehci_qh:   qh_next, qtd_list
  63  *   ehci_qtd:  qtd_list
  64  *
  65  * Also, hold this lock when talking to HC registers or
  66  * when updating hw_* fields in shared qh/qtd/... structures.
  67  */
  68
  69 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  70
  71 struct ehci_hcd {                       /* one per controller */
  72         /* glue to PCI and HCD framework */
  73         struct ehci_caps __iomem *caps;
  74         struct ehci_regs __iomem *regs;
  75         struct ehci_dbg_port __iomem *debug;
  76
  77         __u32                   hcs_params;     /* cached register copy */
  78         spinlock_t              lock;
  79
  80         /* async schedule support */
  81         struct ehci_qh          *async;
  82         struct ehci_qh          *dummy;         /* For AMD quirk use */
  83         struct ehci_qh          *reclaim;
  84         unsigned                scanning : 1;
  85
  86         /* periodic schedule support */
  87 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  88         unsigned                periodic_size;
  89         __hc32                  *periodic;      /* hw periodic table */
  90         dma_addr_t              periodic_dma;
  91         unsigned                i_thresh;       /* uframes HC might cache */
  92
  93         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  94         int                     next_uframe;    /* scan periodic, start here */
  95         unsigned                periodic_sched; /* periodic activity count */
  96
  97         /* list of itds & sitds completed while clock_frame was still active */
  98         struct list_head        cached_itd_list;
  99         struct list_head        cached_sitd_list;
 100         unsigned                clock_frame;
 101
 102         /* per root hub port */
 103         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
 104
 105         /* bit vectors (one bit per port) */
 106         unsigned long           bus_suspended;          /* which ports were
 107                         already suspended at the start of a bus suspend */
 108         unsigned long           companion_ports;        /* which ports are
 109                         dedicated to the companion controller */
 110         unsigned long           owned_ports;            /* which ports are
 111                         owned by the companion during a bus suspend */
 112         unsigned long           port_c_suspend;         /* which ports have
 113                         the change-suspend feature turned on */
 114         unsigned long           suspended_ports;        /* which ports are
 115                         suspended */
 116
 117         /* per-HC memory pools (could be per-bus, but ...) */
 118         struct dma_pool         *qh_pool;       /* qh per active urb */
 119         struct dma_pool         *qtd_pool;      /* one or more per qh */
 120         struct dma_pool         *itd_pool;      /* itd per iso urb */
 121         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 122
 123         struct timer_list       iaa_watchdog;
 124         struct timer_list       watchdog;
 125         unsigned long           actions;
 126         unsigned                stamp;
 127         unsigned                periodic_stamp;
 128         unsigned                random_frame;
 129         unsigned long           next_statechange;
 130         ktime_t                 last_periodic_enable;
 131         u32                     command;
 132
 133         /* SILICON QUIRKS */
 134         unsigned                no_selective_suspend:1;
 135         unsigned                has_fsl_port_bug:1; /* FreeScale */
 136         unsigned                big_endian_mmio:1;
 137         unsigned                big_endian_desc:1;
 138         unsigned                need_io_watchdog:1;
 139         unsigned                broken_periodic:1;
 140         unsigned                fs_i_thresh:1;  /* Intel iso scheduling */
 141         unsigned                use_dummy_qh:1; /* AMD Frame List table quirk*/
 142
 143         u8                      sbrn;           /* packed release number */
 144
 145         /* irq statistics */
 146 #ifdef EHCI_STATS
 147         struct ehci_stats       stats;
 148 #       define COUNT(x) do { (x)++; } while (0)
 149 #else
 150 #       define COUNT(x) do {} while (0)
 151 #endif
 152
 153         /* debug files */
 154 #ifdef DEBUG
 155         struct dentry           *debug_dir;
 156 #endif
 157 };
 158
 159 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 160 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 161 {
 162         return (struct ehci_hcd *) (hcd->hcd_priv);
 163 }
 164 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 165 {
 166         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 167 }
 168
 169
 170 static inline void
 171 iaa_watchdog_start(struct ehci_hcd *ehci)
 172 {
 173         WARN_ON(timer_pending(&ehci->iaa_watchdog));
 174         mod_timer(&ehci->iaa_watchdog,
 175                         jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
 176 }
 177
 178 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
 179 {
 180         del_timer(&ehci->iaa_watchdog);
 181 }
 182
 183 enum ehci_timer_action {
 184         TIMER_IO_WATCHDOG,
 185         TIMER_ASYNC_SHRINK,
 186         TIMER_ASYNC_OFF,
 187 };
 188
 189 static inline void
 190 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 191 {
 192         clear_bit (action, &ehci->actions);
 193 }
 194
 195 static void free_cached_lists(struct ehci_hcd *ehci);
 196
 197 /*-------------------------------------------------------------------------*/
 198
 199 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 200
 201 /* Section 2.2 Host Controller Capability Registers */
 202 struct ehci_caps {
 203         /* these fields are specified as 8 and 16 bit registers,
 204          * but some hosts can't perform 8 or 16 bit PCI accesses.
 205          */
 206         u32             hc_capbase;
 207 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
 208 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
 209         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 210 #define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
 211 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
 212 #define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
 213 #define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
 214 #define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
 215 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
 216 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 217
 218         u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
 219 #define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
 220 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
 221 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
 222 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 223 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 224 #define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
 225         u8              portroute [8];   /* nibbles for routing - offset 0xC */
 226 } __attribute__ ((packed));
 227
 228
 229 /* Section 2.3 Host Controller Operational Registers */
 230 struct ehci_regs {
 231
 232         /* USBCMD: offset 0x00 */
 233         u32             command;
 234 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 235 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 236 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 237 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
 238 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 239 #define CMD_ASE         (1<<5)          /* async schedule enable */
 240 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 241 /* 3:2 is periodic frame list size */
 242 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 243 #define CMD_RUN         (1<<0)          /* start/stop HC */
 244
 245         /* USBSTS: offset 0x04 */
 246         u32             status;
 247 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 248 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 249 #define STS_RECL        (1<<13)         /* Reclamation */
 250 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 251 /* some bits reserved */
 252         /* these STS_* flags are also intr_enable bits (USBINTR) */
 253 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 254 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 255 #define STS_FLR         (1<<3)          /* frame list rolled over */
 256 #define STS_PCD         (1<<2)          /* port change detect */
 257 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 258 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 259
 260         /* USBINTR: offset 0x08 */
 261         u32             intr_enable;
 262
 263         /* FRINDEX: offset 0x0C */
 264         u32             frame_index;    /* current microframe number */
 265         /* CTRLDSSEGMENT: offset 0x10 */
 266         u32             segment;        /* address bits 63:32 if needed */
 267         /* PERIODICLISTBASE: offset 0x14 */
 268         u32             frame_list;     /* points to periodic list */
 269         /* ASYNCLISTADDR: offset 0x18 */
 270         u32             async_next;     /* address of next async queue head */
 271
 272         u32             reserved [9];
 273
 274         /* CONFIGFLAG: offset 0x40 */
 275         u32             configured_flag;
 276 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
 277
 278         /* PORTSC: offset 0x44 */
 279         u32             port_status [0];        /* up to N_PORTS */
 280 /* 31:23 reserved */
 281 #define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
 282 #define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
 283 #define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
 284 /* 19:16 for port testing */
 285 #define PORT_LED_OFF    (0<<14)
 286 #define PORT_LED_AMBER  (1<<14)
 287 #define PORT_LED_GREEN  (2<<14)
 288 #define PORT_LED_MASK   (3<<14)
 289 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
 290 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
 291 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
 292 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
 293 /* 9 reserved */
 294 #define PORT_RESET      (1<<8)          /* reset port */
 295 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 296 #define PORT_RESUME     (1<<6)          /* resume it */
 297 #define PORT_OCC        (1<<5)          /* over current change */
 298 #define PORT_OC         (1<<4)          /* over current active */
 299 #define PORT_PEC        (1<<3)          /* port enable change */
 300 #define PORT_PE         (1<<2)          /* port enable */
 301 #define PORT_CSC        (1<<1)          /* connect status change */
 302 #define PORT_CONNECT    (1<<0)          /* device connected */
 303 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
 304 } __attribute__ ((packed));
 305
 306 #define USBMODE         0x68            /* USB Device mode */
 307 #define USBMODE_SDIS    (1<<3)          /* Stream disable */
 308 #define USBMODE_BE      (1<<2)          /* BE/LE endianness select */
 309 #define USBMODE_CM_HC   (3<<0)          /* host controller mode */
 310 #define USBMODE_CM_IDLE (0<<0)          /* idle state */
 311
 312 /* Appendix C, Debug port ... intended for use with special "debug devices"
 313  * that can help if there's no serial console.  (nonstandard enumeration.)
 314  */
 315 struct ehci_dbg_port {
 316         u32     control;
 317 #define DBGP_OWNER      (1<<30)
 318 #define DBGP_ENABLED    (1<<28)
 319 #define DBGP_DONE       (1<<16)
 320 #define DBGP_INUSE      (1<<10)
 321 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
 322 #       define DBGP_ERR_BAD     1
 323 #       define DBGP_ERR_SIGNAL  2
 324 #define DBGP_ERROR      (1<<6)
 325 #define DBGP_GO         (1<<5)
 326 #define DBGP_OUT        (1<<4)
 327 #define DBGP_LEN(x)     (((x)>>0)&0x0f)
 328         u32     pids;
 329 #define DBGP_PID_GET(x)         (((x)>>16)&0xff)
 330 #define DBGP_PID_SET(data,tok)  (((data)<<8)|(tok))
 331         u32     data03;
 332         u32     data47;
 333         u32     address;
 334 #define DBGP_EPADDR(dev,ep)     (((dev)<<8)|(ep))
 335 } __attribute__ ((packed));
 336
 337 /*-------------------------------------------------------------------------*/
 338
 339 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 340
 341 /*
 342  * EHCI Specification 0.95 Section 3.5
 343  * QTD: describe data transfer components (buffer, direction, ...)
 344  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 345  *
 346  * These are associated only with "QH" (Queue Head) structures,
 347  * used with control, bulk, and interrupt transfers.
 348  */
 349 struct ehci_qtd {
 350         /* first part defined by EHCI spec */
 351         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 352         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 353         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 354 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 355 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 356 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 357 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 358 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 359 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 360 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 361 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 362 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 363 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 364 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 365 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 366 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 367
 368 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 369 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 370 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 371
 372         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 373         __hc32                  hw_buf_hi [5];        /* Appendix B */
 374
 375         /* the rest is HCD-private */
 376         dma_addr_t              qtd_dma;                /* qtd address */
 377         struct list_head        qtd_list;               /* sw qtd list */
 378         struct urb              *urb;                   /* qtd's urb */
 379         size_t                  length;                 /* length of buffer */
 380 } __attribute__ ((aligned (32)));
 381
 382 /* mask NakCnt+T in qh->hw_alt_next */
 383 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 384
 385 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 386
 387 /*-------------------------------------------------------------------------*/
 388
 389 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 390 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 391
 392 /*
 393  * Now the following defines are not converted using the
 394  * __constant_cpu_to_le32() macro anymore, since we have to support
 395  * "dynamic" switching between be and le support, so that the driver
 396  * can be used on one system with SoC EHCI controller using big-endian
 397  * descriptors as well as a normal little-endian PCI EHCI controller.
 398  */
 399 /* values for that type tag */
 400 #define Q_TYPE_ITD      (0 << 1)
 401 #define Q_TYPE_QH       (1 << 1)
 402 #define Q_TYPE_SITD     (2 << 1)
 403 #define Q_TYPE_FSTN     (3 << 1)
 404
 405 /* next async queue entry, or pointer to interrupt/periodic QH */
 406 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 407
 408 /* for periodic/async schedules and qtd lists, mark end of list */
 409 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 410
 411 /*
 412  * Entries in periodic shadow table are pointers to one of four kinds
 413  * of data structure.  That's dictated by the hardware; a type tag is
 414  * encoded in the low bits of the hardware's periodic schedule.  Use
 415  * Q_NEXT_TYPE to get the tag.
 416  *
 417  * For entries in the async schedule, the type tag always says "qh".
 418  */
 419 union ehci_shadow {
 420         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 421         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 422         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 423         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 424         __hc32                  *hw_next;       /* (all types) */
 425         void                    *ptr;
 426 };
 427
 428 /*-------------------------------------------------------------------------*/
 429
 430 /*
 431  * EHCI Specification 0.95 Section 3.6
 432  * QH: describes control/bulk/interrupt endpoints
 433  * See Fig 3-7 "Queue Head Structure Layout".
 434  *
 435  * These appear in both the async and (for interrupt) periodic schedules.
 436  */
 437
 438 /* first part defined by EHCI spec */
 439 struct ehci_qh_hw {
 440         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 441         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 442 #define QH_HEAD         0x00008000
 443         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 444 #define QH_SMASK        0x000000ff
 445 #define QH_CMASK        0x0000ff00
 446 #define QH_HUBADDR      0x007f0000
 447 #define QH_HUBPORT      0x3f800000
 448 #define QH_MULT         0xc0000000
 449         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 450
 451         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 452         __hc32                  hw_qtd_next;
 453         __hc32                  hw_alt_next;
 454         __hc32                  hw_token;
 455         __hc32                  hw_buf [5];
 456         __hc32                  hw_buf_hi [5];
 457 } __attribute__ ((aligned(32)));
 458
 459 struct ehci_qh {
 460         struct ehci_qh_hw       *hw;
 461         /* the rest is HCD-private */
 462         dma_addr_t              qh_dma;         /* address of qh */
 463         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 464         struct list_head        qtd_list;       /* sw qtd list */
 465         struct ehci_qtd         *dummy;
 466         struct ehci_qh          *reclaim;       /* next to reclaim */
 467
 468         struct ehci_hcd         *ehci;
 469
 470         /*
 471          * Do NOT use atomic operations for QH refcounting. On some CPUs
 472          * (PPC7448 for example), atomic operations cannot be performed on
 473          * memory that is cache-inhibited (i.e. being used for DMA).
 474          * Spinlocks are used to protect all QH fields.
 475          */
 476         u32                     refcount;
 477         unsigned                stamp;
 478
 479         u8                      needs_rescan;   /* Dequeue during giveback */
 480         u8                      qh_state;
 481 #define QH_STATE_LINKED         1               /* HC sees this */
 482 #define QH_STATE_UNLINK         2               /* HC may still see this */
 483 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 484 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 485 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 486
 487         u8                      xacterrs;       /* XactErr retry counter */
 488 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 489
 490         /* periodic schedule info */
 491         u8                      usecs;          /* intr bandwidth */
 492         u8                      gap_uf;         /* uframes split/csplit gap */
 493         u8                      c_usecs;        /* ... split completion bw */
 494         u16                     tt_usecs;       /* tt downstream bandwidth */
 495         unsigned short          period;         /* polling interval */
 496         unsigned short          start;          /* where polling starts */
 497 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 498         struct usb_device       *dev;           /* access to TT */
 499         unsigned                is_out:1;       /* bulk or intr OUT */
 500         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 501 };
 502
 503 /*-------------------------------------------------------------------------*/
 504
 505 /* description of one iso transaction (up to 3 KB data if highspeed) */
 506 struct ehci_iso_packet {
 507         /* These will be copied to iTD when scheduling */
 508         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 509         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 510         u8                      cross;          /* buf crosses pages */
 511         /* for full speed OUT splits */
 512         u32                     buf1;
 513 };
 514
 515 /* temporary schedule data for packets from iso urbs (both speeds)
 516  * each packet is one logical usb transaction to the device (not TT),
 517  * beginning at stream->next_uframe
 518  */
 519 struct ehci_iso_sched {
 520         struct list_head        td_list;
 521         unsigned                span;
 522         struct ehci_iso_packet  packet [0];
 523 };
 524
 525 /*
 526  * ehci_iso_stream - groups all (s)itds for this endpoint.
 527  * acts like a qh would, if EHCI had them for ISO.
 528  */
 529 struct ehci_iso_stream {
 530         /* first field matches ehci_hq, but is NULL */
 531         struct ehci_qh_hw       *hw;
 532
 533         u32                     refcount;
 534         u8                      bEndpointAddress;
 535         u8                      highspeed;
 536         struct list_head        td_list;        /* queued itds/sitds */
 537         struct list_head        free_list;      /* list of unused itds/sitds */
 538         struct usb_device       *udev;
 539         struct usb_host_endpoint *ep;
 540
 541         /* output of (re)scheduling */
 542         int                     next_uframe;
 543         __hc32                  splits;
 544
 545         /* the rest is derived from the endpoint descriptor,
 546          * trusting urb->interval == f(epdesc->bInterval) and
 547          * including the extra info for hw_bufp[0..2]
 548          */
 549         u8                      usecs, c_usecs;
 550         u16                     interval;
 551         u16                     tt_usecs;
 552         u16                     maxp;
 553         u16                     raw_mask;
 554         unsigned                bandwidth;
 555
 556         /* This is used to initialize iTD's hw_bufp fields */
 557         __hc32                  buf0;
 558         __hc32                  buf1;
 559         __hc32                  buf2;
 560
 561         /* this is used to initialize sITD's tt info */
 562         __hc32                  address;
 563 };
 564
 565 /*-------------------------------------------------------------------------*/
 566
 567 /*
 568  * EHCI Specification 0.95 Section 3.3
 569  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 570  *
 571  * Schedule records for high speed iso xfers
 572  */
 573 struct ehci_itd {
 574         /* first part defined by EHCI spec */
 575         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 576         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 577 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 578 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 579 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 580 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 581 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 582 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 583
 584 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 585
 586         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 587         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 588
 589         /* the rest is HCD-private */
 590         dma_addr_t              itd_dma;        /* for this itd */
 591         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 592
 593         struct urb              *urb;
 594         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 595         struct list_head        itd_list;       /* list of stream's itds */
 596
 597         /* any/all hw_transactions here may be used by that urb */
 598         unsigned                frame;          /* where scheduled */
 599         unsigned                pg;
 600         unsigned                index[8];       /* in urb->iso_frame_desc */
 601 } __attribute__ ((aligned (32)));
 602
 603 /*-------------------------------------------------------------------------*/
 604
 605 /*
 606  * EHCI Specification 0.95 Section 3.4
 607  * siTD, aka split-transaction isochronous Transfer Descriptor
 608  *       ... describe full speed iso xfers through TT in hubs
 609  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 610  */
 611 struct ehci_sitd {
 612         /* first part defined by EHCI spec */
 613         __hc32                  hw_next;
 614 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 615         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 616         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 617         __hc32                  hw_results;             /* EHCI table 3-11 */
 618 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 619 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 620 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 621 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 622 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 623 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 624 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 625 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 626 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 627 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 628
 629 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 630
 631         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 632         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 633         __hc32                  hw_buf_hi [2];          /* Appendix B */
 634
 635         /* the rest is HCD-private */
 636         dma_addr_t              sitd_dma;
 637         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 638
 639         struct urb              *urb;
 640         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 641         struct list_head        sitd_list;      /* list of stream's sitds */
 642         unsigned                frame;
 643         unsigned                index;
 644 } __attribute__ ((aligned (32)));
 645
 646 /*-------------------------------------------------------------------------*/
 647
 648 /*
 649  * EHCI Specification 0.96 Section 3.7
 650  * Periodic Frame Span Traversal Node (FSTN)
 651  *
 652  * Manages split interrupt transactions (using TT) that span frame boundaries
 653  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 654  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 655  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 656  */
 657 struct ehci_fstn {
 658         __hc32                  hw_next;        /* any periodic q entry */
 659         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 660
 661         /* the rest is HCD-private */
 662         dma_addr_t              fstn_dma;
 663         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 664 } __attribute__ ((aligned (32)));
 665
 666 /*-------------------------------------------------------------------------*/
 667
 668 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 669
 670 /*
 671  * Some EHCI controllers have a Transaction Translator built into the
 672  * root hub. This is a non-standard feature.  Each controller will need
 673  * to add code to the following inline functions, and call them as
 674  * needed (mostly in root hub code).
 675  */
 676
 677 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 678
 679 /* Returns the speed of a device attached to a port on the root hub. */
 680 static inline unsigned int
 681 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 682 {
 683         if (ehci_is_TDI(ehci)) {
 684                 switch ((portsc>>26)&3) {
 685                 case 0:
 686                         return 0;
 687                 case 1:
 688                         return (1<<USB_PORT_FEAT_LOWSPEED);
 689                 case 2:
 690                 default:
 691                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 692                 }
 693         }
 694         return (1<<USB_PORT_FEAT_HIGHSPEED);
 695 }
 696
 697 #else
 698
 699 #define ehci_is_TDI(e)                  (0)
 700
 701 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 702 #endif
 703
 704 /*-------------------------------------------------------------------------*/
 705
 706 #ifdef CONFIG_PPC_83xx
 707 /* Some Freescale processors have an erratum in which the TT
 708  * port number in the queue head was 0..N-1 instead of 1..N.
 709  */
 710 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 711 #else
 712 #define ehci_has_fsl_portno_bug(e)              (0)
 713 #endif
 714
 715 /*
 716  * While most USB host controllers implement their registers in
 717  * little-endian format, a minority (celleb companion chip) implement
 718  * them in big endian format.
 719  *
 720  * This attempts to support either format at compile time without a
 721  * runtime penalty, or both formats with the additional overhead
 722  * of checking a flag bit.
 723  */
 724
 725 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 726 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 727 #else
 728 #define ehci_big_endian_mmio(e)         0
 729 #endif
 730
 731 /*
 732  * Big-endian read/write functions are arch-specific.
 733  * Other arches can be added if/when they're needed.
 734  *
 735  * REVISIT: arch/powerpc now has readl/writel_be, so the
 736  * definition below can die once the 4xx support is
 737  * finally ported over.
 738  */
 739 #if defined(CONFIG_PPC)
 740 #define readl_be(addr)          in_be32((__force unsigned *)addr)
 741 #define writel_be(val, addr)    out_be32((__force unsigned *)addr, val)
 742 #endif
 743
 744 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 745                 __u32 __iomem * regs)
 746 {
 747 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 748         return ehci_big_endian_mmio(ehci) ?
 749                 readl_be(regs) :
 750                 readl(regs);
 751 #else
 752         return readl(regs);
 753 #endif
 754 }
 755
 756 static inline void ehci_writel(const struct ehci_hcd *ehci,
 757                 const unsigned int val, __u32 __iomem *regs)
 758 {
 759 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 760         ehci_big_endian_mmio(ehci) ?
 761                 writel_be(val, regs) :
 762                 writel(val, regs);
 763 #else
 764         writel(val, regs);
 765 #endif
 766 }
 767
 768 /*-------------------------------------------------------------------------*/
 769
 770 /*
 771  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 772  * format, but also its DMA data structures (descriptors).
 773  *
 774  * EHCI controllers accessed through PCI work normally (little-endian
 775  * everywhere), so we won't bother supporting a BE-only mode for now.
 776  */
 777 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 778 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 779
 780 /* cpu to ehci */
 781 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 782 {
 783         return ehci_big_endian_desc(ehci)
 784                 ? (__force __hc32)cpu_to_be32(x)
 785                 : (__force __hc32)cpu_to_le32(x);
 786 }
 787
 788 /* ehci to cpu */
 789 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 790 {
 791         return ehci_big_endian_desc(ehci)
 792                 ? be32_to_cpu((__force __be32)x)
 793                 : le32_to_cpu((__force __le32)x);
 794 }
 795
 796 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 797 {
 798         return ehci_big_endian_desc(ehci)
 799                 ? be32_to_cpup((__force __be32 *)x)
 800                 : le32_to_cpup((__force __le32 *)x);
 801 }
 802
 803 #else
 804
 805 /* cpu to ehci */
 806 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 807 {
 808         return cpu_to_le32(x);
 809 }
 810
 811 /* ehci to cpu */
 812 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 813 {
 814         return le32_to_cpu(x);
 815 }
 816
 817 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 818 {
 819         return le32_to_cpup(x);
 820 }
 821
 822 #endif
 823
 824 /*-------------------------------------------------------------------------*/
 825
 826 #ifndef DEBUG
 827 #define STUB_DEBUG_FILES
 828 #endif  /* DEBUG */
 829
 830 /*-------------------------------------------------------------------------*/
 831
 832 #endif /* __LINUX_EHCI_HCD_H */