allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / usb / host / ehci-sched.c
blob19318f42edc56b4be908c19b0e0d7168e1c7b9c3
1 /*
2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 /* this file is part of ehci-hcd.c */
22 /*-------------------------------------------------------------------------*/
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
37 static int ehci_get_frame (struct usb_hcd *hcd);
39 /*-------------------------------------------------------------------------*/
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
46 static union ehci_shadow *
47 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
48 __hc32 tag)
50 switch (hc32_to_cpu(ehci, tag)) {
51 case Q_TYPE_QH:
52 return &periodic->qh->qh_next;
53 case Q_TYPE_FSTN:
54 return &periodic->fstn->fstn_next;
55 case Q_TYPE_ITD:
56 return &periodic->itd->itd_next;
57 // case Q_TYPE_SITD:
58 default:
59 return &periodic->sitd->sitd_next;
63 static __hc32 *
64 shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic,
65 __hc32 tag)
67 switch (hc32_to_cpu(ehci, tag)) {
68 /* our ehci_shadow.qh is actually software part */
69 case Q_TYPE_QH:
70 return &periodic->qh->hw->hw_next;
71 /* others are hw parts */
72 default:
73 return periodic->hw_next;
77 /* caller must hold ehci->lock */
78 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
80 union ehci_shadow *prev_p = &ehci->pshadow[frame];
81 __hc32 *hw_p = &ehci->periodic[frame];
82 union ehci_shadow here = *prev_p;
84 /* find predecessor of "ptr"; hw and shadow lists are in sync */
85 while (here.ptr && here.ptr != ptr) {
86 prev_p = periodic_next_shadow(ehci, prev_p,
87 Q_NEXT_TYPE(ehci, *hw_p));
88 hw_p = shadow_next_periodic(ehci, &here,
89 Q_NEXT_TYPE(ehci, *hw_p));
90 here = *prev_p;
92 /* an interrupt entry (at list end) could have been shared */
93 if (!here.ptr)
94 return;
96 /* update shadow and hardware lists ... the old "next" pointers
97 * from ptr may still be in use, the caller updates them.
99 *prev_p = *periodic_next_shadow(ehci, &here,
100 Q_NEXT_TYPE(ehci, *hw_p));
102 if (!ehci->use_dummy_qh ||
103 *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p))
104 != EHCI_LIST_END(ehci))
105 *hw_p = *shadow_next_periodic(ehci, &here,
106 Q_NEXT_TYPE(ehci, *hw_p));
107 else
108 *hw_p = ehci->dummy->qh_dma;
111 /* how many of the uframe's 125 usecs are allocated? */
112 static unsigned short
113 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
115 __hc32 *hw_p = &ehci->periodic [frame];
116 union ehci_shadow *q = &ehci->pshadow [frame];
117 unsigned usecs = 0;
118 struct ehci_qh_hw *hw;
120 while (q->ptr) {
121 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
122 case Q_TYPE_QH:
123 hw = q->qh->hw;
124 /* is it in the S-mask? */
125 if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
126 usecs += q->qh->usecs;
127 /* ... or C-mask? */
128 if (hw->hw_info2 & cpu_to_hc32(ehci,
129 1 << (8 + uframe)))
130 usecs += q->qh->c_usecs;
131 hw_p = &hw->hw_next;
132 q = &q->qh->qh_next;
133 break;
134 // case Q_TYPE_FSTN:
135 default:
136 /* for "save place" FSTNs, count the relevant INTR
137 * bandwidth from the previous frame
139 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
140 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
142 hw_p = &q->fstn->hw_next;
143 q = &q->fstn->fstn_next;
144 break;
145 case Q_TYPE_ITD:
146 if (q->itd->hw_transaction[uframe])
147 usecs += q->itd->stream->usecs;
148 hw_p = &q->itd->hw_next;
149 q = &q->itd->itd_next;
150 break;
151 case Q_TYPE_SITD:
152 /* is it in the S-mask? (count SPLIT, DATA) */
153 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
154 1 << uframe)) {
155 if (q->sitd->hw_fullspeed_ep &
156 cpu_to_hc32(ehci, 1<<31))
157 usecs += q->sitd->stream->usecs;
158 else /* worst case for OUT start-split */
159 usecs += HS_USECS_ISO (188);
162 /* ... C-mask? (count CSPLIT, DATA) */
163 if (q->sitd->hw_uframe &
164 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
165 /* worst case for IN complete-split */
166 usecs += q->sitd->stream->c_usecs;
169 hw_p = &q->sitd->hw_next;
170 q = &q->sitd->sitd_next;
171 break;
174 #ifdef DEBUG
175 if (usecs > 100)
176 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
177 frame * 8 + uframe, usecs);
178 #endif
179 return usecs;
182 /*-------------------------------------------------------------------------*/
184 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
186 if (!dev1->tt || !dev2->tt)
187 return 0;
188 if (dev1->tt != dev2->tt)
189 return 0;
190 if (dev1->tt->multi)
191 return dev1->ttport == dev2->ttport;
192 else
193 return 1;
196 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
198 /* Which uframe does the low/fullspeed transfer start in?
200 * The parameter is the mask of ssplits in "H-frame" terms
201 * and this returns the transfer start uframe in "B-frame" terms,
202 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
203 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
204 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
206 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
208 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
209 if (!smask) {
210 ehci_err(ehci, "invalid empty smask!\n");
211 /* uframe 7 can't have bw so this will indicate failure */
212 return 7;
214 return ffs(smask) - 1;
217 static const unsigned char
218 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 58, 0 };
220 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
221 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
223 int i;
224 for (i=0; i<7; i++) {
225 if (max_tt_usecs[i] < tt_usecs[i]) {
226 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
227 tt_usecs[i] = max_tt_usecs[i];
232 /* How many of the tt's periodic downstream 1000 usecs are allocated?
234 * While this measures the bandwidth in terms of usecs/uframe,
235 * the low/fullspeed bus has no notion of uframes, so any particular
236 * low/fullspeed transfer can "carry over" from one uframe to the next,
237 * since the TT just performs downstream transfers in sequence.
239 * For example two separate 100 usec transfers can start in the same uframe,
240 * and the second one would "carry over" 75 usecs into the next uframe.
242 static void
243 periodic_tt_usecs (
244 struct ehci_hcd *ehci,
245 struct usb_device *dev,
246 unsigned frame,
247 unsigned short tt_usecs[8]
250 __hc32 *hw_p = &ehci->periodic [frame];
251 union ehci_shadow *q = &ehci->pshadow [frame];
252 unsigned char uf;
254 memset(tt_usecs, 0, 16);
256 while (q->ptr) {
257 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
258 case Q_TYPE_ITD:
259 hw_p = &q->itd->hw_next;
260 q = &q->itd->itd_next;
261 continue;
262 case Q_TYPE_QH:
263 if (same_tt(dev, q->qh->dev)) {
264 uf = tt_start_uframe(ehci, q->qh->hw->hw_info2);
265 tt_usecs[uf] += q->qh->tt_usecs;
267 hw_p = &q->qh->hw->hw_next;
268 q = &q->qh->qh_next;
269 continue;
270 case Q_TYPE_SITD:
271 if (same_tt(dev, q->sitd->urb->dev)) {
272 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
273 tt_usecs[uf] += q->sitd->stream->tt_usecs;
275 hw_p = &q->sitd->hw_next;
276 q = &q->sitd->sitd_next;
277 continue;
278 // case Q_TYPE_FSTN:
279 default:
280 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
281 frame);
282 hw_p = &q->fstn->hw_next;
283 q = &q->fstn->fstn_next;
287 carryover_tt_bandwidth(tt_usecs);
289 if (max_tt_usecs[7] < tt_usecs[7])
290 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
291 frame, tt_usecs[7] - max_tt_usecs[7]);
295 * Return true if the device's tt's downstream bus is available for a
296 * periodic transfer of the specified length (usecs), starting at the
297 * specified frame/uframe. Note that (as summarized in section 11.19
298 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
299 * uframe.
301 * The uframe parameter is when the fullspeed/lowspeed transfer
302 * should be executed in "B-frame" terms, which is the same as the
303 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
304 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
305 * See the EHCI spec sec 4.5 and fig 4.7.
307 * This checks if the full/lowspeed bus, at the specified starting uframe,
308 * has the specified bandwidth available, according to rules listed
309 * in USB 2.0 spec section 11.18.1 fig 11-60.
311 * This does not check if the transfer would exceed the max ssplit
312 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
313 * since proper scheduling limits ssplits to less than 16 per uframe.
315 static int tt_available (
316 struct ehci_hcd *ehci,
317 unsigned period,
318 struct usb_device *dev,
319 unsigned frame,
320 unsigned uframe,
321 u16 usecs
324 if ((period == 0) || (uframe >= 7)) /* error */
325 return 0;
327 for (; frame < ehci->periodic_size; frame += period) {
328 unsigned short tt_usecs[8];
330 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
332 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
333 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
334 frame, usecs, uframe,
335 tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
336 tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
338 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
339 ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
340 frame, uframe);
341 return 0;
344 /* special case for isoc transfers larger than 125us:
345 * the first and each subsequent fully used uframe
346 * must be empty, so as to not illegally delay
347 * already scheduled transactions
349 if (125 < usecs) {
350 int ufs = (usecs / 125);
351 int i;
352 for (i = uframe; i < (uframe + ufs) && i < 8; i++)
353 if (0 < tt_usecs[i]) {
354 ehci_vdbg(ehci,
355 "multi-uframe xfer can't fit "
356 "in frame %d uframe %d\n",
357 frame, i);
358 return 0;
362 tt_usecs[uframe] += usecs;
364 carryover_tt_bandwidth(tt_usecs);
366 /* fail if the carryover pushed bw past the last uframe's limit */
367 if (max_tt_usecs[7] < tt_usecs[7]) {
368 ehci_vdbg(ehci,
369 "tt unavailable usecs %d frame %d uframe %d\n",
370 usecs, frame, uframe);
371 return 0;
375 return 1;
378 #else
380 /* return true iff the device's transaction translator is available
381 * for a periodic transfer starting at the specified frame, using
382 * all the uframes in the mask.
384 static int tt_no_collision (
385 struct ehci_hcd *ehci,
386 unsigned period,
387 struct usb_device *dev,
388 unsigned frame,
389 u32 uf_mask
392 if (period == 0) /* error */
393 return 0;
395 /* note bandwidth wastage: split never follows csplit
396 * (different dev or endpoint) until the next uframe.
397 * calling convention doesn't make that distinction.
399 for (; frame < ehci->periodic_size; frame += period) {
400 union ehci_shadow here;
401 __hc32 type;
402 struct ehci_qh_hw *hw;
404 here = ehci->pshadow [frame];
405 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
406 while (here.ptr) {
407 switch (hc32_to_cpu(ehci, type)) {
408 case Q_TYPE_ITD:
409 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
410 here = here.itd->itd_next;
411 continue;
412 case Q_TYPE_QH:
413 hw = here.qh->hw;
414 if (same_tt (dev, here.qh->dev)) {
415 u32 mask;
417 mask = hc32_to_cpu(ehci,
418 hw->hw_info2);
419 /* "knows" no gap is needed */
420 mask |= mask >> 8;
421 if (mask & uf_mask)
422 break;
424 type = Q_NEXT_TYPE(ehci, hw->hw_next);
425 here = here.qh->qh_next;
426 continue;
427 case Q_TYPE_SITD:
428 if (same_tt (dev, here.sitd->urb->dev)) {
429 u16 mask;
431 mask = hc32_to_cpu(ehci, here.sitd
432 ->hw_uframe);
433 /* FIXME assumes no gap for IN! */
434 mask |= mask >> 8;
435 if (mask & uf_mask)
436 break;
438 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
439 here = here.sitd->sitd_next;
440 continue;
441 // case Q_TYPE_FSTN:
442 default:
443 ehci_dbg (ehci,
444 "periodic frame %d bogus type %d\n",
445 frame, type);
448 /* collision or error */
449 return 0;
453 /* no collision */
454 return 1;
457 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
459 /*-------------------------------------------------------------------------*/
461 static int enable_periodic (struct ehci_hcd *ehci)
463 u32 cmd;
464 int status;
466 if (ehci->periodic_sched++)
467 return 0;
469 /* did clearing PSE did take effect yet?
470 * takes effect only at frame boundaries...
472 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
473 STS_PSS, 0, 9 * 125);
474 if (status)
475 return status;
477 cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
478 ehci_writel(ehci, cmd, &ehci->regs->command);
479 /* posted write ... PSS happens later */
480 ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
482 /* make sure ehci_work scans these */
483 ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
484 % (ehci->periodic_size << 3);
485 if (unlikely(ehci->broken_periodic))
486 ehci->last_periodic_enable = ktime_get_real();
487 return 0;
490 static int disable_periodic (struct ehci_hcd *ehci)
492 u32 cmd;
493 int status;
495 if (--ehci->periodic_sched)
496 return 0;
498 if (unlikely(ehci->broken_periodic)) {
499 /* delay experimentally determined */
500 ktime_t safe = ktime_add_us(ehci->last_periodic_enable, 1000);
501 ktime_t now = ktime_get_real();
502 s64 delay = ktime_us_delta(safe, now);
504 if (unlikely(delay > 0))
505 udelay(delay);
508 /* did setting PSE not take effect yet?
509 * takes effect only at frame boundaries...
511 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
512 STS_PSS, STS_PSS, 9 * 125);
513 if (status)
514 return status;
516 cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
517 ehci_writel(ehci, cmd, &ehci->regs->command);
518 /* posted write ... */
520 free_cached_lists(ehci);
522 ehci->next_uframe = -1;
523 return 0;
526 /*-------------------------------------------------------------------------*/
528 /* periodic schedule slots have iso tds (normal or split) first, then a
529 * sparse tree for active interrupt transfers.
531 * this just links in a qh; caller guarantees uframe masks are set right.
532 * no FSTN support (yet; ehci 0.96+)
534 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
536 unsigned i;
537 unsigned period = qh->period;
539 dev_dbg (&qh->dev->dev,
540 "link qh%d-%04x/%p start %d [%d/%d us]\n",
541 period, hc32_to_cpup(ehci, &qh->hw->hw_info2)
542 & (QH_CMASK | QH_SMASK),
543 qh, qh->start, qh->usecs, qh->c_usecs);
545 /* high bandwidth, or otherwise every microframe */
546 if (period == 0)
547 period = 1;
549 for (i = qh->start; i < ehci->periodic_size; i += period) {
550 union ehci_shadow *prev = &ehci->pshadow[i];
551 __hc32 *hw_p = &ehci->periodic[i];
552 union ehci_shadow here = *prev;
553 __hc32 type = 0;
555 /* skip the iso nodes at list head */
556 while (here.ptr) {
557 type = Q_NEXT_TYPE(ehci, *hw_p);
558 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
559 break;
560 prev = periodic_next_shadow(ehci, prev, type);
561 hw_p = shadow_next_periodic(ehci, &here, type);
562 here = *prev;
565 /* sorting each branch by period (slow-->fast)
566 * enables sharing interior tree nodes
568 while (here.ptr && qh != here.qh) {
569 if (qh->period > here.qh->period)
570 break;
571 prev = &here.qh->qh_next;
572 hw_p = &here.qh->hw->hw_next;
573 here = *prev;
575 /* link in this qh, unless some earlier pass did that */
576 if (qh != here.qh) {
577 qh->qh_next = here;
578 if (here.qh)
579 qh->hw->hw_next = *hw_p;
580 wmb ();
581 prev->qh = qh;
582 *hw_p = QH_NEXT (ehci, qh->qh_dma);
585 qh->qh_state = QH_STATE_LINKED;
586 qh->xacterrs = 0;
587 qh_get (qh);
589 /* update per-qh bandwidth for usbfs */
590 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
591 ? ((qh->usecs + qh->c_usecs) / qh->period)
592 : (qh->usecs * 8);
594 /* maybe enable periodic schedule processing */
595 return enable_periodic(ehci);
598 static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
600 unsigned i;
601 unsigned period;
603 // FIXME:
604 // IF this isn't high speed
605 // and this qh is active in the current uframe
606 // (and overlay token SplitXstate is false?)
607 // THEN
608 // qh->hw_info1 |= __constant_cpu_to_hc32(1 << 7 /* "ignore" */);
610 /* high bandwidth, or otherwise part of every microframe */
611 if ((period = qh->period) == 0)
612 period = 1;
614 for (i = qh->start; i < ehci->periodic_size; i += period)
615 periodic_unlink (ehci, i, qh);
617 /* update per-qh bandwidth for usbfs */
618 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
619 ? ((qh->usecs + qh->c_usecs) / qh->period)
620 : (qh->usecs * 8);
622 dev_dbg (&qh->dev->dev,
623 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
624 qh->period,
625 hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK),
626 qh, qh->start, qh->usecs, qh->c_usecs);
628 /* qh->qh_next still "live" to HC */
629 qh->qh_state = QH_STATE_UNLINK;
630 qh->qh_next.ptr = NULL;
631 qh_put (qh);
633 /* maybe turn off periodic schedule */
634 return disable_periodic(ehci);
637 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
639 unsigned wait;
640 struct ehci_qh_hw *hw = qh->hw;
641 int rc;
643 /* If the QH isn't linked then there's nothing we can do
644 * unless we were called during a giveback, in which case
645 * qh_completions() has to deal with it.
647 if (qh->qh_state != QH_STATE_LINKED) {
648 if (qh->qh_state == QH_STATE_COMPLETING)
649 qh->needs_rescan = 1;
650 return;
653 qh_unlink_periodic (ehci, qh);
655 /* simple/paranoid: always delay, expecting the HC needs to read
656 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
657 * expect khubd to clean up after any CSPLITs we won't issue.
658 * active high speed queues may need bigger delays...
660 if (list_empty (&qh->qtd_list)
661 || (cpu_to_hc32(ehci, QH_CMASK)
662 & hw->hw_info2) != 0)
663 wait = 2;
664 else
665 wait = 55; /* worst case: 3 * 1024 */
667 udelay (wait);
668 qh->qh_state = QH_STATE_IDLE;
669 hw->hw_next = EHCI_LIST_END(ehci);
670 wmb ();
672 qh_completions(ehci, qh);
674 /* reschedule QH iff another request is queued */
675 if (!list_empty(&qh->qtd_list) &&
676 HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
677 rc = qh_schedule(ehci, qh);
679 /* An error here likely indicates handshake failure
680 * or no space left in the schedule. Neither fault
681 * should happen often ...
683 * FIXME kill the now-dysfunctional queued urbs
685 if (rc != 0)
686 ehci_err(ehci, "can't reschedule qh %p, err %d\n",
687 qh, rc);
691 /*-------------------------------------------------------------------------*/
693 static int check_period (
694 struct ehci_hcd *ehci,
695 unsigned frame,
696 unsigned uframe,
697 unsigned period,
698 unsigned usecs
700 int claimed;
702 /* complete split running into next frame?
703 * given FSTN support, we could sometimes check...
705 if (uframe >= 8)
706 return 0;
709 * 80% periodic == 100 usec/uframe available
710 * convert "usecs we need" to "max already claimed"
712 usecs = 100 - usecs;
714 /* we "know" 2 and 4 uframe intervals were rejected; so
715 * for period 0, check _every_ microframe in the schedule.
717 if (unlikely (period == 0)) {
718 do {
719 for (uframe = 0; uframe < 7; uframe++) {
720 claimed = periodic_usecs (ehci, frame, uframe);
721 if (claimed > usecs)
722 return 0;
724 } while ((frame += 1) < ehci->periodic_size);
726 /* just check the specified uframe, at that period */
727 } else {
728 do {
729 claimed = periodic_usecs (ehci, frame, uframe);
730 if (claimed > usecs)
731 return 0;
732 } while ((frame += period) < ehci->periodic_size);
735 // success!
736 return 1;
739 static int check_intr_schedule (
740 struct ehci_hcd *ehci,
741 unsigned frame,
742 unsigned uframe,
743 const struct ehci_qh *qh,
744 __hc32 *c_maskp
747 int retval = -ENOSPC;
748 u8 mask = 0;
750 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
751 goto done;
753 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
754 goto done;
755 if (!qh->c_usecs) {
756 retval = 0;
757 *c_maskp = 0;
758 goto done;
761 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
762 if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
763 qh->tt_usecs)) {
764 unsigned i;
766 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
767 for (i=uframe+1; i<8 && i<uframe+4; i++)
768 if (!check_period (ehci, frame, i,
769 qh->period, qh->c_usecs))
770 goto done;
771 else
772 mask |= 1 << i;
774 retval = 0;
776 *c_maskp = cpu_to_hc32(ehci, mask << 8);
778 #else
779 /* Make sure this tt's buffer is also available for CSPLITs.
780 * We pessimize a bit; probably the typical full speed case
781 * doesn't need the second CSPLIT.
783 * NOTE: both SPLIT and CSPLIT could be checked in just
784 * one smart pass...
786 mask = 0x03 << (uframe + qh->gap_uf);
787 *c_maskp = cpu_to_hc32(ehci, mask << 8);
789 mask |= 1 << uframe;
790 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
791 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
792 qh->period, qh->c_usecs))
793 goto done;
794 if (!check_period (ehci, frame, uframe + qh->gap_uf,
795 qh->period, qh->c_usecs))
796 goto done;
797 retval = 0;
799 #endif
800 done:
801 return retval;
804 /* "first fit" scheduling policy used the first time through,
805 * or when the previous schedule slot can't be re-used.
807 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
809 int status;
810 unsigned uframe;
811 __hc32 c_mask;
812 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
813 struct ehci_qh_hw *hw = qh->hw;
815 qh_refresh(ehci, qh);
816 hw->hw_next = EHCI_LIST_END(ehci);
817 frame = qh->start;
819 /* reuse the previous schedule slots, if we can */
820 if (frame < qh->period) {
821 uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK);
822 status = check_intr_schedule (ehci, frame, --uframe,
823 qh, &c_mask);
824 } else {
825 uframe = 0;
826 c_mask = 0;
827 status = -ENOSPC;
830 /* else scan the schedule to find a group of slots such that all
831 * uframes have enough periodic bandwidth available.
833 if (status) {
834 /* "normal" case, uframing flexible except with splits */
835 if (qh->period) {
836 int i;
838 for (i = qh->period; status && i > 0; --i) {
839 frame = ++ehci->random_frame % qh->period;
840 for (uframe = 0; uframe < 8; uframe++) {
841 status = check_intr_schedule (ehci,
842 frame, uframe, qh,
843 &c_mask);
844 if (status == 0)
845 break;
849 /* qh->period == 0 means every uframe */
850 } else {
851 frame = 0;
852 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
854 if (status)
855 goto done;
856 qh->start = frame;
858 /* reset S-frame and (maybe) C-frame masks */
859 hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
860 hw->hw_info2 |= qh->period
861 ? cpu_to_hc32(ehci, 1 << uframe)
862 : cpu_to_hc32(ehci, QH_SMASK);
863 hw->hw_info2 |= c_mask;
864 } else
865 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
867 /* stuff into the periodic schedule */
868 status = qh_link_periodic (ehci, qh);
869 done:
870 return status;
873 static int intr_submit (
874 struct ehci_hcd *ehci,
875 struct urb *urb,
876 struct list_head *qtd_list,
877 gfp_t mem_flags
879 unsigned epnum;
880 unsigned long flags;
881 struct ehci_qh *qh;
882 int status;
883 struct list_head empty;
885 /* get endpoint and transfer/schedule data */
886 epnum = urb->ep->desc.bEndpointAddress;
888 spin_lock_irqsave (&ehci->lock, flags);
890 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
891 &ehci_to_hcd(ehci)->flags))) {
892 status = -ESHUTDOWN;
893 goto done_not_linked;
895 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
896 if (unlikely(status))
897 goto done_not_linked;
899 /* get qh and force any scheduling errors */
900 INIT_LIST_HEAD (&empty);
901 qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
902 if (qh == NULL) {
903 status = -ENOMEM;
904 goto done;
906 if (qh->qh_state == QH_STATE_IDLE) {
907 if ((status = qh_schedule (ehci, qh)) != 0)
908 goto done;
911 /* then queue the urb's tds to the qh */
912 qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
913 BUG_ON (qh == NULL);
915 /* ... update usbfs periodic stats */
916 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
918 done:
919 if (unlikely(status))
920 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
921 done_not_linked:
922 spin_unlock_irqrestore (&ehci->lock, flags);
923 if (status)
924 qtd_list_free (ehci, urb, qtd_list);
926 return status;
929 /*-------------------------------------------------------------------------*/
931 /* ehci_iso_stream ops work with both ITD and SITD */
933 static struct ehci_iso_stream *
934 iso_stream_alloc (gfp_t mem_flags)
936 struct ehci_iso_stream *stream;
938 stream = kzalloc(sizeof *stream, mem_flags);
939 if (likely (stream != NULL)) {
940 INIT_LIST_HEAD(&stream->td_list);
941 INIT_LIST_HEAD(&stream->free_list);
942 stream->next_uframe = -1;
943 stream->refcount = 1;
945 return stream;
948 static void
949 iso_stream_init (
950 struct ehci_hcd *ehci,
951 struct ehci_iso_stream *stream,
952 struct usb_device *dev,
953 int pipe,
954 unsigned interval
957 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
959 u32 buf1;
960 unsigned epnum, maxp;
961 int is_input;
962 long bandwidth;
965 * this might be a "high bandwidth" highspeed endpoint,
966 * as encoded in the ep descriptor's wMaxPacket field
968 epnum = usb_pipeendpoint (pipe);
969 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
970 maxp = usb_maxpacket(dev, pipe, !is_input);
971 if (is_input) {
972 buf1 = (1 << 11);
973 } else {
974 buf1 = 0;
977 /* knows about ITD vs SITD */
978 if (dev->speed == USB_SPEED_HIGH) {
979 unsigned multi = hb_mult(maxp);
981 stream->highspeed = 1;
983 maxp = max_packet(maxp);
984 buf1 |= maxp;
985 maxp *= multi;
987 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
988 stream->buf1 = cpu_to_hc32(ehci, buf1);
989 stream->buf2 = cpu_to_hc32(ehci, multi);
991 /* usbfs wants to report the average usecs per frame tied up
992 * when transfers on this endpoint are scheduled ...
994 stream->usecs = HS_USECS_ISO (maxp);
995 bandwidth = stream->usecs * 8;
996 bandwidth /= interval;
998 } else {
999 u32 addr;
1000 int think_time;
1001 int hs_transfers;
1003 addr = dev->ttport << 24;
1004 if (!ehci_is_TDI(ehci)
1005 || (dev->tt->hub !=
1006 ehci_to_hcd(ehci)->self.root_hub))
1007 addr |= dev->tt->hub->devnum << 16;
1008 addr |= epnum << 8;
1009 addr |= dev->devnum;
1010 stream->usecs = HS_USECS_ISO (maxp);
1011 think_time = dev->tt ? dev->tt->think_time : 0;
1012 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
1013 dev->speed, is_input, 1, maxp));
1014 hs_transfers = max (1u, (maxp + 187) / 188);
1015 if (is_input) {
1016 u32 tmp;
1018 addr |= 1 << 31;
1019 stream->c_usecs = stream->usecs;
1020 stream->usecs = HS_USECS_ISO (1);
1021 stream->raw_mask = 1;
1023 /* c-mask as specified in USB 2.0 11.18.4 3.c */
1024 tmp = (1 << (hs_transfers + 2)) - 1;
1025 stream->raw_mask |= tmp << (8 + 2);
1026 } else
1027 stream->raw_mask = smask_out [hs_transfers - 1];
1028 bandwidth = stream->usecs + stream->c_usecs;
1029 bandwidth /= interval << 3;
1031 /* stream->splits gets created from raw_mask later */
1032 stream->address = cpu_to_hc32(ehci, addr);
1034 stream->bandwidth = bandwidth;
1036 stream->udev = dev;
1038 stream->bEndpointAddress = is_input | epnum;
1039 stream->interval = interval;
1040 stream->maxp = maxp;
1043 static void
1044 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1046 stream->refcount--;
1048 /* free whenever just a dev->ep reference remains.
1049 * not like a QH -- no persistent state (toggle, halt)
1051 if (stream->refcount == 1) {
1052 // BUG_ON (!list_empty(&stream->td_list));
1054 while (!list_empty (&stream->free_list)) {
1055 struct list_head *entry;
1057 entry = stream->free_list.next;
1058 list_del (entry);
1060 /* knows about ITD vs SITD */
1061 if (stream->highspeed) {
1062 struct ehci_itd *itd;
1064 itd = list_entry (entry, struct ehci_itd,
1065 itd_list);
1066 dma_pool_free (ehci->itd_pool, itd,
1067 itd->itd_dma);
1068 } else {
1069 struct ehci_sitd *sitd;
1071 sitd = list_entry (entry, struct ehci_sitd,
1072 sitd_list);
1073 dma_pool_free (ehci->sitd_pool, sitd,
1074 sitd->sitd_dma);
1078 stream->bEndpointAddress &= 0x0f;
1079 if (stream->ep)
1080 stream->ep->hcpriv = NULL;
1082 kfree(stream);
1086 static inline struct ehci_iso_stream *
1087 iso_stream_get (struct ehci_iso_stream *stream)
1089 if (likely (stream != NULL))
1090 stream->refcount++;
1091 return stream;
1094 static struct ehci_iso_stream *
1095 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1097 unsigned epnum;
1098 struct ehci_iso_stream *stream;
1099 struct usb_host_endpoint *ep;
1100 unsigned long flags;
1102 epnum = usb_pipeendpoint (urb->pipe);
1103 if (usb_pipein(urb->pipe))
1104 ep = urb->dev->ep_in[epnum];
1105 else
1106 ep = urb->dev->ep_out[epnum];
1108 spin_lock_irqsave (&ehci->lock, flags);
1109 stream = ep->hcpriv;
1111 if (unlikely (stream == NULL)) {
1112 stream = iso_stream_alloc(GFP_ATOMIC);
1113 if (likely (stream != NULL)) {
1114 /* dev->ep owns the initial refcount */
1115 ep->hcpriv = stream;
1116 stream->ep = ep;
1117 iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1118 urb->interval);
1121 /* if dev->ep [epnum] is a QH, hw is set */
1122 } else if (unlikely (stream->hw != NULL)) {
1123 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1124 urb->dev->devpath, epnum,
1125 usb_pipein(urb->pipe) ? "in" : "out");
1126 stream = NULL;
1129 /* caller guarantees an eventual matching iso_stream_put */
1130 stream = iso_stream_get (stream);
1132 spin_unlock_irqrestore (&ehci->lock, flags);
1133 return stream;
1136 /*-------------------------------------------------------------------------*/
1138 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1140 static struct ehci_iso_sched *
1141 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1143 struct ehci_iso_sched *iso_sched;
1144 int size = sizeof *iso_sched;
1146 size += packets * sizeof (struct ehci_iso_packet);
1147 iso_sched = kzalloc(size, mem_flags);
1148 if (likely (iso_sched != NULL)) {
1149 INIT_LIST_HEAD (&iso_sched->td_list);
1151 return iso_sched;
1154 static inline void
1155 itd_sched_init(
1156 struct ehci_hcd *ehci,
1157 struct ehci_iso_sched *iso_sched,
1158 struct ehci_iso_stream *stream,
1159 struct urb *urb
1162 unsigned i;
1163 dma_addr_t dma = urb->transfer_dma;
1165 /* how many uframes are needed for these transfers */
1166 iso_sched->span = urb->number_of_packets * stream->interval;
1168 /* figure out per-uframe itd fields that we'll need later
1169 * when we fit new itds into the schedule.
1171 for (i = 0; i < urb->number_of_packets; i++) {
1172 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
1173 unsigned length;
1174 dma_addr_t buf;
1175 u32 trans;
1177 length = urb->iso_frame_desc [i].length;
1178 buf = dma + urb->iso_frame_desc [i].offset;
1180 trans = EHCI_ISOC_ACTIVE;
1181 trans |= buf & 0x0fff;
1182 if (unlikely (((i + 1) == urb->number_of_packets))
1183 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1184 trans |= EHCI_ITD_IOC;
1185 trans |= length << 16;
1186 uframe->transaction = cpu_to_hc32(ehci, trans);
1188 /* might need to cross a buffer page within a uframe */
1189 uframe->bufp = (buf & ~(u64)0x0fff);
1190 buf += length;
1191 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1192 uframe->cross = 1;
1196 static void
1197 iso_sched_free (
1198 struct ehci_iso_stream *stream,
1199 struct ehci_iso_sched *iso_sched
1202 if (!iso_sched)
1203 return;
1204 // caller must hold ehci->lock!
1205 list_splice (&iso_sched->td_list, &stream->free_list);
1206 kfree (iso_sched);
1209 static int
1210 itd_urb_transaction (
1211 struct ehci_iso_stream *stream,
1212 struct ehci_hcd *ehci,
1213 struct urb *urb,
1214 gfp_t mem_flags
1217 struct ehci_itd *itd;
1218 dma_addr_t itd_dma;
1219 int i;
1220 unsigned num_itds;
1221 struct ehci_iso_sched *sched;
1222 unsigned long flags;
1224 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1225 if (unlikely (sched == NULL))
1226 return -ENOMEM;
1228 itd_sched_init(ehci, sched, stream, urb);
1230 if (urb->interval < 8)
1231 num_itds = 1 + (sched->span + 7) / 8;
1232 else
1233 num_itds = urb->number_of_packets;
1235 /* allocate/init ITDs */
1236 spin_lock_irqsave (&ehci->lock, flags);
1237 for (i = 0; i < num_itds; i++) {
1239 /* free_list.next might be cache-hot ... but maybe
1240 * the HC caches it too. avoid that issue for now.
1243 /* prefer previously-allocated itds */
1244 if (likely (!list_empty(&stream->free_list))) {
1245 itd = list_entry (stream->free_list.prev,
1246 struct ehci_itd, itd_list);
1247 list_del (&itd->itd_list);
1248 itd_dma = itd->itd_dma;
1249 } else {
1250 spin_unlock_irqrestore (&ehci->lock, flags);
1251 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1252 &itd_dma);
1253 spin_lock_irqsave (&ehci->lock, flags);
1254 if (!itd) {
1255 iso_sched_free(stream, sched);
1256 spin_unlock_irqrestore(&ehci->lock, flags);
1257 return -ENOMEM;
1261 memset (itd, 0, sizeof *itd);
1262 itd->itd_dma = itd_dma;
1263 list_add (&itd->itd_list, &sched->td_list);
1265 spin_unlock_irqrestore (&ehci->lock, flags);
1267 /* temporarily store schedule info in hcpriv */
1268 urb->hcpriv = sched;
1269 urb->error_count = 0;
1270 return 0;
1273 /*-------------------------------------------------------------------------*/
1275 static inline int
1276 itd_slot_ok (
1277 struct ehci_hcd *ehci,
1278 u32 mod,
1279 u32 uframe,
1280 u8 usecs,
1281 u32 period
1284 uframe %= period;
1285 do {
1286 /* can't commit more than 80% periodic == 100 usec */
1287 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1288 > (100 - usecs))
1289 return 0;
1291 /* we know urb->interval is 2^N uframes */
1292 uframe += period;
1293 } while (uframe < mod);
1294 return 1;
1297 static inline int
1298 sitd_slot_ok (
1299 struct ehci_hcd *ehci,
1300 u32 mod,
1301 struct ehci_iso_stream *stream,
1302 u32 uframe,
1303 struct ehci_iso_sched *sched,
1304 u32 period_uframes
1307 u32 mask, tmp;
1308 u32 frame, uf;
1310 mask = stream->raw_mask << (uframe & 7);
1312 /* for IN, don't wrap CSPLIT into the next frame */
1313 if (mask & ~0xffff)
1314 return 0;
1316 /* this multi-pass logic is simple, but performance may
1317 * suffer when the schedule data isn't cached.
1320 /* check bandwidth */
1321 uframe %= period_uframes;
1322 do {
1323 u32 max_used;
1325 frame = uframe >> 3;
1326 uf = uframe & 7;
1328 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1329 /* The tt's fullspeed bus bandwidth must be available.
1330 * tt_available scheduling guarantees 10+% for control/bulk.
1332 if (!tt_available (ehci, period_uframes << 3,
1333 stream->udev, frame, uf, stream->tt_usecs))
1334 return 0;
1335 #else
1336 /* tt must be idle for start(s), any gap, and csplit.
1337 * assume scheduling slop leaves 10+% for control/bulk.
1339 if (!tt_no_collision (ehci, period_uframes << 3,
1340 stream->udev, frame, mask))
1341 return 0;
1342 #endif
1344 /* check starts (OUT uses more than one) */
1345 max_used = 100 - stream->usecs;
1346 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1347 if (periodic_usecs (ehci, frame, uf) > max_used)
1348 return 0;
1351 /* for IN, check CSPLIT */
1352 if (stream->c_usecs) {
1353 uf = uframe & 7;
1354 max_used = 100 - stream->c_usecs;
1355 do {
1356 tmp = 1 << uf;
1357 tmp <<= 8;
1358 if ((stream->raw_mask & tmp) == 0)
1359 continue;
1360 if (periodic_usecs (ehci, frame, uf)
1361 > max_used)
1362 return 0;
1363 } while (++uf < 8);
1366 /* we know urb->interval is 2^N uframes */
1367 uframe += period_uframes;
1368 } while (uframe < mod);
1370 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1371 return 1;
1375 * This scheduler plans almost as far into the future as it has actual
1376 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1377 * "as small as possible" to be cache-friendlier.) That limits the size
1378 * transfers you can stream reliably; avoid more than 64 msec per urb.
1379 * Also avoid queue depths of less than ehci's worst irq latency (affected
1380 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1381 * and other factors); or more than about 230 msec total (for portability,
1382 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1385 #define SCHEDULE_SLOP 80 /* microframes */
1387 static int
1388 iso_stream_schedule (
1389 struct ehci_hcd *ehci,
1390 struct urb *urb,
1391 struct ehci_iso_stream *stream
1394 u32 now, next, start, period, span;
1395 int status;
1396 unsigned mod = ehci->periodic_size << 3;
1397 struct ehci_iso_sched *sched = urb->hcpriv;
1399 period = urb->interval;
1400 span = sched->span;
1401 if (!stream->highspeed) {
1402 period <<= 3;
1403 span <<= 3;
1406 if (span > mod - SCHEDULE_SLOP) {
1407 ehci_dbg (ehci, "iso request %p too long\n", urb);
1408 status = -EFBIG;
1409 goto fail;
1412 now = ehci_readl(ehci, &ehci->regs->frame_index) & (mod - 1);
1414 /* Typical case: reuse current schedule, stream is still active.
1415 * Hopefully there are no gaps from the host falling behind
1416 * (irq delays etc), but if there are we'll take the next
1417 * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1419 if (likely (!list_empty (&stream->td_list))) {
1420 u32 excess;
1422 /* For high speed devices, allow scheduling within the
1423 * isochronous scheduling threshold. For full speed devices
1424 * and Intel PCI-based controllers, don't (work around for
1425 * Intel ICH9 bug).
1427 if (!stream->highspeed && ehci->fs_i_thresh)
1428 next = now + ehci->i_thresh;
1429 else
1430 next = now;
1432 /* Fell behind (by up to twice the slop amount)?
1433 * We decide based on the time of the last currently-scheduled
1434 * slot, not the time of the next available slot.
1436 excess = (stream->next_uframe - period - next) & (mod - 1);
1437 if (excess >= mod - 2 * SCHEDULE_SLOP)
1438 start = next + excess - mod + period *
1439 DIV_ROUND_UP(mod - excess, period);
1440 else
1441 start = next + excess + period;
1442 if (start - now >= mod) {
1443 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1444 urb, start - now - period, period,
1445 mod);
1446 status = -EFBIG;
1447 goto fail;
1451 /* need to schedule; when's the next (u)frame we could start?
1452 * this is bigger than ehci->i_thresh allows; scheduling itself
1453 * isn't free, the slop should handle reasonably slow cpus. it
1454 * can also help high bandwidth if the dma and irq loads don't
1455 * jump until after the queue is primed.
1457 else {
1458 start = SCHEDULE_SLOP + (now & ~0x07);
1460 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1462 /* find a uframe slot with enough bandwidth */
1463 next = start + period;
1464 for (; start < next; start++) {
1466 /* check schedule: enough space? */
1467 if (stream->highspeed) {
1468 if (itd_slot_ok(ehci, mod, start,
1469 stream->usecs, period))
1470 break;
1471 } else {
1472 if ((start % 8) >= 6)
1473 continue;
1474 if (sitd_slot_ok(ehci, mod, stream,
1475 start, sched, period))
1476 break;
1480 /* no room in the schedule */
1481 if (start == next) {
1482 ehci_dbg(ehci, "iso resched full %p (now %d max %d)\n",
1483 urb, now, now + mod);
1484 status = -ENOSPC;
1485 goto fail;
1489 /* Tried to schedule too far into the future? */
1490 if (unlikely(start - now + span - period
1491 >= mod - 2 * SCHEDULE_SLOP)) {
1492 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1493 urb, start - now, span - period,
1494 mod - 2 * SCHEDULE_SLOP);
1495 status = -EFBIG;
1496 goto fail;
1499 stream->next_uframe = start & (mod - 1);
1501 /* report high speed start in uframes; full speed, in frames */
1502 urb->start_frame = stream->next_uframe;
1503 if (!stream->highspeed)
1504 urb->start_frame >>= 3;
1505 return 0;
1507 fail:
1508 iso_sched_free(stream, sched);
1509 urb->hcpriv = NULL;
1510 return status;
1513 /*-------------------------------------------------------------------------*/
1515 static inline void
1516 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1517 struct ehci_itd *itd)
1519 int i;
1521 /* it's been recently zeroed */
1522 itd->hw_next = EHCI_LIST_END(ehci);
1523 itd->hw_bufp [0] = stream->buf0;
1524 itd->hw_bufp [1] = stream->buf1;
1525 itd->hw_bufp [2] = stream->buf2;
1527 for (i = 0; i < 8; i++)
1528 itd->index[i] = -1;
1530 /* All other fields are filled when scheduling */
1533 static inline void
1534 itd_patch(
1535 struct ehci_hcd *ehci,
1536 struct ehci_itd *itd,
1537 struct ehci_iso_sched *iso_sched,
1538 unsigned index,
1539 u16 uframe
1542 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1543 unsigned pg = itd->pg;
1545 // BUG_ON (pg == 6 && uf->cross);
1547 uframe &= 0x07;
1548 itd->index [uframe] = index;
1550 itd->hw_transaction[uframe] = uf->transaction;
1551 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1552 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1553 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1555 /* iso_frame_desc[].offset must be strictly increasing */
1556 if (unlikely (uf->cross)) {
1557 u64 bufp = uf->bufp + 4096;
1559 itd->pg = ++pg;
1560 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1561 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1565 static inline void
1566 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1568 union ehci_shadow *prev = &ehci->pshadow[frame];
1569 __hc32 *hw_p = &ehci->periodic[frame];
1570 union ehci_shadow here = *prev;
1571 __hc32 type = 0;
1573 /* skip any iso nodes which might belong to previous microframes */
1574 while (here.ptr) {
1575 type = Q_NEXT_TYPE(ehci, *hw_p);
1576 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1577 break;
1578 prev = periodic_next_shadow(ehci, prev, type);
1579 hw_p = shadow_next_periodic(ehci, &here, type);
1580 here = *prev;
1583 itd->itd_next = here;
1584 itd->hw_next = *hw_p;
1585 prev->itd = itd;
1586 itd->frame = frame;
1587 wmb ();
1588 *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1591 /* fit urb's itds into the selected schedule slot; activate as needed */
1592 static int
1593 itd_link_urb (
1594 struct ehci_hcd *ehci,
1595 struct urb *urb,
1596 unsigned mod,
1597 struct ehci_iso_stream *stream
1600 int packet;
1601 unsigned next_uframe, uframe, frame;
1602 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1603 struct ehci_itd *itd;
1605 next_uframe = stream->next_uframe & (mod - 1);
1607 if (unlikely (list_empty(&stream->td_list))) {
1608 ehci_to_hcd(ehci)->self.bandwidth_allocated
1609 += stream->bandwidth;
1610 ehci_vdbg (ehci,
1611 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1612 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1613 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1614 urb->interval,
1615 next_uframe >> 3, next_uframe & 0x7);
1617 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1619 /* fill iTDs uframe by uframe */
1620 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1621 if (itd == NULL) {
1622 /* ASSERT: we have all necessary itds */
1623 // BUG_ON (list_empty (&iso_sched->td_list));
1625 /* ASSERT: no itds for this endpoint in this uframe */
1627 itd = list_entry (iso_sched->td_list.next,
1628 struct ehci_itd, itd_list);
1629 list_move_tail (&itd->itd_list, &stream->td_list);
1630 itd->stream = iso_stream_get (stream);
1631 itd->urb = urb;
1632 itd_init (ehci, stream, itd);
1635 uframe = next_uframe & 0x07;
1636 frame = next_uframe >> 3;
1638 itd_patch(ehci, itd, iso_sched, packet, uframe);
1640 next_uframe += stream->interval;
1641 next_uframe &= mod - 1;
1642 packet++;
1644 /* link completed itds into the schedule */
1645 if (((next_uframe >> 3) != frame)
1646 || packet == urb->number_of_packets) {
1647 itd_link(ehci, frame & (ehci->periodic_size - 1), itd);
1648 itd = NULL;
1651 stream->next_uframe = next_uframe;
1653 /* don't need that schedule data any more */
1654 iso_sched_free (stream, iso_sched);
1655 urb->hcpriv = NULL;
1657 timer_action (ehci, TIMER_IO_WATCHDOG);
1658 return enable_periodic(ehci);
1661 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1663 /* Process and recycle a completed ITD. Return true iff its urb completed,
1664 * and hence its completion callback probably added things to the hardware
1665 * schedule.
1667 * Note that we carefully avoid recycling this descriptor until after any
1668 * completion callback runs, so that it won't be reused quickly. That is,
1669 * assuming (a) no more than two urbs per frame on this endpoint, and also
1670 * (b) only this endpoint's completions submit URBs. It seems some silicon
1671 * corrupts things if you reuse completed descriptors very quickly...
1673 static unsigned
1674 itd_complete (
1675 struct ehci_hcd *ehci,
1676 struct ehci_itd *itd
1678 struct urb *urb = itd->urb;
1679 struct usb_iso_packet_descriptor *desc;
1680 u32 t;
1681 unsigned uframe;
1682 int urb_index = -1;
1683 struct ehci_iso_stream *stream = itd->stream;
1684 struct usb_device *dev;
1685 unsigned retval = false;
1687 /* for each uframe with a packet */
1688 for (uframe = 0; uframe < 8; uframe++) {
1689 if (likely (itd->index[uframe] == -1))
1690 continue;
1691 urb_index = itd->index[uframe];
1692 desc = &urb->iso_frame_desc [urb_index];
1694 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1695 itd->hw_transaction [uframe] = 0;
1697 /* report transfer status */
1698 if (unlikely (t & ISO_ERRS)) {
1699 urb->error_count++;
1700 if (t & EHCI_ISOC_BUF_ERR)
1701 desc->status = usb_pipein (urb->pipe)
1702 ? -ENOSR /* hc couldn't read */
1703 : -ECOMM; /* hc couldn't write */
1704 else if (t & EHCI_ISOC_BABBLE)
1705 desc->status = -EOVERFLOW;
1706 else /* (t & EHCI_ISOC_XACTERR) */
1707 desc->status = -EPROTO;
1709 /* HC need not update length with this error */
1710 if (!(t & EHCI_ISOC_BABBLE)) {
1711 desc->actual_length = EHCI_ITD_LENGTH(t);
1712 urb->actual_length += desc->actual_length;
1714 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1715 desc->status = 0;
1716 desc->actual_length = EHCI_ITD_LENGTH(t);
1717 urb->actual_length += desc->actual_length;
1718 } else {
1719 /* URB was too late */
1720 desc->status = -EXDEV;
1724 /* handle completion now? */
1725 if (likely ((urb_index + 1) != urb->number_of_packets))
1726 goto done;
1728 /* ASSERT: it's really the last itd for this urb
1729 list_for_each_entry (itd, &stream->td_list, itd_list)
1730 BUG_ON (itd->urb == urb);
1733 /* give urb back to the driver; completion often (re)submits */
1734 dev = urb->dev;
1735 ehci_urb_done(ehci, urb, 0);
1736 retval = true;
1737 urb = NULL;
1738 (void) disable_periodic(ehci);
1739 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1741 if (unlikely(list_is_singular(&stream->td_list))) {
1742 ehci_to_hcd(ehci)->self.bandwidth_allocated
1743 -= stream->bandwidth;
1744 ehci_vdbg (ehci,
1745 "deschedule devp %s ep%d%s-iso\n",
1746 dev->devpath, stream->bEndpointAddress & 0x0f,
1747 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1749 iso_stream_put (ehci, stream);
1751 done:
1752 itd->urb = NULL;
1753 if (ehci->clock_frame != itd->frame || itd->index[7] != -1) {
1754 /* OK to recycle this ITD now. */
1755 itd->stream = NULL;
1756 list_move(&itd->itd_list, &stream->free_list);
1757 iso_stream_put(ehci, stream);
1758 } else {
1759 /* HW might remember this ITD, so we can't recycle it yet.
1760 * Move it to a safe place until a new frame starts.
1762 list_move(&itd->itd_list, &ehci->cached_itd_list);
1763 if (stream->refcount == 2) {
1764 /* If iso_stream_put() were called here, stream
1765 * would be freed. Instead, just prevent reuse.
1767 stream->ep->hcpriv = NULL;
1768 stream->ep = NULL;
1771 return retval;
1774 /*-------------------------------------------------------------------------*/
1776 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1777 gfp_t mem_flags)
1779 int status = -EINVAL;
1780 unsigned long flags;
1781 struct ehci_iso_stream *stream;
1783 /* Get iso_stream head */
1784 stream = iso_stream_find (ehci, urb);
1785 if (unlikely (stream == NULL)) {
1786 ehci_dbg (ehci, "can't get iso stream\n");
1787 return -ENOMEM;
1789 if (unlikely (urb->interval != stream->interval)) {
1790 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1791 stream->interval, urb->interval);
1792 goto done;
1795 #ifdef EHCI_URB_TRACE
1796 ehci_dbg (ehci,
1797 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1798 __FUNCTION__, urb->dev->devpath, urb,
1799 usb_pipeendpoint (urb->pipe),
1800 usb_pipein (urb->pipe) ? "in" : "out",
1801 urb->transfer_buffer_length,
1802 urb->number_of_packets, urb->interval,
1803 stream);
1804 #endif
1806 /* allocate ITDs w/o locking anything */
1807 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1808 if (unlikely (status < 0)) {
1809 ehci_dbg (ehci, "can't init itds\n");
1810 goto done;
1813 /* schedule ... need to lock */
1814 spin_lock_irqsave (&ehci->lock, flags);
1815 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
1816 &ehci_to_hcd(ehci)->flags))) {
1817 status = -ESHUTDOWN;
1818 goto done_not_linked;
1820 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1821 if (unlikely(status))
1822 goto done_not_linked;
1823 status = iso_stream_schedule(ehci, urb, stream);
1824 if (likely (status == 0))
1825 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1826 else
1827 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1828 done_not_linked:
1829 spin_unlock_irqrestore (&ehci->lock, flags);
1831 done:
1832 if (unlikely (status < 0))
1833 iso_stream_put (ehci, stream);
1834 return status;
1837 /*-------------------------------------------------------------------------*/
1840 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1841 * TTs in USB 2.0 hubs. These need microframe scheduling.
1844 static inline void
1845 sitd_sched_init(
1846 struct ehci_hcd *ehci,
1847 struct ehci_iso_sched *iso_sched,
1848 struct ehci_iso_stream *stream,
1849 struct urb *urb
1852 unsigned i;
1853 dma_addr_t dma = urb->transfer_dma;
1855 /* how many frames are needed for these transfers */
1856 iso_sched->span = urb->number_of_packets * stream->interval;
1858 /* figure out per-frame sitd fields that we'll need later
1859 * when we fit new sitds into the schedule.
1861 for (i = 0; i < urb->number_of_packets; i++) {
1862 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1863 unsigned length;
1864 dma_addr_t buf;
1865 u32 trans;
1867 length = urb->iso_frame_desc [i].length & 0x03ff;
1868 buf = dma + urb->iso_frame_desc [i].offset;
1870 trans = SITD_STS_ACTIVE;
1871 if (((i + 1) == urb->number_of_packets)
1872 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1873 trans |= SITD_IOC;
1874 trans |= length << 16;
1875 packet->transaction = cpu_to_hc32(ehci, trans);
1877 /* might need to cross a buffer page within a td */
1878 packet->bufp = buf;
1879 packet->buf1 = (buf + length) & ~0x0fff;
1880 if (packet->buf1 != (buf & ~(u64)0x0fff))
1881 packet->cross = 1;
1883 /* OUT uses multiple start-splits */
1884 if (stream->bEndpointAddress & USB_DIR_IN)
1885 continue;
1886 length = (length + 187) / 188;
1887 if (length > 1) /* BEGIN vs ALL */
1888 length |= 1 << 3;
1889 packet->buf1 |= length;
1893 static int
1894 sitd_urb_transaction (
1895 struct ehci_iso_stream *stream,
1896 struct ehci_hcd *ehci,
1897 struct urb *urb,
1898 gfp_t mem_flags
1901 struct ehci_sitd *sitd;
1902 dma_addr_t sitd_dma;
1903 int i;
1904 struct ehci_iso_sched *iso_sched;
1905 unsigned long flags;
1907 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1908 if (iso_sched == NULL)
1909 return -ENOMEM;
1911 sitd_sched_init(ehci, iso_sched, stream, urb);
1913 /* allocate/init sITDs */
1914 spin_lock_irqsave (&ehci->lock, flags);
1915 for (i = 0; i < urb->number_of_packets; i++) {
1917 /* NOTE: for now, we don't try to handle wraparound cases
1918 * for IN (using sitd->hw_backpointer, like a FSTN), which
1919 * means we never need two sitds for full speed packets.
1922 /* free_list.next might be cache-hot ... but maybe
1923 * the HC caches it too. avoid that issue for now.
1926 /* prefer previously-allocated sitds */
1927 if (!list_empty(&stream->free_list)) {
1928 sitd = list_entry (stream->free_list.prev,
1929 struct ehci_sitd, sitd_list);
1930 list_del (&sitd->sitd_list);
1931 sitd_dma = sitd->sitd_dma;
1932 } else {
1933 spin_unlock_irqrestore (&ehci->lock, flags);
1934 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1935 &sitd_dma);
1936 spin_lock_irqsave (&ehci->lock, flags);
1937 if (!sitd) {
1938 iso_sched_free(stream, iso_sched);
1939 spin_unlock_irqrestore(&ehci->lock, flags);
1940 return -ENOMEM;
1944 memset (sitd, 0, sizeof *sitd);
1945 sitd->sitd_dma = sitd_dma;
1946 list_add (&sitd->sitd_list, &iso_sched->td_list);
1949 /* temporarily store schedule info in hcpriv */
1950 urb->hcpriv = iso_sched;
1951 urb->error_count = 0;
1953 spin_unlock_irqrestore (&ehci->lock, flags);
1954 return 0;
1957 /*-------------------------------------------------------------------------*/
1959 static inline void
1960 sitd_patch(
1961 struct ehci_hcd *ehci,
1962 struct ehci_iso_stream *stream,
1963 struct ehci_sitd *sitd,
1964 struct ehci_iso_sched *iso_sched,
1965 unsigned index
1968 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1969 u64 bufp = uf->bufp;
1971 sitd->hw_next = EHCI_LIST_END(ehci);
1972 sitd->hw_fullspeed_ep = stream->address;
1973 sitd->hw_uframe = stream->splits;
1974 sitd->hw_results = uf->transaction;
1975 sitd->hw_backpointer = EHCI_LIST_END(ehci);
1977 bufp = uf->bufp;
1978 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1979 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1981 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1982 if (uf->cross)
1983 bufp += 4096;
1984 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1985 sitd->index = index;
1988 static inline void
1989 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1991 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1992 sitd->sitd_next = ehci->pshadow [frame];
1993 sitd->hw_next = ehci->periodic [frame];
1994 ehci->pshadow [frame].sitd = sitd;
1995 sitd->frame = frame;
1996 wmb ();
1997 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
2000 /* fit urb's sitds into the selected schedule slot; activate as needed */
2001 static int
2002 sitd_link_urb (
2003 struct ehci_hcd *ehci,
2004 struct urb *urb,
2005 unsigned mod,
2006 struct ehci_iso_stream *stream
2009 int packet;
2010 unsigned next_uframe;
2011 struct ehci_iso_sched *sched = urb->hcpriv;
2012 struct ehci_sitd *sitd;
2014 next_uframe = stream->next_uframe;
2016 if (list_empty(&stream->td_list)) {
2017 /* usbfs ignores TT bandwidth */
2018 ehci_to_hcd(ehci)->self.bandwidth_allocated
2019 += stream->bandwidth;
2020 ehci_vdbg (ehci,
2021 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2022 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2023 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
2024 (next_uframe >> 3) & (ehci->periodic_size - 1),
2025 stream->interval, hc32_to_cpu(ehci, stream->splits));
2027 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2029 /* fill sITDs frame by frame */
2030 for (packet = 0, sitd = NULL;
2031 packet < urb->number_of_packets;
2032 packet++) {
2034 /* ASSERT: we have all necessary sitds */
2035 BUG_ON (list_empty (&sched->td_list));
2037 /* ASSERT: no itds for this endpoint in this frame */
2039 sitd = list_entry (sched->td_list.next,
2040 struct ehci_sitd, sitd_list);
2041 list_move_tail (&sitd->sitd_list, &stream->td_list);
2042 sitd->stream = iso_stream_get (stream);
2043 sitd->urb = urb;
2045 sitd_patch(ehci, stream, sitd, sched, packet);
2046 sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1),
2047 sitd);
2049 next_uframe += stream->interval << 3;
2051 stream->next_uframe = next_uframe & (mod - 1);
2053 /* don't need that schedule data any more */
2054 iso_sched_free (stream, sched);
2055 urb->hcpriv = NULL;
2057 timer_action (ehci, TIMER_IO_WATCHDOG);
2058 return enable_periodic(ehci);
2061 /*-------------------------------------------------------------------------*/
2063 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
2064 | SITD_STS_XACT | SITD_STS_MMF)
2066 /* Process and recycle a completed SITD. Return true iff its urb completed,
2067 * and hence its completion callback probably added things to the hardware
2068 * schedule.
2070 * Note that we carefully avoid recycling this descriptor until after any
2071 * completion callback runs, so that it won't be reused quickly. That is,
2072 * assuming (a) no more than two urbs per frame on this endpoint, and also
2073 * (b) only this endpoint's completions submit URBs. It seems some silicon
2074 * corrupts things if you reuse completed descriptors very quickly...
2076 static unsigned
2077 sitd_complete (
2078 struct ehci_hcd *ehci,
2079 struct ehci_sitd *sitd
2081 struct urb *urb = sitd->urb;
2082 struct usb_iso_packet_descriptor *desc;
2083 u32 t;
2084 int urb_index = -1;
2085 struct ehci_iso_stream *stream = sitd->stream;
2086 struct usb_device *dev;
2087 unsigned retval = false;
2089 urb_index = sitd->index;
2090 desc = &urb->iso_frame_desc [urb_index];
2091 t = hc32_to_cpup(ehci, &sitd->hw_results);
2093 /* report transfer status */
2094 if (t & SITD_ERRS) {
2095 urb->error_count++;
2096 if (t & SITD_STS_DBE)
2097 desc->status = usb_pipein (urb->pipe)
2098 ? -ENOSR /* hc couldn't read */
2099 : -ECOMM; /* hc couldn't write */
2100 else if (t & SITD_STS_BABBLE)
2101 desc->status = -EOVERFLOW;
2102 else /* XACT, MMF, etc */
2103 desc->status = -EPROTO;
2104 } else {
2105 desc->status = 0;
2106 desc->actual_length = desc->length - SITD_LENGTH(t);
2107 urb->actual_length += desc->actual_length;
2110 /* handle completion now? */
2111 if ((urb_index + 1) != urb->number_of_packets)
2112 goto done;
2114 /* ASSERT: it's really the last sitd for this urb
2115 list_for_each_entry (sitd, &stream->td_list, sitd_list)
2116 BUG_ON (sitd->urb == urb);
2119 /* give urb back to the driver; completion often (re)submits */
2120 dev = urb->dev;
2121 ehci_urb_done(ehci, urb, 0);
2122 retval = true;
2123 urb = NULL;
2124 (void) disable_periodic(ehci);
2125 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2127 if (list_is_singular(&stream->td_list)) {
2128 ehci_to_hcd(ehci)->self.bandwidth_allocated
2129 -= stream->bandwidth;
2130 ehci_vdbg (ehci,
2131 "deschedule devp %s ep%d%s-iso\n",
2132 dev->devpath, stream->bEndpointAddress & 0x0f,
2133 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2135 iso_stream_put (ehci, stream);
2137 done:
2138 sitd->urb = NULL;
2139 if (ehci->clock_frame != sitd->frame) {
2140 /* OK to recycle this SITD now. */
2141 sitd->stream = NULL;
2142 list_move(&sitd->sitd_list, &stream->free_list);
2143 iso_stream_put(ehci, stream);
2144 } else {
2145 /* HW might remember this SITD, so we can't recycle it yet.
2146 * Move it to a safe place until a new frame starts.
2148 list_move(&sitd->sitd_list, &ehci->cached_sitd_list);
2149 if (stream->refcount == 2) {
2150 /* If iso_stream_put() were called here, stream
2151 * would be freed. Instead, just prevent reuse.
2153 stream->ep->hcpriv = NULL;
2154 stream->ep = NULL;
2157 return retval;
2161 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2162 gfp_t mem_flags)
2164 int status = -EINVAL;
2165 unsigned long flags;
2166 struct ehci_iso_stream *stream;
2168 /* Get iso_stream head */
2169 stream = iso_stream_find (ehci, urb);
2170 if (stream == NULL) {
2171 ehci_dbg (ehci, "can't get iso stream\n");
2172 return -ENOMEM;
2174 if (urb->interval != stream->interval) {
2175 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2176 stream->interval, urb->interval);
2177 goto done;
2180 #ifdef EHCI_URB_TRACE
2181 ehci_dbg (ehci,
2182 "submit %p dev%s ep%d%s-iso len %d\n",
2183 urb, urb->dev->devpath,
2184 usb_pipeendpoint (urb->pipe),
2185 usb_pipein (urb->pipe) ? "in" : "out",
2186 urb->transfer_buffer_length);
2187 #endif
2189 /* allocate SITDs */
2190 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2191 if (status < 0) {
2192 ehci_dbg (ehci, "can't init sitds\n");
2193 goto done;
2196 /* schedule ... need to lock */
2197 spin_lock_irqsave (&ehci->lock, flags);
2198 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
2199 &ehci_to_hcd(ehci)->flags))) {
2200 status = -ESHUTDOWN;
2201 goto done_not_linked;
2203 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2204 if (unlikely(status))
2205 goto done_not_linked;
2206 status = iso_stream_schedule(ehci, urb, stream);
2207 if (status == 0)
2208 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2209 else
2210 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2211 done_not_linked:
2212 spin_unlock_irqrestore (&ehci->lock, flags);
2214 done:
2215 if (status < 0)
2216 iso_stream_put (ehci, stream);
2217 return status;
2220 /*-------------------------------------------------------------------------*/
2222 static void free_cached_lists(struct ehci_hcd *ehci)
2224 struct ehci_itd *itd, *n;
2225 struct ehci_sitd *sitd, *sn;
2227 list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) {
2228 struct ehci_iso_stream *stream = itd->stream;
2229 itd->stream = NULL;
2230 list_move(&itd->itd_list, &stream->free_list);
2231 iso_stream_put(ehci, stream);
2234 list_for_each_entry_safe(sitd, sn, &ehci->cached_sitd_list, sitd_list) {
2235 struct ehci_iso_stream *stream = sitd->stream;
2236 sitd->stream = NULL;
2237 list_move(&sitd->sitd_list, &stream->free_list);
2238 iso_stream_put(ehci, stream);
2242 /*-------------------------------------------------------------------------*/
2244 static void
2245 scan_periodic (struct ehci_hcd *ehci)
2247 unsigned now_uframe, frame, clock, clock_frame, mod;
2248 unsigned modified;
2250 mod = ehci->periodic_size << 3;
2253 * When running, scan from last scan point up to "now"
2254 * else clean up by scanning everything that's left.
2255 * Touches as few pages as possible: cache-friendly.
2257 now_uframe = ehci->next_uframe;
2258 if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2259 clock = ehci_readl(ehci, &ehci->regs->frame_index);
2260 clock_frame = (clock >> 3) & (ehci->periodic_size - 1);
2261 } else {
2262 clock = now_uframe + mod - 1;
2263 clock_frame = -1;
2265 if (ehci->clock_frame != clock_frame) {
2266 free_cached_lists(ehci);
2267 ehci->clock_frame = clock_frame;
2269 clock &= mod - 1;
2270 clock_frame = clock >> 3;
2271 ++ehci->periodic_stamp;
2273 for (;;) {
2274 union ehci_shadow q, *q_p;
2275 __hc32 type, *hw_p;
2276 unsigned incomplete = false;
2278 frame = now_uframe >> 3;
2280 restart:
2281 /* scan each element in frame's queue for completions */
2282 q_p = &ehci->pshadow [frame];
2283 hw_p = &ehci->periodic [frame];
2284 q.ptr = q_p->ptr;
2285 type = Q_NEXT_TYPE(ehci, *hw_p);
2286 modified = 0;
2288 while (q.ptr != NULL) {
2289 unsigned uf;
2290 union ehci_shadow temp;
2291 int live;
2293 live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2294 switch (hc32_to_cpu(ehci, type)) {
2295 case Q_TYPE_QH:
2296 /* handle any completions */
2297 temp.qh = qh_get (q.qh);
2298 type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next);
2299 q = q.qh->qh_next;
2300 if (temp.qh->stamp != ehci->periodic_stamp) {
2301 modified = qh_completions(ehci, temp.qh);
2302 if (!modified)
2303 temp.qh->stamp = ehci->periodic_stamp;
2304 if (unlikely(list_empty(&temp.qh->qtd_list) ||
2305 temp.qh->needs_rescan))
2306 intr_deschedule(ehci, temp.qh);
2308 qh_put (temp.qh);
2309 break;
2310 case Q_TYPE_FSTN:
2311 /* for "save place" FSTNs, look at QH entries
2312 * in the previous frame for completions.
2314 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2315 dbg ("ignoring completions from FSTNs");
2317 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2318 q = q.fstn->fstn_next;
2319 break;
2320 case Q_TYPE_ITD:
2321 /* If this ITD is still active, leave it for
2322 * later processing ... check the next entry.
2323 * No need to check for activity unless the
2324 * frame is current.
2326 if (frame == clock_frame && live) {
2327 rmb();
2328 for (uf = 0; uf < 8; uf++) {
2329 if (q.itd->hw_transaction[uf] &
2330 ITD_ACTIVE(ehci))
2331 break;
2333 if (uf < 8) {
2334 incomplete = true;
2335 q_p = &q.itd->itd_next;
2336 hw_p = &q.itd->hw_next;
2337 type = Q_NEXT_TYPE(ehci,
2338 q.itd->hw_next);
2339 q = *q_p;
2340 break;
2344 /* Take finished ITDs out of the schedule
2345 * and process them: recycle, maybe report
2346 * URB completion. HC won't cache the
2347 * pointer for much longer, if at all.
2349 *q_p = q.itd->itd_next;
2350 if (!ehci->use_dummy_qh ||
2351 q.itd->hw_next != EHCI_LIST_END(ehci))
2352 *hw_p = q.itd->hw_next;
2353 else
2354 *hw_p = ehci->dummy->qh_dma;
2355 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2356 wmb();
2357 modified = itd_complete (ehci, q.itd);
2358 q = *q_p;
2359 break;
2360 case Q_TYPE_SITD:
2361 /* If this SITD is still active, leave it for
2362 * later processing ... check the next entry.
2363 * No need to check for activity unless the
2364 * frame is current.
2366 if (((frame == clock_frame) ||
2367 (((frame + 1) & (ehci->periodic_size - 1))
2368 == clock_frame))
2369 && live
2370 && (q.sitd->hw_results &
2371 SITD_ACTIVE(ehci))) {
2373 incomplete = true;
2374 q_p = &q.sitd->sitd_next;
2375 hw_p = &q.sitd->hw_next;
2376 type = Q_NEXT_TYPE(ehci,
2377 q.sitd->hw_next);
2378 q = *q_p;
2379 break;
2382 /* Take finished SITDs out of the schedule
2383 * and process them: recycle, maybe report
2384 * URB completion.
2386 *q_p = q.sitd->sitd_next;
2387 if (!ehci->use_dummy_qh ||
2388 q.sitd->hw_next != EHCI_LIST_END(ehci))
2389 *hw_p = q.sitd->hw_next;
2390 else
2391 *hw_p = ehci->dummy->qh_dma;
2392 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2393 wmb();
2394 modified = sitd_complete (ehci, q.sitd);
2395 q = *q_p;
2396 break;
2397 default:
2398 dbg ("corrupt type %d frame %d shadow %p",
2399 type, frame, q.ptr);
2400 // BUG ();
2401 q.ptr = NULL;
2404 /* assume completion callbacks modify the queue */
2405 if (unlikely (modified)) {
2406 if (likely(ehci->periodic_sched > 0))
2407 goto restart;
2408 /* short-circuit this scan */
2409 now_uframe = clock;
2410 break;
2414 /* If we can tell we caught up to the hardware, stop now.
2415 * We can't advance our scan without collecting the ISO
2416 * transfers that are still pending in this frame.
2418 if (incomplete && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2419 ehci->next_uframe = now_uframe;
2420 break;
2423 // FIXME: this assumes we won't get lapped when
2424 // latencies climb; that should be rare, but...
2425 // detect it, and just go all the way around.
2426 // FLR might help detect this case, so long as latencies
2427 // don't exceed periodic_size msec (default 1.024 sec).
2429 // FIXME: likewise assumes HC doesn't halt mid-scan
2431 if (now_uframe == clock) {
2432 unsigned now;
2434 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
2435 || ehci->periodic_sched == 0)
2436 break;
2437 ehci->next_uframe = now_uframe;
2438 now = ehci_readl(ehci, &ehci->regs->frame_index) &
2439 (mod - 1);
2440 if (now_uframe == now)
2441 break;
2443 /* rescan the rest of this frame, then ... */
2444 clock = now;
2445 clock_frame = clock >> 3;
2446 if (ehci->clock_frame != clock_frame) {
2447 free_cached_lists(ehci);
2448 ehci->clock_frame = clock_frame;
2449 ++ehci->periodic_stamp;
2451 } else {
2452 now_uframe++;
2453 now_uframe &= mod - 1;