release/src-rt-6.x/linux/linux-2.6/drivers/scsi/lpfc/lpfc_hw.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2004-2007 Emulex.  All rights reserved.           *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 #define FDMI_DID        0xfffffaU
  22 #define NameServer_DID  0xfffffcU
  23 #define SCR_DID         0xfffffdU
  24 #define Fabric_DID      0xfffffeU
  25 #define Bcast_DID       0xffffffU
  26 #define Mask_DID        0xffffffU
  27 #define CT_DID_MASK     0xffff00U
  28 #define Fabric_DID_MASK 0xfff000U
  29 #define WELL_KNOWN_DID_MASK 0xfffff0U
  30
  31 #define PT2PT_LocalID   1
  32 #define PT2PT_RemoteID  2
  33
  34 #define FF_DEF_EDTOV          2000      /* Default E_D_TOV (2000ms) */
  35 #define FF_DEF_ALTOV            15      /* Default AL_TIME (15ms) */
  36 #define FF_DEF_RATOV             2      /* Default RA_TOV (2s) */
  37 #define FF_DEF_ARBTOV         1900      /* Default ARB_TOV (1900ms) */
  38
  39 #define LPFC_BUF_RING0        64        /* Number of buffers to post to RING
  40                                            0 */
  41
  42 #define FCELSSIZE             1024      /* maximum ELS transfer size */
  43
  44 #define LPFC_FCP_RING            0      /* ring 0 for FCP initiator commands */
  45 #define LPFC_EXTRA_RING          1      /* ring 1 for other protocols */
  46 #define LPFC_ELS_RING            2      /* ring 2 for ELS commands */
  47 #define LPFC_FCP_NEXT_RING       3
  48
  49 #define SLI2_IOCB_CMD_R0_ENTRIES    172 /* SLI-2 FCP command ring entries */
  50 #define SLI2_IOCB_RSP_R0_ENTRIES    134 /* SLI-2 FCP response ring entries */
  51 #define SLI2_IOCB_CMD_R1_ENTRIES      4 /* SLI-2 extra command ring entries */
  52 #define SLI2_IOCB_RSP_R1_ENTRIES      4 /* SLI-2 extra response ring entries */
  53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
  54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
  55 #define SLI2_IOCB_CMD_R2_ENTRIES     20 /* SLI-2 ELS command ring entries */
  56 #define SLI2_IOCB_RSP_R2_ENTRIES     20 /* SLI-2 ELS response ring entries */
  57 #define SLI2_IOCB_CMD_R3_ENTRIES      0
  58 #define SLI2_IOCB_RSP_R3_ENTRIES      0
  59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
  60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
  61
  62 /* Common Transport structures and definitions */
  63
  64 union CtRevisionId {
  65         /* Structure is in Big Endian format */
  66         struct {
  67                 uint32_t Revision:8;
  68                 uint32_t InId:24;
  69         } bits;
  70         uint32_t word;
  71 };
  72
  73 union CtCommandResponse {
  74         /* Structure is in Big Endian format */
  75         struct {
  76                 uint32_t CmdRsp:16;
  77                 uint32_t Size:16;
  78         } bits;
  79         uint32_t word;
  80 };
  81
  82 struct lpfc_sli_ct_request {
  83         /* Structure is in Big Endian format */
  84         union CtRevisionId RevisionId;
  85         uint8_t FsType;
  86         uint8_t FsSubType;
  87         uint8_t Options;
  88         uint8_t Rsrvd1;
  89         union CtCommandResponse CommandResponse;
  90         uint8_t Rsrvd2;
  91         uint8_t ReasonCode;
  92         uint8_t Explanation;
  93         uint8_t VendorUnique;
  94
  95         union {
  96                 uint32_t PortID;
  97                 struct gid {
  98                         uint8_t PortType;       /* for GID_PT requests */
  99                         uint8_t DomainScope;
 100                         uint8_t AreaScope;
 101                         uint8_t Fc4Type;        /* for GID_FT requests */
 102                 } gid;
 103                 struct rft {
 104                         uint32_t PortId;        /* For RFT_ID requests */
 105
 106 #ifdef __BIG_ENDIAN_BITFIELD
 107                         uint32_t rsvd0:16;
 108                         uint32_t rsvd1:7;
 109                         uint32_t fcpReg:1;      /* Type 8 */
 110                         uint32_t rsvd2:2;
 111                         uint32_t ipReg:1;       /* Type 5 */
 112                         uint32_t rsvd3:5;
 113 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 114                         uint32_t rsvd0:16;
 115                         uint32_t fcpReg:1;      /* Type 8 */
 116                         uint32_t rsvd1:7;
 117                         uint32_t rsvd3:5;
 118                         uint32_t ipReg:1;       /* Type 5 */
 119                         uint32_t rsvd2:2;
 120 #endif
 121
 122                         uint32_t rsvd[7];
 123                 } rft;
 124                 struct rff {
 125                         uint32_t PortId;
 126                         uint8_t reserved[2];
 127 #ifdef __BIG_ENDIAN_BITFIELD
 128                         uint8_t feature_res:6;
 129                         uint8_t feature_init:1;
 130                         uint8_t feature_tgt:1;
 131 #else  /*  __LITTLE_ENDIAN_BITFIELD */
 132                         uint8_t feature_tgt:1;
 133                         uint8_t feature_init:1;
 134                         uint8_t feature_res:6;
 135 #endif
 136                         uint8_t type_code;     /* type=8 for FCP */
 137                 } rff;
 138                 struct rnn {
 139                         uint32_t PortId;        /* For RNN_ID requests */
 140                         uint8_t wwnn[8];
 141                 } rnn;
 142                 struct rsnn {   /* For RSNN_ID requests */
 143                         uint8_t wwnn[8];
 144                         uint8_t len;
 145                         uint8_t symbname[255];
 146                 } rsnn;
 147         } un;
 148 };
 149
 150 #define  SLI_CT_REVISION        1
 151 #define  GID_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 260)
 152 #define  RFT_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 228)
 153 #define  RFF_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 235)
 154 #define  RNN_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 252)
 155 #define  RSNN_REQUEST_SZ        (sizeof(struct lpfc_sli_ct_request))
 156
 157 /*
 158  * FsType Definitions
 159  */
 160
 161 #define  SLI_CT_MANAGEMENT_SERVICE        0xFA
 162 #define  SLI_CT_TIME_SERVICE              0xFB
 163 #define  SLI_CT_DIRECTORY_SERVICE         0xFC
 164 #define  SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
 165
 166 /*
 167  * Directory Service Subtypes
 168  */
 169
 170 #define  SLI_CT_DIRECTORY_NAME_SERVER     0x02
 171
 172 /*
 173  * Response Codes
 174  */
 175
 176 #define  SLI_CT_RESPONSE_FS_RJT           0x8001
 177 #define  SLI_CT_RESPONSE_FS_ACC           0x8002
 178
 179 /*
 180  * Reason Codes
 181  */
 182
 183 #define  SLI_CT_NO_ADDITIONAL_EXPL        0x0
 184 #define  SLI_CT_INVALID_COMMAND           0x01
 185 #define  SLI_CT_INVALID_VERSION           0x02
 186 #define  SLI_CT_LOGICAL_ERROR             0x03
 187 #define  SLI_CT_INVALID_IU_SIZE           0x04
 188 #define  SLI_CT_LOGICAL_BUSY              0x05
 189 #define  SLI_CT_PROTOCOL_ERROR            0x07
 190 #define  SLI_CT_UNABLE_TO_PERFORM_REQ     0x09
 191 #define  SLI_CT_REQ_NOT_SUPPORTED         0x0b
 192 #define  SLI_CT_HBA_INFO_NOT_REGISTERED   0x10
 193 #define  SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE  0x11
 194 #define  SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN      0x12
 195 #define  SLI_CT_HBA_ATTR_NOT_PRESENT      0x13
 196 #define  SLI_CT_PORT_INFO_NOT_REGISTERED  0x20
 197 #define  SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
 198 #define  SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN     0x22
 199 #define  SLI_CT_VENDOR_UNIQUE             0xff
 200
 201 /*
 202  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
 203  */
 204
 205 #define  SLI_CT_NO_PORT_ID                0x01
 206 #define  SLI_CT_NO_PORT_NAME              0x02
 207 #define  SLI_CT_NO_NODE_NAME              0x03
 208 #define  SLI_CT_NO_CLASS_OF_SERVICE       0x04
 209 #define  SLI_CT_NO_IP_ADDRESS             0x05
 210 #define  SLI_CT_NO_IPA                    0x06
 211 #define  SLI_CT_NO_FC4_TYPES              0x07
 212 #define  SLI_CT_NO_SYMBOLIC_PORT_NAME     0x08
 213 #define  SLI_CT_NO_SYMBOLIC_NODE_NAME     0x09
 214 #define  SLI_CT_NO_PORT_TYPE              0x0A
 215 #define  SLI_CT_ACCESS_DENIED             0x10
 216 #define  SLI_CT_INVALID_PORT_ID           0x11
 217 #define  SLI_CT_DATABASE_EMPTY            0x12
 218
 219 /*
 220  * Name Server Command Codes
 221  */
 222
 223 #define  SLI_CTNS_GA_NXT      0x0100
 224 #define  SLI_CTNS_GPN_ID      0x0112
 225 #define  SLI_CTNS_GNN_ID      0x0113
 226 #define  SLI_CTNS_GCS_ID      0x0114
 227 #define  SLI_CTNS_GFT_ID      0x0117
 228 #define  SLI_CTNS_GSPN_ID     0x0118
 229 #define  SLI_CTNS_GPT_ID      0x011A
 230 #define  SLI_CTNS_GID_PN      0x0121
 231 #define  SLI_CTNS_GID_NN      0x0131
 232 #define  SLI_CTNS_GIP_NN      0x0135
 233 #define  SLI_CTNS_GIPA_NN     0x0136
 234 #define  SLI_CTNS_GSNN_NN     0x0139
 235 #define  SLI_CTNS_GNN_IP      0x0153
 236 #define  SLI_CTNS_GIPA_IP     0x0156
 237 #define  SLI_CTNS_GID_FT      0x0171
 238 #define  SLI_CTNS_GID_PT      0x01A1
 239 #define  SLI_CTNS_RPN_ID      0x0212
 240 #define  SLI_CTNS_RNN_ID      0x0213
 241 #define  SLI_CTNS_RCS_ID      0x0214
 242 #define  SLI_CTNS_RFT_ID      0x0217
 243 #define  SLI_CTNS_RFF_ID      0x021F
 244 #define  SLI_CTNS_RSPN_ID     0x0218
 245 #define  SLI_CTNS_RPT_ID      0x021A
 246 #define  SLI_CTNS_RIP_NN      0x0235
 247 #define  SLI_CTNS_RIPA_NN     0x0236
 248 #define  SLI_CTNS_RSNN_NN     0x0239
 249 #define  SLI_CTNS_DA_ID       0x0300
 250
 251 /*
 252  * Port Types
 253  */
 254
 255 #define  SLI_CTPT_N_PORT      0x01
 256 #define  SLI_CTPT_NL_PORT     0x02
 257 #define  SLI_CTPT_FNL_PORT    0x03
 258 #define  SLI_CTPT_IP          0x04
 259 #define  SLI_CTPT_FCP         0x08
 260 #define  SLI_CTPT_NX_PORT     0x7F
 261 #define  SLI_CTPT_F_PORT      0x81
 262 #define  SLI_CTPT_FL_PORT     0x82
 263 #define  SLI_CTPT_E_PORT      0x84
 264
 265 #define SLI_CT_LAST_ENTRY     0x80000000
 266
 267 /* Fibre Channel Service Parameter definitions */
 268
 269 #define FC_PH_4_0   6           /* FC-PH version 4.0 */
 270 #define FC_PH_4_1   7           /* FC-PH version 4.1 */
 271 #define FC_PH_4_2   8           /* FC-PH version 4.2 */
 272 #define FC_PH_4_3   9           /* FC-PH version 4.3 */
 273
 274 #define FC_PH_LOW   8           /* Lowest supported FC-PH version */
 275 #define FC_PH_HIGH  9           /* Highest supported FC-PH version */
 276 #define FC_PH3   0x20           /* FC-PH-3 version */
 277
 278 #define FF_FRAME_SIZE     2048
 279
 280 struct lpfc_name {
 281         union {
 282                 struct {
 283 #ifdef __BIG_ENDIAN_BITFIELD
 284                         uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 285                         uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 286                                                    8:11 of IEEE ext */
 287 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 288                         uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 289                                                    8:11 of IEEE ext */
 290                         uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 291 #endif
 292
 293 #define NAME_IEEE           0x1 /* IEEE name - nameType */
 294 #define NAME_IEEE_EXT       0x2 /* IEEE extended name */
 295 #define NAME_FC_TYPE        0x3 /* FC native name type */
 296 #define NAME_IP_TYPE        0x4 /* IP address */
 297 #define NAME_CCITT_TYPE     0xC
 298 #define NAME_CCITT_GR_TYPE  0xE
 299                         uint8_t IEEEextLsb;     /* FC Word 0, bit 16:23, IEEE
 300                                                    extended Lsb */
 301                         uint8_t IEEE[6];        /* FC IEEE address */
 302                 } s;
 303                 uint8_t wwn[8];
 304         } u;
 305 };
 306
 307 struct csp {
 308         uint8_t fcphHigh;       /* FC Word 0, byte 0 */
 309         uint8_t fcphLow;
 310         uint8_t bbCreditMsb;
 311         uint8_t bbCreditlsb;    /* FC Word 0, byte 3 */
 312
 313 #ifdef __BIG_ENDIAN_BITFIELD
 314         uint16_t increasingOffset:1;    /* FC Word 1, bit 31 */
 315         uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 316         uint16_t word1Reserved2:1;      /* FC Word 1, bit 29 */
 317         uint16_t fPort:1;       /* FC Word 1, bit 28 */
 318         uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 319         uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 320         uint16_t multicast:1;   /* FC Word 1, bit 25 */
 321         uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 322
 323         uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 324         uint16_t simplex:1;     /* FC Word 1, bit 22 */
 325         uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 326         uint16_t dhd:1;         /* FC Word 1, bit 18 */
 327         uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 328         uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 329 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 330         uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 331         uint16_t multicast:1;   /* FC Word 1, bit 25 */
 332         uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 333         uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 334         uint16_t fPort:1;       /* FC Word 1, bit 28 */
 335         uint16_t word1Reserved2:1;      /* FC Word 1, bit 29 */
 336         uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 337         uint16_t increasingOffset:1;    /* FC Word 1, bit 31 */
 338
 339         uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 340         uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 341         uint16_t dhd:1;         /* FC Word 1, bit 18 */
 342         uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 343         uint16_t simplex:1;     /* FC Word 1, bit 22 */
 344         uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 345 #endif
 346
 347         uint8_t bbRcvSizeMsb;   /* Upper nibble is reserved */
 348         uint8_t bbRcvSizeLsb;   /* FC Word 1, byte 3 */
 349         union {
 350                 struct {
 351                         uint8_t word2Reserved1; /* FC Word 2 byte 0 */
 352
 353                         uint8_t totalConcurrSeq;        /* FC Word 2 byte 1 */
 354                         uint8_t roByCategoryMsb;        /* FC Word 2 byte 2 */
 355
 356                         uint8_t roByCategoryLsb;        /* FC Word 2 byte 3 */
 357                 } nPort;
 358                 uint32_t r_a_tov;       /* R_A_TOV must be in B.E. format */
 359         } w2;
 360
 361         uint32_t e_d_tov;       /* E_D_TOV must be in B.E. format */
 362 };
 363
 364 struct class_parms {
 365 #ifdef __BIG_ENDIAN_BITFIELD
 366         uint8_t classValid:1;   /* FC Word 0, bit 31 */
 367         uint8_t intermix:1;     /* FC Word 0, bit 30 */
 368         uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 369         uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 370         uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 371         uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 372 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 373         uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 374         uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 375         uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 376         uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 377         uint8_t intermix:1;     /* FC Word 0, bit 30 */
 378         uint8_t classValid:1;   /* FC Word 0, bit 31 */
 379
 380 #endif
 381
 382         uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
 383
 384 #ifdef __BIG_ENDIAN_BITFIELD
 385         uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 386         uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 387         uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 388         uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 389         uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 390 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 391         uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 392         uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 393         uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 394         uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 395         uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 396 #endif
 397
 398         uint8_t word0Reserved4; /* FC Word 0, bit  0: 7 */
 399
 400 #ifdef __BIG_ENDIAN_BITFIELD
 401         uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 402         uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 403         uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 404         uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 405         uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 406         uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 407 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 408         uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 409         uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 410         uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 411         uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 412         uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 413         uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 414 #endif
 415
 416         uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
 417         uint8_t rcvDataSizeMsb; /* FC Word 1, bit  8:15 */
 418         uint8_t rcvDataSizeLsb; /* FC Word 1, bit  0: 7 */
 419
 420         uint8_t concurrentSeqMsb;       /* FC Word 2, bit 24:31 */
 421         uint8_t concurrentSeqLsb;       /* FC Word 2, bit 16:23 */
 422         uint8_t EeCreditSeqMsb; /* FC Word 2, bit  8:15 */
 423         uint8_t EeCreditSeqLsb; /* FC Word 2, bit  0: 7 */
 424
 425         uint8_t openSeqPerXchgMsb;      /* FC Word 3, bit 24:31 */
 426         uint8_t openSeqPerXchgLsb;      /* FC Word 3, bit 16:23 */
 427         uint8_t word3Reserved1; /* Fc Word 3, bit  8:15 */
 428         uint8_t word3Reserved2; /* Fc Word 3, bit  0: 7 */
 429 };
 430
 431 struct serv_parm {      /* Structure is in Big Endian format */
 432         struct csp cmn;
 433         struct lpfc_name portName;
 434         struct lpfc_name nodeName;
 435         struct class_parms cls1;
 436         struct class_parms cls2;
 437         struct class_parms cls3;
 438         struct class_parms cls4;
 439         uint8_t vendorVersion[16];
 440 };
 441
 442 /*
 443  *  Extended Link Service LS_COMMAND codes (Payload Word 0)
 444  */
 445 #ifdef __BIG_ENDIAN_BITFIELD
 446 #define ELS_CMD_MASK      0xffff0000
 447 #define ELS_RSP_MASK      0xff000000
 448 #define ELS_CMD_LS_RJT    0x01000000
 449 #define ELS_CMD_ACC       0x02000000
 450 #define ELS_CMD_PLOGI     0x03000000
 451 #define ELS_CMD_FLOGI     0x04000000
 452 #define ELS_CMD_LOGO      0x05000000
 453 #define ELS_CMD_ABTX      0x06000000
 454 #define ELS_CMD_RCS       0x07000000
 455 #define ELS_CMD_RES       0x08000000
 456 #define ELS_CMD_RSS       0x09000000
 457 #define ELS_CMD_RSI       0x0A000000
 458 #define ELS_CMD_ESTS      0x0B000000
 459 #define ELS_CMD_ESTC      0x0C000000
 460 #define ELS_CMD_ADVC      0x0D000000
 461 #define ELS_CMD_RTV       0x0E000000
 462 #define ELS_CMD_RLS       0x0F000000
 463 #define ELS_CMD_ECHO      0x10000000
 464 #define ELS_CMD_TEST      0x11000000
 465 #define ELS_CMD_RRQ       0x12000000
 466 #define ELS_CMD_PRLI      0x20100014
 467 #define ELS_CMD_PRLO      0x21100014
 468 #define ELS_CMD_PRLO_ACC  0x02100014
 469 #define ELS_CMD_PDISC     0x50000000
 470 #define ELS_CMD_FDISC     0x51000000
 471 #define ELS_CMD_ADISC     0x52000000
 472 #define ELS_CMD_FARP      0x54000000
 473 #define ELS_CMD_FARPR     0x55000000
 474 #define ELS_CMD_RPS       0x56000000
 475 #define ELS_CMD_RPL       0x57000000
 476 #define ELS_CMD_FAN       0x60000000
 477 #define ELS_CMD_RSCN      0x61040000
 478 #define ELS_CMD_SCR       0x62000000
 479 #define ELS_CMD_RNID      0x78000000
 480 #define ELS_CMD_LIRR      0x7A000000
 481 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 482 #define ELS_CMD_MASK      0xffff
 483 #define ELS_RSP_MASK      0xff
 484 #define ELS_CMD_LS_RJT    0x01
 485 #define ELS_CMD_ACC       0x02
 486 #define ELS_CMD_PLOGI     0x03
 487 #define ELS_CMD_FLOGI     0x04
 488 #define ELS_CMD_LOGO      0x05
 489 #define ELS_CMD_ABTX      0x06
 490 #define ELS_CMD_RCS       0x07
 491 #define ELS_CMD_RES       0x08
 492 #define ELS_CMD_RSS       0x09
 493 #define ELS_CMD_RSI       0x0A
 494 #define ELS_CMD_ESTS      0x0B
 495 #define ELS_CMD_ESTC      0x0C
 496 #define ELS_CMD_ADVC      0x0D
 497 #define ELS_CMD_RTV       0x0E
 498 #define ELS_CMD_RLS       0x0F
 499 #define ELS_CMD_ECHO      0x10
 500 #define ELS_CMD_TEST      0x11
 501 #define ELS_CMD_RRQ       0x12
 502 #define ELS_CMD_PRLI      0x14001020
 503 #define ELS_CMD_PRLO      0x14001021
 504 #define ELS_CMD_PRLO_ACC  0x14001002
 505 #define ELS_CMD_PDISC     0x50
 506 #define ELS_CMD_FDISC     0x51
 507 #define ELS_CMD_ADISC     0x52
 508 #define ELS_CMD_FARP      0x54
 509 #define ELS_CMD_FARPR     0x55
 510 #define ELS_CMD_RPS       0x56
 511 #define ELS_CMD_RPL       0x57
 512 #define ELS_CMD_FAN       0x60
 513 #define ELS_CMD_RSCN      0x0461
 514 #define ELS_CMD_SCR       0x62
 515 #define ELS_CMD_RNID      0x78
 516 #define ELS_CMD_LIRR      0x7A
 517 #endif
 518
 519 /*
 520  *  LS_RJT Payload Definition
 521  */
 522
 523 struct ls_rjt { /* Structure is in Big Endian format */
 524         union {
 525                 uint32_t lsRjtError;
 526                 struct {
 527                         uint8_t lsRjtRsvd0;     /* FC Word 0, bit 24:31 */
 528
 529                         uint8_t lsRjtRsnCode;   /* FC Word 0, bit 16:23 */
 530                         /* LS_RJT reason codes */
 531 #define LSRJT_INVALID_CMD     0x01
 532 #define LSRJT_LOGICAL_ERR     0x03
 533 #define LSRJT_LOGICAL_BSY     0x05
 534 #define LSRJT_PROTOCOL_ERR    0x07
 535 #define LSRJT_UNABLE_TPC      0x09      /* Unable to perform command */
 536 #define LSRJT_CMD_UNSUPPORTED 0x0B
 537 #define LSRJT_VENDOR_UNIQUE   0xFF      /* See Byte 3 */
 538
 539                         uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
 540                         /* LS_RJT reason explanation */
 541 #define LSEXP_NOTHING_MORE      0x00
 542 #define LSEXP_SPARM_OPTIONS     0x01
 543 #define LSEXP_SPARM_ICTL        0x03
 544 #define LSEXP_SPARM_RCTL        0x05
 545 #define LSEXP_SPARM_RCV_SIZE    0x07
 546 #define LSEXP_SPARM_CONCUR_SEQ  0x09
 547 #define LSEXP_SPARM_CREDIT      0x0B
 548 #define LSEXP_INVALID_PNAME     0x0D
 549 #define LSEXP_INVALID_NNAME     0x0E
 550 #define LSEXP_INVALID_CSP       0x0F
 551 #define LSEXP_INVALID_ASSOC_HDR 0x11
 552 #define LSEXP_ASSOC_HDR_REQ     0x13
 553 #define LSEXP_INVALID_O_SID     0x15
 554 #define LSEXP_INVALID_OX_RX     0x17
 555 #define LSEXP_CMD_IN_PROGRESS   0x19
 556 #define LSEXP_INVALID_NPORT_ID  0x1F
 557 #define LSEXP_INVALID_SEQ_ID    0x21
 558 #define LSEXP_INVALID_XCHG      0x23
 559 #define LSEXP_INACTIVE_XCHG     0x25
 560 #define LSEXP_RQ_REQUIRED       0x27
 561 #define LSEXP_OUT_OF_RESOURCE   0x29
 562 #define LSEXP_CANT_GIVE_DATA    0x2A
 563 #define LSEXP_REQ_UNSUPPORTED   0x2C
 564                         uint8_t vendorUnique;   /* FC Word 0, bit  0: 7 */
 565                 } b;
 566         } un;
 567 };
 568
 569 /*
 570  *  N_Port Login (FLOGO/PLOGO Request) Payload Definition
 571  */
 572
 573 typedef struct _LOGO {          /* Structure is in Big Endian format */
 574         union {
 575                 uint32_t nPortId32;     /* Access nPortId as a word */
 576                 struct {
 577                         uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
 578                         uint8_t nPortIdByte0;   /* N_port  ID bit 16:23 */
 579                         uint8_t nPortIdByte1;   /* N_port  ID bit  8:15 */
 580                         uint8_t nPortIdByte2;   /* N_port  ID bit  0: 7 */
 581                 } b;
 582         } un;
 583         struct lpfc_name portName;      /* N_port name field */
 584 } LOGO;
 585
 586 /*
 587  *  FCP Login (PRLI Request / ACC) Payload Definition
 588  */
 589
 590 #define PRLX_PAGE_LEN   0x10
 591 #define TPRLO_PAGE_LEN  0x14
 592
 593 typedef struct _PRLI {          /* Structure is in Big Endian format */
 594         uint8_t prliType;       /* FC Parm Word 0, bit 24:31 */
 595
 596 #define PRLI_FCP_TYPE 0x08
 597         uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 598
 599 #ifdef __BIG_ENDIAN_BITFIELD
 600         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 601         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 602         uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 603
 604         /*    ACC = imagePairEstablished */
 605         uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 606         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 607 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 608         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 609         uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 610         uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 611         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 612         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 613         /*    ACC = imagePairEstablished */
 614 #endif
 615
 616 #define PRLI_REQ_EXECUTED     0x1       /* acceptRspCode */
 617 #define PRLI_NO_RESOURCES     0x2
 618 #define PRLI_INIT_INCOMPLETE  0x3
 619 #define PRLI_NO_SUCH_PA       0x4
 620 #define PRLI_PREDEF_CONFIG    0x5
 621 #define PRLI_PARTIAL_SUCCESS  0x6
 622 #define PRLI_INVALID_PAGE_CNT 0x7
 623         uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 624
 625         uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 626
 627         uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 628
 629         uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
 630         uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
 631
 632 #ifdef __BIG_ENDIAN_BITFIELD
 633         uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 634         uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 635         uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 636         uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 637         uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 638         uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 639         uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 640         uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 641         uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 642         uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 643         uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 644         uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 645         uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 646         uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 647         uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 648         uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 649 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 650         uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 651         uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 652         uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 653         uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 654         uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 655         uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 656         uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 657         uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 658         uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 659         uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 660         uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 661         uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 662         uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 663         uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 664         uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 665         uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 666 #endif
 667 } PRLI;
 668
 669 /*
 670  *  FCP Logout (PRLO Request / ACC) Payload Definition
 671  */
 672
 673 typedef struct _PRLO {          /* Structure is in Big Endian format */
 674         uint8_t prloType;       /* FC Parm Word 0, bit 24:31 */
 675
 676 #define PRLO_FCP_TYPE  0x08
 677         uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 678
 679 #ifdef __BIG_ENDIAN_BITFIELD
 680         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 681         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 682         uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 683         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 684 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 685         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 686         uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 687         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 688         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 689 #endif
 690
 691 #define PRLO_REQ_EXECUTED     0x1       /* acceptRspCode */
 692 #define PRLO_NO_SUCH_IMAGE    0x4
 693 #define PRLO_INVALID_PAGE_CNT 0x7
 694
 695         uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 696
 697         uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 698
 699         uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 700
 701         uint32_t word3Reserved1;        /* FC Parm Word 3, bit 0:31 */
 702 } PRLO;
 703
 704 typedef struct _ADISC {         /* Structure is in Big Endian format */
 705         uint32_t hardAL_PA;
 706         struct lpfc_name portName;
 707         struct lpfc_name nodeName;
 708         uint32_t DID;
 709 } ADISC;
 710
 711 typedef struct _FARP {          /* Structure is in Big Endian format */
 712         uint32_t Mflags:8;
 713         uint32_t Odid:24;
 714 #define FARP_NO_ACTION          0       /* FARP information enclosed, no
 715                                            action */
 716 #define FARP_MATCH_PORT         0x1     /* Match on Responder Port Name */
 717 #define FARP_MATCH_NODE         0x2     /* Match on Responder Node Name */
 718 #define FARP_MATCH_IP           0x4     /* Match on IP address, not supported */
 719 #define FARP_MATCH_IPV4         0x5     /* Match on IPV4 address, not
 720                                            supported */
 721 #define FARP_MATCH_IPV6         0x6     /* Match on IPV6 address, not
 722                                            supported */
 723         uint32_t Rflags:8;
 724         uint32_t Rdid:24;
 725 #define FARP_REQUEST_PLOGI      0x1     /* Request for PLOGI */
 726 #define FARP_REQUEST_FARPR      0x2     /* Request for FARP Response */
 727         struct lpfc_name OportName;
 728         struct lpfc_name OnodeName;
 729         struct lpfc_name RportName;
 730         struct lpfc_name RnodeName;
 731         uint8_t Oipaddr[16];
 732         uint8_t Ripaddr[16];
 733 } FARP;
 734
 735 typedef struct _FAN {           /* Structure is in Big Endian format */
 736         uint32_t Fdid;
 737         struct lpfc_name FportName;
 738         struct lpfc_name FnodeName;
 739 } FAN;
 740
 741 typedef struct _SCR {           /* Structure is in Big Endian format */
 742         uint8_t resvd1;
 743         uint8_t resvd2;
 744         uint8_t resvd3;
 745         uint8_t Function;
 746 #define  SCR_FUNC_FABRIC     0x01
 747 #define  SCR_FUNC_NPORT      0x02
 748 #define  SCR_FUNC_FULL       0x03
 749 #define  SCR_CLEAR           0xff
 750 } SCR;
 751
 752 typedef struct _RNID_TOP_DISC {
 753         struct lpfc_name portName;
 754         uint8_t resvd[8];
 755         uint32_t unitType;
 756 #define RNID_HBA            0x7
 757 #define RNID_HOST           0xa
 758 #define RNID_DRIVER         0xd
 759         uint32_t physPort;
 760         uint32_t attachedNodes;
 761         uint16_t ipVersion;
 762 #define RNID_IPV4           0x1
 763 #define RNID_IPV6           0x2
 764         uint16_t UDPport;
 765         uint8_t ipAddr[16];
 766         uint16_t resvd1;
 767         uint16_t flags;
 768 #define RNID_TD_SUPPORT     0x1
 769 #define RNID_LP_VALID       0x2
 770 } RNID_TOP_DISC;
 771
 772 typedef struct _RNID {          /* Structure is in Big Endian format */
 773         uint8_t Format;
 774 #define RNID_TOPOLOGY_DISC  0xdf
 775         uint8_t CommonLen;
 776         uint8_t resvd1;
 777         uint8_t SpecificLen;
 778         struct lpfc_name portName;
 779         struct lpfc_name nodeName;
 780         union {
 781                 RNID_TOP_DISC topologyDisc;     /* topology disc (0xdf) */
 782         } un;
 783 } RNID;
 784
 785 typedef struct  _RPS {          /* Structure is in Big Endian format */
 786         union {
 787                 uint32_t portNum;
 788                 struct lpfc_name portName;
 789         } un;
 790 } RPS;
 791
 792 typedef struct  _RPS_RSP {      /* Structure is in Big Endian format */
 793         uint16_t rsvd1;
 794         uint16_t portStatus;
 795         uint32_t linkFailureCnt;
 796         uint32_t lossSyncCnt;
 797         uint32_t lossSignalCnt;
 798         uint32_t primSeqErrCnt;
 799         uint32_t invalidXmitWord;
 800         uint32_t crcCnt;
 801 } RPS_RSP;
 802
 803 typedef struct  _RPL {          /* Structure is in Big Endian format */
 804         uint32_t maxsize;
 805         uint32_t index;
 806 } RPL;
 807
 808 typedef struct  _PORT_NUM_BLK {
 809         uint32_t portNum;
 810         uint32_t portID;
 811         struct lpfc_name portName;
 812 } PORT_NUM_BLK;
 813
 814 typedef struct  _RPL_RSP {      /* Structure is in Big Endian format */
 815         uint32_t listLen;
 816         uint32_t index;
 817         PORT_NUM_BLK port_num_blk;
 818 } RPL_RSP;
 819
 820 /* This is used for RSCN command */
 821 typedef struct _D_ID {          /* Structure is in Big Endian format */
 822         union {
 823                 uint32_t word;
 824                 struct {
 825 #ifdef __BIG_ENDIAN_BITFIELD
 826                         uint8_t resv;
 827                         uint8_t domain;
 828                         uint8_t area;
 829                         uint8_t id;
 830 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 831                         uint8_t id;
 832                         uint8_t area;
 833                         uint8_t domain;
 834                         uint8_t resv;
 835 #endif
 836                 } b;
 837         } un;
 838 } D_ID;
 839
 840 /*
 841  *  Structure to define all ELS Payload types
 842  */
 843
 844 typedef struct _ELS_PKT {       /* Structure is in Big Endian format */
 845         uint8_t elsCode;        /* FC Word 0, bit 24:31 */
 846         uint8_t elsByte1;
 847         uint8_t elsByte2;
 848         uint8_t elsByte3;
 849         union {
 850                 struct ls_rjt lsRjt;    /* Payload for LS_RJT ELS response */
 851                 struct serv_parm logi;  /* Payload for PLOGI/FLOGI/PDISC/ACC */
 852                 LOGO logo;      /* Payload for PLOGO/FLOGO/ACC */
 853                 PRLI prli;      /* Payload for PRLI/ACC */
 854                 PRLO prlo;      /* Payload for PRLO/ACC */
 855                 ADISC adisc;    /* Payload for ADISC/ACC */
 856                 FARP farp;      /* Payload for FARP/ACC */
 857                 FAN fan;        /* Payload for FAN */
 858                 SCR scr;        /* Payload for SCR/ACC */
 859                 RNID rnid;      /* Payload for RNID */
 860                 uint8_t pad[128 - 4];   /* Pad out to payload of 128 bytes */
 861         } un;
 862 } ELS_PKT;
 863
 864 /*
 865  * FDMI
 866  * HBA MAnagement Operations Command Codes
 867  */
 868 #define  SLI_MGMT_GRHL     0x100        /* Get registered HBA list */
 869 #define  SLI_MGMT_GHAT     0x101        /* Get HBA attributes */
 870 #define  SLI_MGMT_GRPL     0x102        /* Get registered Port list */
 871 #define  SLI_MGMT_GPAT     0x110        /* Get Port attributes */
 872 #define  SLI_MGMT_RHBA     0x200        /* Register HBA */
 873 #define  SLI_MGMT_RHAT     0x201        /* Register HBA atttributes */
 874 #define  SLI_MGMT_RPRT     0x210        /* Register Port */
 875 #define  SLI_MGMT_RPA      0x211        /* Register Port attributes */
 876 #define  SLI_MGMT_DHBA     0x300        /* De-register HBA */
 877 #define  SLI_MGMT_DPRT     0x310        /* De-register Port */
 878
 879 /*
 880  * Management Service Subtypes
 881  */
 882 #define  SLI_CT_FDMI_Subtypes     0x10
 883
 884 /*
 885  * HBA Management Service Reject Code
 886  */
 887 #define  REJECT_CODE             0x9    /* Unable to perform command request */
 888
 889 /*
 890  * HBA Management Service Reject Reason Code
 891  * Please refer to the Reason Codes above
 892  */
 893
 894 /*
 895  * HBA Attribute Types
 896  */
 897 #define  NODE_NAME               0x1
 898 #define  MANUFACTURER            0x2
 899 #define  SERIAL_NUMBER           0x3
 900 #define  MODEL                   0x4
 901 #define  MODEL_DESCRIPTION       0x5
 902 #define  HARDWARE_VERSION        0x6
 903 #define  DRIVER_VERSION          0x7
 904 #define  OPTION_ROM_VERSION      0x8
 905 #define  FIRMWARE_VERSION        0x9
 906 #define  OS_NAME_VERSION         0xa
 907 #define  MAX_CT_PAYLOAD_LEN      0xb
 908
 909 /*
 910  * Port Attrubute Types
 911  */
 912 #define  SUPPORTED_FC4_TYPES     0x1
 913 #define  SUPPORTED_SPEED         0x2
 914 #define  PORT_SPEED              0x3
 915 #define  MAX_FRAME_SIZE          0x4
 916 #define  OS_DEVICE_NAME          0x5
 917 #define  HOST_NAME               0x6
 918
 919 union AttributesDef {
 920         /* Structure is in Big Endian format */
 921         struct {
 922                 uint32_t AttrType:16;
 923                 uint32_t AttrLen:16;
 924         } bits;
 925         uint32_t word;
 926 };
 927
 928
 929 /*
 930  * HBA Attribute Entry (8 - 260 bytes)
 931  */
 932 typedef struct {
 933         union AttributesDef ad;
 934         union {
 935                 uint32_t VendorSpecific;
 936                 uint8_t Manufacturer[64];
 937                 uint8_t SerialNumber[64];
 938                 uint8_t Model[256];
 939                 uint8_t ModelDescription[256];
 940                 uint8_t HardwareVersion[256];
 941                 uint8_t DriverVersion[256];
 942                 uint8_t OptionROMVersion[256];
 943                 uint8_t FirmwareVersion[256];
 944                 struct lpfc_name NodeName;
 945                 uint8_t SupportFC4Types[32];
 946                 uint32_t SupportSpeed;
 947                 uint32_t PortSpeed;
 948                 uint32_t MaxFrameSize;
 949                 uint8_t OsDeviceName[256];
 950                 uint8_t OsNameVersion[256];
 951                 uint32_t MaxCTPayloadLen;
 952                 uint8_t HostName[256];
 953         } un;
 954 } ATTRIBUTE_ENTRY;
 955
 956 /*
 957  * HBA Attribute Block
 958  */
 959 typedef struct {
 960         uint32_t EntryCnt;      /* Number of HBA attribute entries */
 961         ATTRIBUTE_ENTRY Entry;  /* Variable-length array */
 962 } ATTRIBUTE_BLOCK;
 963
 964 /*
 965  * Port Entry
 966  */
 967 typedef struct {
 968         struct lpfc_name PortName;
 969 } PORT_ENTRY;
 970
 971 /*
 972  * HBA Identifier
 973  */
 974 typedef struct {
 975         struct lpfc_name PortName;
 976 } HBA_IDENTIFIER;
 977
 978 /*
 979  * Registered Port List Format
 980  */
 981 typedef struct {
 982         uint32_t EntryCnt;
 983         PORT_ENTRY pe;          /* Variable-length array */
 984 } REG_PORT_LIST;
 985
 986 /*
 987  * Register HBA(RHBA)
 988  */
 989 typedef struct {
 990         HBA_IDENTIFIER hi;
 991         REG_PORT_LIST rpl;      /* variable-length array */
 992 /* ATTRIBUTE_BLOCK   ab; */
 993 } REG_HBA;
 994
 995 /*
 996  * Register HBA Attributes (RHAT)
 997  */
 998 typedef struct {
 999         struct lpfc_name HBA_PortName;
1000         ATTRIBUTE_BLOCK ab;
1001 } REG_HBA_ATTRIBUTE;
1002
1003 /*
1004  * Register Port Attributes (RPA)
1005  */
1006 typedef struct {
1007         struct lpfc_name PortName;
1008         ATTRIBUTE_BLOCK ab;
1009 } REG_PORT_ATTRIBUTE;
1010
1011 /*
1012  * Get Registered HBA List (GRHL) Accept Payload Format
1013  */
1014 typedef struct {
1015         uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1016         struct lpfc_name HBA_PortName;  /* Variable-length array */
1017 } GRHL_ACC_PAYLOAD;
1018
1019 /*
1020  * Get Registered Port List (GRPL) Accept Payload Format
1021  */
1022 typedef struct {
1023         uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1024         PORT_ENTRY Reg_Port_Entry[1];   /* Variable-length array */
1025 } GRPL_ACC_PAYLOAD;
1026
1027 /*
1028  * Get Port Attributes (GPAT) Accept Payload Format
1029  */
1030
1031 typedef struct {
1032         ATTRIBUTE_BLOCK pab;
1033 } GPAT_ACC_PAYLOAD;
1034
1035
1036 /*
1037  *  Begin HBA configuration parameters.
1038  *  The PCI configuration register BAR assignments are:
1039  *  BAR0, offset 0x10 - SLIM base memory address
1040  *  BAR1, offset 0x14 - SLIM base memory high address
1041  *  BAR2, offset 0x18 - REGISTER base memory address
1042  *  BAR3, offset 0x1c - REGISTER base memory high address
1043  *  BAR4, offset 0x20 - BIU I/O registers
1044  *  BAR5, offset 0x24 - REGISTER base io high address
1045  */
1046
1047 /* Number of rings currently used and available. */
1048 #define MAX_CONFIGURED_RINGS     3
1049 #define MAX_RINGS                4
1050
1051 /* IOCB / Mailbox is owned by FireFly */
1052 #define OWN_CHIP        1
1053
1054 /* IOCB / Mailbox is owned by Host */
1055 #define OWN_HOST        0
1056
1057 /* Number of 4-byte words in an IOCB. */
1058 #define IOCB_WORD_SZ    8
1059
1060 /* defines for type field in fc header */
1061 #define FC_ELS_DATA     0x1
1062 #define FC_LLC_SNAP     0x5
1063 #define FC_FCP_DATA     0x8
1064 #define FC_COMMON_TRANSPORT_ULP 0x20
1065
1066 /* defines for rctl field in fc header */
1067 #define FC_DEV_DATA     0x0
1068 #define FC_UNSOL_CTL    0x2
1069 #define FC_SOL_CTL      0x3
1070 #define FC_UNSOL_DATA   0x4
1071 #define FC_FCP_CMND     0x6
1072 #define FC_ELS_REQ      0x22
1073 #define FC_ELS_RSP      0x23
1074
1075 /* network headers for Dfctl field */
1076 #define FC_NET_HDR      0x20
1077
1078 /* Start FireFly Register definitions */
1079 #define PCI_VENDOR_ID_EMULEX        0x10df
1080 #define PCI_DEVICE_ID_FIREFLY       0x1ae5
1081 #define PCI_DEVICE_ID_SAT_SMB       0xf011
1082 #define PCI_DEVICE_ID_SAT_MID       0xf015
1083 #define PCI_DEVICE_ID_RFLY          0xf095
1084 #define PCI_DEVICE_ID_PFLY          0xf098
1085 #define PCI_DEVICE_ID_LP101         0xf0a1
1086 #define PCI_DEVICE_ID_TFLY          0xf0a5
1087 #define PCI_DEVICE_ID_BSMB          0xf0d1
1088 #define PCI_DEVICE_ID_BMID          0xf0d5
1089 #define PCI_DEVICE_ID_ZSMB          0xf0e1
1090 #define PCI_DEVICE_ID_ZMID          0xf0e5
1091 #define PCI_DEVICE_ID_NEPTUNE       0xf0f5
1092 #define PCI_DEVICE_ID_NEPTUNE_SCSP  0xf0f6
1093 #define PCI_DEVICE_ID_NEPTUNE_DCSP  0xf0f7
1094 #define PCI_DEVICE_ID_SAT           0xf100
1095 #define PCI_DEVICE_ID_SAT_SCSP      0xf111
1096 #define PCI_DEVICE_ID_SAT_DCSP      0xf112
1097 #define PCI_DEVICE_ID_SUPERFLY      0xf700
1098 #define PCI_DEVICE_ID_DRAGONFLY     0xf800
1099 #define PCI_DEVICE_ID_CENTAUR       0xf900
1100 #define PCI_DEVICE_ID_PEGASUS       0xf980
1101 #define PCI_DEVICE_ID_THOR          0xfa00
1102 #define PCI_DEVICE_ID_VIPER         0xfb00
1103 #define PCI_DEVICE_ID_LP10000S      0xfc00
1104 #define PCI_DEVICE_ID_LP11000S      0xfc10
1105 #define PCI_DEVICE_ID_LPE11000S     0xfc20
1106 #define PCI_DEVICE_ID_SAT_S         0xfc40
1107 #define PCI_DEVICE_ID_HELIOS        0xfd00
1108 #define PCI_DEVICE_ID_HELIOS_SCSP   0xfd11
1109 #define PCI_DEVICE_ID_HELIOS_DCSP   0xfd12
1110 #define PCI_DEVICE_ID_ZEPHYR        0xfe00
1111 #define PCI_DEVICE_ID_ZEPHYR_SCSP   0xfe11
1112 #define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
1113
1114 #define JEDEC_ID_ADDRESS            0x0080001c
1115 #define FIREFLY_JEDEC_ID            0x1ACC
1116 #define SUPERFLY_JEDEC_ID           0x0020
1117 #define DRAGONFLY_JEDEC_ID          0x0021
1118 #define DRAGONFLY_V2_JEDEC_ID       0x0025
1119 #define CENTAUR_2G_JEDEC_ID         0x0026
1120 #define CENTAUR_1G_JEDEC_ID         0x0028
1121 #define PEGASUS_ORION_JEDEC_ID      0x0036
1122 #define PEGASUS_JEDEC_ID            0x0038
1123 #define THOR_JEDEC_ID               0x0012
1124 #define HELIOS_JEDEC_ID             0x0364
1125 #define ZEPHYR_JEDEC_ID             0x0577
1126 #define VIPER_JEDEC_ID              0x4838
1127 #define SATURN_JEDEC_ID             0x1004
1128
1129 #define JEDEC_ID_MASK               0x0FFFF000
1130 #define JEDEC_ID_SHIFT              12
1131 #define FC_JEDEC_ID(id)             ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1132
1133 typedef struct {                /* FireFly BIU registers */
1134         uint32_t hostAtt;       /* See definitions for Host Attention
1135                                    register */
1136         uint32_t chipAtt;       /* See definitions for Chip Attention
1137                                    register */
1138         uint32_t hostStatus;    /* See definitions for Host Status register */
1139         uint32_t hostControl;   /* See definitions for Host Control register */
1140         uint32_t buiConfig;     /* See definitions for BIU configuration
1141                                    register */
1142 } FF_REGS;
1143
1144 /* IO Register size in bytes */
1145 #define FF_REG_AREA_SIZE       256
1146
1147 /* Host Attention Register */
1148
1149 #define HA_REG_OFFSET  0        /* Byte offset from register base address */
1150
1151 #define HA_R0RE_REQ    0x00000001       /* Bit  0 */
1152 #define HA_R0CE_RSP    0x00000002       /* Bit  1 */
1153 #define HA_R0ATT       0x00000008       /* Bit  3 */
1154 #define HA_R1RE_REQ    0x00000010       /* Bit  4 */
1155 #define HA_R1CE_RSP    0x00000020       /* Bit  5 */
1156 #define HA_R1ATT       0x00000080       /* Bit  7 */
1157 #define HA_R2RE_REQ    0x00000100       /* Bit  8 */
1158 #define HA_R2CE_RSP    0x00000200       /* Bit  9 */
1159 #define HA_R2ATT       0x00000800       /* Bit 11 */
1160 #define HA_R3RE_REQ    0x00001000       /* Bit 12 */
1161 #define HA_R3CE_RSP    0x00002000       /* Bit 13 */
1162 #define HA_R3ATT       0x00008000       /* Bit 15 */
1163 #define HA_LATT        0x20000000       /* Bit 29 */
1164 #define HA_MBATT       0x40000000       /* Bit 30 */
1165 #define HA_ERATT       0x80000000       /* Bit 31 */
1166
1167 #define HA_RXRE_REQ    0x00000001       /* Bit  0 */
1168 #define HA_RXCE_RSP    0x00000002       /* Bit  1 */
1169 #define HA_RXATT       0x00000008       /* Bit  3 */
1170 #define HA_RXMASK      0x0000000f
1171
1172 /* Chip Attention Register */
1173
1174 #define CA_REG_OFFSET  4        /* Byte offset from register base address */
1175
1176 #define CA_R0CE_REQ    0x00000001       /* Bit  0 */
1177 #define CA_R0RE_RSP    0x00000002       /* Bit  1 */
1178 #define CA_R0ATT       0x00000008       /* Bit  3 */
1179 #define CA_R1CE_REQ    0x00000010       /* Bit  4 */
1180 #define CA_R1RE_RSP    0x00000020       /* Bit  5 */
1181 #define CA_R1ATT       0x00000080       /* Bit  7 */
1182 #define CA_R2CE_REQ    0x00000100       /* Bit  8 */
1183 #define CA_R2RE_RSP    0x00000200       /* Bit  9 */
1184 #define CA_R2ATT       0x00000800       /* Bit 11 */
1185 #define CA_R3CE_REQ    0x00001000       /* Bit 12 */
1186 #define CA_R3RE_RSP    0x00002000       /* Bit 13 */
1187 #define CA_R3ATT       0x00008000       /* Bit 15 */
1188 #define CA_MBATT       0x40000000       /* Bit 30 */
1189
1190 /* Host Status Register */
1191
1192 #define HS_REG_OFFSET  8        /* Byte offset from register base address */
1193
1194 #define HS_MBRDY       0x00400000       /* Bit 22 */
1195 #define HS_FFRDY       0x00800000       /* Bit 23 */
1196 #define HS_FFER8       0x01000000       /* Bit 24 */
1197 #define HS_FFER7       0x02000000       /* Bit 25 */
1198 #define HS_FFER6       0x04000000       /* Bit 26 */
1199 #define HS_FFER5       0x08000000       /* Bit 27 */
1200 #define HS_FFER4       0x10000000       /* Bit 28 */
1201 #define HS_FFER3       0x20000000       /* Bit 29 */
1202 #define HS_FFER2       0x40000000       /* Bit 30 */
1203 #define HS_FFER1       0x80000000       /* Bit 31 */
1204 #define HS_FFERM       0xFF000000       /* Mask for error bits 31:24 */
1205
1206 /* Host Control Register */
1207
1208 #define HC_REG_OFFSET  12       /* Word offset from register base address */
1209
1210 #define HC_MBINT_ENA   0x00000001       /* Bit  0 */
1211 #define HC_R0INT_ENA   0x00000002       /* Bit  1 */
1212 #define HC_R1INT_ENA   0x00000004       /* Bit  2 */
1213 #define HC_R2INT_ENA   0x00000008       /* Bit  3 */
1214 #define HC_R3INT_ENA   0x00000010       /* Bit  4 */
1215 #define HC_INITHBI     0x02000000       /* Bit 25 */
1216 #define HC_INITMB      0x04000000       /* Bit 26 */
1217 #define HC_INITFF      0x08000000       /* Bit 27 */
1218 #define HC_LAINT_ENA   0x20000000       /* Bit 29 */
1219 #define HC_ERINT_ENA   0x80000000       /* Bit 31 */
1220
1221 /* Mailbox Commands */
1222 #define MBX_SHUTDOWN        0x00        /* terminate testing */
1223 #define MBX_LOAD_SM         0x01
1224 #define MBX_READ_NV         0x02
1225 #define MBX_WRITE_NV        0x03
1226 #define MBX_RUN_BIU_DIAG    0x04
1227 #define MBX_INIT_LINK       0x05
1228 #define MBX_DOWN_LINK       0x06
1229 #define MBX_CONFIG_LINK     0x07
1230 #define MBX_CONFIG_RING     0x09
1231 #define MBX_RESET_RING      0x0A
1232 #define MBX_READ_CONFIG     0x0B
1233 #define MBX_READ_RCONFIG    0x0C
1234 #define MBX_READ_SPARM      0x0D
1235 #define MBX_READ_STATUS     0x0E
1236 #define MBX_READ_RPI        0x0F
1237 #define MBX_READ_XRI        0x10
1238 #define MBX_READ_REV        0x11
1239 #define MBX_READ_LNK_STAT   0x12
1240 #define MBX_REG_LOGIN       0x13
1241 #define MBX_UNREG_LOGIN     0x14
1242 #define MBX_READ_LA         0x15
1243 #define MBX_CLEAR_LA        0x16
1244 #define MBX_DUMP_MEMORY     0x17
1245 #define MBX_DUMP_CONTEXT    0x18
1246 #define MBX_RUN_DIAGS       0x19
1247 #define MBX_RESTART         0x1A
1248 #define MBX_UPDATE_CFG      0x1B
1249 #define MBX_DOWN_LOAD       0x1C
1250 #define MBX_DEL_LD_ENTRY    0x1D
1251 #define MBX_RUN_PROGRAM     0x1E
1252 #define MBX_SET_MASK        0x20
1253 #define MBX_SET_SLIM        0x21
1254 #define MBX_UNREG_D_ID      0x23
1255 #define MBX_KILL_BOARD      0x24
1256 #define MBX_CONFIG_FARP     0x25
1257 #define MBX_BEACON          0x2A
1258
1259 #define MBX_LOAD_AREA       0x81
1260 #define MBX_RUN_BIU_DIAG64  0x84
1261 #define MBX_CONFIG_PORT     0x88
1262 #define MBX_READ_SPARM64    0x8D
1263 #define MBX_READ_RPI64      0x8F
1264 #define MBX_REG_LOGIN64     0x93
1265 #define MBX_READ_LA64       0x95
1266
1267 #define MBX_FLASH_WR_ULA    0x98
1268 #define MBX_SET_DEBUG       0x99
1269 #define MBX_LOAD_EXP_ROM    0x9C
1270
1271 #define MBX_MAX_CMDS        0x9D
1272 #define MBX_SLI2_CMD_MASK   0x80
1273
1274 /* IOCB Commands */
1275
1276 #define CMD_RCV_SEQUENCE_CX     0x01
1277 #define CMD_XMIT_SEQUENCE_CR    0x02
1278 #define CMD_XMIT_SEQUENCE_CX    0x03
1279 #define CMD_XMIT_BCAST_CN       0x04
1280 #define CMD_XMIT_BCAST_CX       0x05
1281 #define CMD_QUE_RING_BUF_CN     0x06
1282 #define CMD_QUE_XRI_BUF_CX      0x07
1283 #define CMD_IOCB_CONTINUE_CN    0x08
1284 #define CMD_RET_XRI_BUF_CX      0x09
1285 #define CMD_ELS_REQUEST_CR      0x0A
1286 #define CMD_ELS_REQUEST_CX      0x0B
1287 #define CMD_RCV_ELS_REQ_CX      0x0D
1288 #define CMD_ABORT_XRI_CN        0x0E
1289 #define CMD_ABORT_XRI_CX        0x0F
1290 #define CMD_CLOSE_XRI_CN        0x10
1291 #define CMD_CLOSE_XRI_CX        0x11
1292 #define CMD_CREATE_XRI_CR       0x12
1293 #define CMD_CREATE_XRI_CX       0x13
1294 #define CMD_GET_RPI_CN          0x14
1295 #define CMD_XMIT_ELS_RSP_CX     0x15
1296 #define CMD_GET_RPI_CR          0x16
1297 #define CMD_XRI_ABORTED_CX      0x17
1298 #define CMD_FCP_IWRITE_CR       0x18
1299 #define CMD_FCP_IWRITE_CX       0x19
1300 #define CMD_FCP_IREAD_CR        0x1A
1301 #define CMD_FCP_IREAD_CX        0x1B
1302 #define CMD_FCP_ICMND_CR        0x1C
1303 #define CMD_FCP_ICMND_CX        0x1D
1304 #define CMD_FCP_TSEND_CX        0x1F
1305 #define CMD_FCP_TRECEIVE_CX     0x21
1306 #define CMD_FCP_TRSP_CX         0x23
1307 #define CMD_FCP_AUTO_TRSP_CX    0x29
1308
1309 #define CMD_ADAPTER_MSG         0x20
1310 #define CMD_ADAPTER_DUMP        0x22
1311
1312 /*  SLI_2 IOCB Command Set */
1313
1314 #define CMD_RCV_SEQUENCE64_CX   0x81
1315 #define CMD_XMIT_SEQUENCE64_CR  0x82
1316 #define CMD_XMIT_SEQUENCE64_CX  0x83
1317 #define CMD_XMIT_BCAST64_CN     0x84
1318 #define CMD_XMIT_BCAST64_CX     0x85
1319 #define CMD_QUE_RING_BUF64_CN   0x86
1320 #define CMD_QUE_XRI_BUF64_CX    0x87
1321 #define CMD_IOCB_CONTINUE64_CN  0x88
1322 #define CMD_RET_XRI_BUF64_CX    0x89
1323 #define CMD_ELS_REQUEST64_CR    0x8A
1324 #define CMD_ELS_REQUEST64_CX    0x8B
1325 #define CMD_ABORT_MXRI64_CN     0x8C
1326 #define CMD_RCV_ELS_REQ64_CX    0x8D
1327 #define CMD_XMIT_ELS_RSP64_CX   0x95
1328 #define CMD_FCP_IWRITE64_CR     0x98
1329 #define CMD_FCP_IWRITE64_CX     0x99
1330 #define CMD_FCP_IREAD64_CR      0x9A
1331 #define CMD_FCP_IREAD64_CX      0x9B
1332 #define CMD_FCP_ICMND64_CR      0x9C
1333 #define CMD_FCP_ICMND64_CX      0x9D
1334 #define CMD_FCP_TSEND64_CX      0x9F
1335 #define CMD_FCP_TRECEIVE64_CX   0xA1
1336 #define CMD_FCP_TRSP64_CX       0xA3
1337
1338 #define CMD_GEN_REQUEST64_CR    0xC2
1339 #define CMD_GEN_REQUEST64_CX    0xC3
1340
1341 #define CMD_MAX_IOCB_CMD        0xE6
1342 #define CMD_IOCB_MASK           0xff
1343
1344 #define MAX_MSG_DATA            28      /* max msg data in CMD_ADAPTER_MSG
1345                                            iocb */
1346 #define LPFC_MAX_ADPTMSG         32     /* max msg data */
1347 /*
1348  *  Define Status
1349  */
1350 #define MBX_SUCCESS                 0
1351 #define MBXERR_NUM_RINGS            1
1352 #define MBXERR_NUM_IOCBS            2
1353 #define MBXERR_IOCBS_EXCEEDED       3
1354 #define MBXERR_BAD_RING_NUMBER      4
1355 #define MBXERR_MASK_ENTRIES_RANGE   5
1356 #define MBXERR_MASKS_EXCEEDED       6
1357 #define MBXERR_BAD_PROFILE          7
1358 #define MBXERR_BAD_DEF_CLASS        8
1359 #define MBXERR_BAD_MAX_RESPONDER    9
1360 #define MBXERR_BAD_MAX_ORIGINATOR   10
1361 #define MBXERR_RPI_REGISTERED       11
1362 #define MBXERR_RPI_FULL             12
1363 #define MBXERR_NO_RESOURCES         13
1364 #define MBXERR_BAD_RCV_LENGTH       14
1365 #define MBXERR_DMA_ERROR            15
1366 #define MBXERR_ERROR                16
1367 #define MBX_NOT_FINISHED           255
1368
1369 #define MBX_BUSY                   0xffffff /* Attempted cmd to busy Mailbox */
1370 #define MBX_TIMEOUT                0xfffffe /* time-out expired waiting for */
1371
1372 /*
1373  *    Begin Structure Definitions for Mailbox Commands
1374  */
1375
1376 typedef struct {
1377 #ifdef __BIG_ENDIAN_BITFIELD
1378         uint8_t tval;
1379         uint8_t tmask;
1380         uint8_t rval;
1381         uint8_t rmask;
1382 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1383         uint8_t rmask;
1384         uint8_t rval;
1385         uint8_t tmask;
1386         uint8_t tval;
1387 #endif
1388 } RR_REG;
1389
1390 struct ulp_bde {
1391         uint32_t bdeAddress;
1392 #ifdef __BIG_ENDIAN_BITFIELD
1393         uint32_t bdeReserved:4;
1394         uint32_t bdeAddrHigh:4;
1395         uint32_t bdeSize:24;
1396 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1397         uint32_t bdeSize:24;
1398         uint32_t bdeAddrHigh:4;
1399         uint32_t bdeReserved:4;
1400 #endif
1401 };
1402
1403 struct ulp_bde64 {      /* SLI-2 */
1404         union ULP_BDE_TUS {
1405                 uint32_t w;
1406                 struct {
1407 #ifdef __BIG_ENDIAN_BITFIELD
1408                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
1409                                                    VALUE !! */
1410                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
1411 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1412                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
1413                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
1414                                                    VALUE !! */
1415 #endif
1416
1417 #define BUFF_USE_RSVD       0x01        /* bdeFlags */
1418 #define BUFF_USE_INTRPT     0x02        /* Not Implemented with LP6000 */
1419 #define BUFF_USE_CMND       0x04        /* Optional, 1=cmd/rsp 0=data buffer */
1420 #define BUFF_USE_RCV        0x08        /*  "" "", 1=rcv buffer, 0=xmit
1421                                             buffer */
1422 #define BUFF_TYPE_32BIT     0x10        /*  "" "", 1=32 bit addr 0=64 bit
1423                                             addr */
1424 #define BUFF_TYPE_SPECIAL   0x20        /* Not Implemented with LP6000  */
1425 #define BUFF_TYPE_BDL       0x40        /* Optional,  may be set in BDL */
1426 #define BUFF_TYPE_INVALID   0x80        /*  ""  "" */
1427                 } f;
1428         } tus;
1429         uint32_t addrLow;
1430         uint32_t addrHigh;
1431 };
1432 #define BDE64_SIZE_WORD 0
1433 #define BPL64_SIZE_WORD 0x40
1434
1435 typedef struct ULP_BDL {        /* SLI-2 */
1436 #ifdef __BIG_ENDIAN_BITFIELD
1437         uint32_t bdeFlags:8;    /* BDL Flags */
1438         uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
1439 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1440         uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
1441         uint32_t bdeFlags:8;    /* BDL Flags */
1442 #endif
1443
1444         uint32_t addrLow;       /* Address 0:31 */
1445         uint32_t addrHigh;      /* Address 32:63 */
1446         uint32_t ulpIoTag32;    /* Can be used for 32 bit I/O Tag */
1447 } ULP_BDL;
1448
1449 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1450
1451 typedef struct {
1452 #ifdef __BIG_ENDIAN_BITFIELD
1453         uint32_t rsvd2:25;
1454         uint32_t acknowledgment:1;
1455         uint32_t version:1;
1456         uint32_t erase_or_prog:1;
1457         uint32_t update_flash:1;
1458         uint32_t update_ram:1;
1459         uint32_t method:1;
1460         uint32_t load_cmplt:1;
1461 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1462         uint32_t load_cmplt:1;
1463         uint32_t method:1;
1464         uint32_t update_ram:1;
1465         uint32_t update_flash:1;
1466         uint32_t erase_or_prog:1;
1467         uint32_t version:1;
1468         uint32_t acknowledgment:1;
1469         uint32_t rsvd2:25;
1470 #endif
1471
1472         uint32_t dl_to_adr_low;
1473         uint32_t dl_to_adr_high;
1474         uint32_t dl_len;
1475         union {
1476                 uint32_t dl_from_mbx_offset;
1477                 struct ulp_bde dl_from_bde;
1478                 struct ulp_bde64 dl_from_bde64;
1479         } un;
1480
1481 } LOAD_SM_VAR;
1482
1483 /* Structure for MB Command READ_NVPARM (02) */
1484
1485 typedef struct {
1486         uint32_t rsvd1[3];      /* Read as all one's */
1487         uint32_t rsvd2;         /* Read as all zero's */
1488         uint32_t portname[2];   /* N_PORT name */
1489         uint32_t nodename[2];   /* NODE name */
1490
1491 #ifdef __BIG_ENDIAN_BITFIELD
1492         uint32_t pref_DID:24;
1493         uint32_t hardAL_PA:8;
1494 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1495         uint32_t hardAL_PA:8;
1496         uint32_t pref_DID:24;
1497 #endif
1498
1499         uint32_t rsvd3[21];     /* Read as all one's */
1500 } READ_NV_VAR;
1501
1502 /* Structure for MB Command WRITE_NVPARMS (03) */
1503
1504 typedef struct {
1505         uint32_t rsvd1[3];      /* Must be all one's */
1506         uint32_t rsvd2;         /* Must be all zero's */
1507         uint32_t portname[2];   /* N_PORT name */
1508         uint32_t nodename[2];   /* NODE name */
1509
1510 #ifdef __BIG_ENDIAN_BITFIELD
1511         uint32_t pref_DID:24;
1512         uint32_t hardAL_PA:8;
1513 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1514         uint32_t hardAL_PA:8;
1515         uint32_t pref_DID:24;
1516 #endif
1517
1518         uint32_t rsvd3[21];     /* Must be all one's */
1519 } WRITE_NV_VAR;
1520
1521 /* Structure for MB Command RUN_BIU_DIAG (04) */
1522 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1523
1524 typedef struct {
1525         uint32_t rsvd1;
1526         union {
1527                 struct {
1528                         struct ulp_bde xmit_bde;
1529                         struct ulp_bde rcv_bde;
1530                 } s1;
1531                 struct {
1532                         struct ulp_bde64 xmit_bde64;
1533                         struct ulp_bde64 rcv_bde64;
1534                 } s2;
1535         } un;
1536 } BIU_DIAG_VAR;
1537
1538 /* Structure for MB Command INIT_LINK (05) */
1539
1540 typedef struct {
1541 #ifdef __BIG_ENDIAN_BITFIELD
1542         uint32_t rsvd1:24;
1543         uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1544 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1545         uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1546         uint32_t rsvd1:24;
1547 #endif
1548
1549 #ifdef __BIG_ENDIAN_BITFIELD
1550         uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
1551         uint8_t rsvd2;
1552         uint16_t link_flags;
1553 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1554         uint16_t link_flags;
1555         uint8_t rsvd2;
1556         uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
1557 #endif
1558
1559 #define FLAGS_LOCAL_LB               0x01 /* link_flags (=1) ENDEC loopback */
1560 #define FLAGS_TOPOLOGY_MODE_LOOP_PT  0x00 /* Attempt loop then pt-pt */
1561 #define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
1562 #define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
1563 #define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
1564 #define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
1565
1566 #define FLAGS_TOPOLOGY_FAILOVER      0x0400     /* Bit 10 */
1567 #define FLAGS_LINK_SPEED             0x0800     /* Bit 11 */
1568 #define FLAGS_IMED_ABORT             0x04000    /* Bit 14 */
1569
1570         uint32_t link_speed;
1571 #define LINK_SPEED_AUTO 0       /* Auto selection */
1572 #define LINK_SPEED_1G   1       /* 1 Gigabaud */
1573 #define LINK_SPEED_2G   2       /* 2 Gigabaud */
1574 #define LINK_SPEED_4G   4       /* 4 Gigabaud */
1575 #define LINK_SPEED_8G   8       /* 8 Gigabaud */
1576 #define LINK_SPEED_10G   16      /* 10 Gigabaud */
1577
1578 } INIT_LINK_VAR;
1579
1580 /* Structure for MB Command DOWN_LINK (06) */
1581
1582 typedef struct {
1583         uint32_t rsvd1;
1584 } DOWN_LINK_VAR;
1585
1586 /* Structure for MB Command CONFIG_LINK (07) */
1587
1588 typedef struct {
1589 #ifdef __BIG_ENDIAN_BITFIELD
1590         uint32_t cr:1;
1591         uint32_t ci:1;
1592         uint32_t cr_delay:6;
1593         uint32_t cr_count:8;
1594         uint32_t rsvd1:8;
1595         uint32_t MaxBBC:8;
1596 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1597         uint32_t MaxBBC:8;
1598         uint32_t rsvd1:8;
1599         uint32_t cr_count:8;
1600         uint32_t cr_delay:6;
1601         uint32_t ci:1;
1602         uint32_t cr:1;
1603 #endif
1604
1605         uint32_t myId;
1606         uint32_t rsvd2;
1607         uint32_t edtov;
1608         uint32_t arbtov;
1609         uint32_t ratov;
1610         uint32_t rttov;
1611         uint32_t altov;
1612         uint32_t crtov;
1613         uint32_t citov;
1614 #ifdef __BIG_ENDIAN_BITFIELD
1615         uint32_t rrq_enable:1;
1616         uint32_t rrq_immed:1;
1617         uint32_t rsvd4:29;
1618         uint32_t ack0_enable:1;
1619 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1620         uint32_t ack0_enable:1;
1621         uint32_t rsvd4:29;
1622         uint32_t rrq_immed:1;
1623         uint32_t rrq_enable:1;
1624 #endif
1625 } CONFIG_LINK;
1626
1627 /* Structure for MB Command PART_SLIM (08)
1628  * will be removed since SLI1 is no longer supported!
1629  */
1630 typedef struct {
1631 #ifdef __BIG_ENDIAN_BITFIELD
1632         uint16_t offCiocb;
1633         uint16_t numCiocb;
1634         uint16_t offRiocb;
1635         uint16_t numRiocb;
1636 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1637         uint16_t numCiocb;
1638         uint16_t offCiocb;
1639         uint16_t numRiocb;
1640         uint16_t offRiocb;
1641 #endif
1642 } RING_DEF;
1643
1644 typedef struct {
1645 #ifdef __BIG_ENDIAN_BITFIELD
1646         uint32_t unused1:24;
1647         uint32_t numRing:8;
1648 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1649         uint32_t numRing:8;
1650         uint32_t unused1:24;
1651 #endif
1652
1653         RING_DEF ringdef[4];
1654         uint32_t hbainit;
1655 } PART_SLIM_VAR;
1656
1657 /* Structure for MB Command CONFIG_RING (09) */
1658
1659 typedef struct {
1660 #ifdef __BIG_ENDIAN_BITFIELD
1661         uint32_t unused2:6;
1662         uint32_t recvSeq:1;
1663         uint32_t recvNotify:1;
1664         uint32_t numMask:8;
1665         uint32_t profile:8;
1666         uint32_t unused1:4;
1667         uint32_t ring:4;
1668 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1669         uint32_t ring:4;
1670         uint32_t unused1:4;
1671         uint32_t profile:8;
1672         uint32_t numMask:8;
1673         uint32_t recvNotify:1;
1674         uint32_t recvSeq:1;
1675         uint32_t unused2:6;
1676 #endif
1677
1678 #ifdef __BIG_ENDIAN_BITFIELD
1679         uint16_t maxRespXchg;
1680         uint16_t maxOrigXchg;
1681 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1682         uint16_t maxOrigXchg;
1683         uint16_t maxRespXchg;
1684 #endif
1685
1686         RR_REG rrRegs[6];
1687 } CONFIG_RING_VAR;
1688
1689 /* Structure for MB Command RESET_RING (10) */
1690
1691 typedef struct {
1692         uint32_t ring_no;
1693 } RESET_RING_VAR;
1694
1695 /* Structure for MB Command READ_CONFIG (11) */
1696
1697 typedef struct {
1698 #ifdef __BIG_ENDIAN_BITFIELD
1699         uint32_t cr:1;
1700         uint32_t ci:1;
1701         uint32_t cr_delay:6;
1702         uint32_t cr_count:8;
1703         uint32_t InitBBC:8;
1704         uint32_t MaxBBC:8;
1705 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1706         uint32_t MaxBBC:8;
1707         uint32_t InitBBC:8;
1708         uint32_t cr_count:8;
1709         uint32_t cr_delay:6;
1710         uint32_t ci:1;
1711         uint32_t cr:1;
1712 #endif
1713
1714 #ifdef __BIG_ENDIAN_BITFIELD
1715         uint32_t topology:8;
1716         uint32_t myDid:24;
1717 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1718         uint32_t myDid:24;
1719         uint32_t topology:8;
1720 #endif
1721
1722         /* Defines for topology (defined previously) */
1723 #ifdef __BIG_ENDIAN_BITFIELD
1724         uint32_t AR:1;
1725         uint32_t IR:1;
1726         uint32_t rsvd1:29;
1727         uint32_t ack0:1;
1728 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1729         uint32_t ack0:1;
1730         uint32_t rsvd1:29;
1731         uint32_t IR:1;
1732         uint32_t AR:1;
1733 #endif
1734
1735         uint32_t edtov;
1736         uint32_t arbtov;
1737         uint32_t ratov;
1738         uint32_t rttov;
1739         uint32_t altov;
1740         uint32_t lmt;
1741 #define LMT_RESERVED  0x000    /* Not used */
1742 #define LMT_1Gb       0x004
1743 #define LMT_2Gb       0x008
1744 #define LMT_4Gb       0x040
1745 #define LMT_8Gb       0x080
1746 #define LMT_10Gb      0x100
1747
1748
1749         uint32_t rsvd2;
1750         uint32_t rsvd3;
1751         uint32_t max_xri;
1752         uint32_t max_iocb;
1753         uint32_t max_rpi;
1754         uint32_t avail_xri;
1755         uint32_t avail_iocb;
1756         uint32_t avail_rpi;
1757         uint32_t default_rpi;
1758 } READ_CONFIG_VAR;
1759
1760 /* Structure for MB Command READ_RCONFIG (12) */
1761
1762 typedef struct {
1763 #ifdef __BIG_ENDIAN_BITFIELD
1764         uint32_t rsvd2:7;
1765         uint32_t recvNotify:1;
1766         uint32_t numMask:8;
1767         uint32_t profile:8;
1768         uint32_t rsvd1:4;
1769         uint32_t ring:4;
1770 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1771         uint32_t ring:4;
1772         uint32_t rsvd1:4;
1773         uint32_t profile:8;
1774         uint32_t numMask:8;
1775         uint32_t recvNotify:1;
1776         uint32_t rsvd2:7;
1777 #endif
1778
1779 #ifdef __BIG_ENDIAN_BITFIELD
1780         uint16_t maxResp;
1781         uint16_t maxOrig;
1782 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1783         uint16_t maxOrig;
1784         uint16_t maxResp;
1785 #endif
1786
1787         RR_REG rrRegs[6];
1788
1789 #ifdef __BIG_ENDIAN_BITFIELD
1790         uint16_t cmdRingOffset;
1791         uint16_t cmdEntryCnt;
1792         uint16_t rspRingOffset;
1793         uint16_t rspEntryCnt;
1794         uint16_t nextCmdOffset;
1795         uint16_t rsvd3;
1796         uint16_t nextRspOffset;
1797         uint16_t rsvd4;
1798 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1799         uint16_t cmdEntryCnt;
1800         uint16_t cmdRingOffset;
1801         uint16_t rspEntryCnt;
1802         uint16_t rspRingOffset;
1803         uint16_t rsvd3;
1804         uint16_t nextCmdOffset;
1805         uint16_t rsvd4;
1806         uint16_t nextRspOffset;
1807 #endif
1808 } READ_RCONF_VAR;
1809
1810 /* Structure for MB Command READ_SPARM (13) */
1811 /* Structure for MB Command READ_SPARM64 (0x8D) */
1812
1813 typedef struct {
1814         uint32_t rsvd1;
1815         uint32_t rsvd2;
1816         union {
1817                 struct ulp_bde sp; /* This BDE points to struct serv_parm
1818                                       structure */
1819                 struct ulp_bde64 sp64;
1820         } un;
1821 } READ_SPARM_VAR;
1822
1823 /* Structure for MB Command READ_STATUS (14) */
1824
1825 typedef struct {
1826 #ifdef __BIG_ENDIAN_BITFIELD
1827         uint32_t rsvd1:31;
1828         uint32_t clrCounters:1;
1829         uint16_t activeXriCnt;
1830         uint16_t activeRpiCnt;
1831 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1832         uint32_t clrCounters:1;
1833         uint32_t rsvd1:31;
1834         uint16_t activeRpiCnt;
1835         uint16_t activeXriCnt;
1836 #endif
1837
1838         uint32_t xmitByteCnt;
1839         uint32_t rcvByteCnt;
1840         uint32_t xmitFrameCnt;
1841         uint32_t rcvFrameCnt;
1842         uint32_t xmitSeqCnt;
1843         uint32_t rcvSeqCnt;
1844         uint32_t totalOrigExchanges;
1845         uint32_t totalRespExchanges;
1846         uint32_t rcvPbsyCnt;
1847         uint32_t rcvFbsyCnt;
1848 } READ_STATUS_VAR;
1849
1850 /* Structure for MB Command READ_RPI (15) */
1851 /* Structure for MB Command READ_RPI64 (0x8F) */
1852
1853 typedef struct {
1854 #ifdef __BIG_ENDIAN_BITFIELD
1855         uint16_t nextRpi;
1856         uint16_t reqRpi;
1857         uint32_t rsvd2:8;
1858         uint32_t DID:24;
1859 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1860         uint16_t reqRpi;
1861         uint16_t nextRpi;
1862         uint32_t DID:24;
1863         uint32_t rsvd2:8;
1864 #endif
1865
1866         union {
1867                 struct ulp_bde sp;
1868                 struct ulp_bde64 sp64;
1869         } un;
1870
1871 } READ_RPI_VAR;
1872
1873 /* Structure for MB Command READ_XRI (16) */
1874
1875 typedef struct {
1876 #ifdef __BIG_ENDIAN_BITFIELD
1877         uint16_t nextXri;
1878         uint16_t reqXri;
1879         uint16_t rsvd1;
1880         uint16_t rpi;
1881         uint32_t rsvd2:8;
1882         uint32_t DID:24;
1883         uint32_t rsvd3:8;
1884         uint32_t SID:24;
1885         uint32_t rsvd4;
1886         uint8_t seqId;
1887         uint8_t rsvd5;
1888         uint16_t seqCount;
1889         uint16_t oxId;
1890         uint16_t rxId;
1891         uint32_t rsvd6:30;
1892         uint32_t si:1;
1893         uint32_t exchOrig:1;
1894 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1895         uint16_t reqXri;
1896         uint16_t nextXri;
1897         uint16_t rpi;
1898         uint16_t rsvd1;
1899         uint32_t DID:24;
1900         uint32_t rsvd2:8;
1901         uint32_t SID:24;
1902         uint32_t rsvd3:8;
1903         uint32_t rsvd4;
1904         uint16_t seqCount;
1905         uint8_t rsvd5;
1906         uint8_t seqId;
1907         uint16_t rxId;
1908         uint16_t oxId;
1909         uint32_t exchOrig:1;
1910         uint32_t si:1;
1911         uint32_t rsvd6:30;
1912 #endif
1913 } READ_XRI_VAR;
1914
1915 /* Structure for MB Command READ_REV (17) */
1916
1917 typedef struct {
1918 #ifdef __BIG_ENDIAN_BITFIELD
1919         uint32_t cv:1;
1920         uint32_t rr:1;
1921         uint32_t rsvd1:29;
1922         uint32_t rv:1;
1923 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1924         uint32_t rv:1;
1925         uint32_t rsvd1:29;
1926         uint32_t rr:1;
1927         uint32_t cv:1;
1928 #endif
1929
1930         uint32_t biuRev;
1931         uint32_t smRev;
1932         union {
1933                 uint32_t smFwRev;
1934                 struct {
1935 #ifdef __BIG_ENDIAN_BITFIELD
1936                         uint8_t ProgType;
1937                         uint8_t ProgId;
1938                         uint16_t ProgVer:4;
1939                         uint16_t ProgRev:4;
1940                         uint16_t ProgFixLvl:2;
1941                         uint16_t ProgDistType:2;
1942                         uint16_t DistCnt:4;
1943 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1944                         uint16_t DistCnt:4;
1945                         uint16_t ProgDistType:2;
1946                         uint16_t ProgFixLvl:2;
1947                         uint16_t ProgRev:4;
1948                         uint16_t ProgVer:4;
1949                         uint8_t ProgId;
1950                         uint8_t ProgType;
1951 #endif
1952
1953                 } b;
1954         } un;
1955         uint32_t endecRev;
1956 #ifdef __BIG_ENDIAN_BITFIELD
1957         uint8_t feaLevelHigh;
1958         uint8_t feaLevelLow;
1959         uint8_t fcphHigh;
1960         uint8_t fcphLow;
1961 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1962         uint8_t fcphLow;
1963         uint8_t fcphHigh;
1964         uint8_t feaLevelLow;
1965         uint8_t feaLevelHigh;
1966 #endif
1967
1968         uint32_t postKernRev;
1969         uint32_t opFwRev;
1970         uint8_t opFwName[16];
1971         uint32_t sli1FwRev;
1972         uint8_t sli1FwName[16];
1973         uint32_t sli2FwRev;
1974         uint8_t sli2FwName[16];
1975         uint32_t rsvd2;
1976         uint32_t RandomData[7];
1977 } READ_REV_VAR;
1978
1979 /* Structure for MB Command READ_LINK_STAT (18) */
1980
1981 typedef struct {
1982         uint32_t rsvd1;
1983         uint32_t linkFailureCnt;
1984         uint32_t lossSyncCnt;
1985
1986         uint32_t lossSignalCnt;
1987         uint32_t primSeqErrCnt;
1988         uint32_t invalidXmitWord;
1989         uint32_t crcCnt;
1990         uint32_t primSeqTimeout;
1991         uint32_t elasticOverrun;
1992         uint32_t arbTimeout;
1993 } READ_LNK_VAR;
1994
1995 /* Structure for MB Command REG_LOGIN (19) */
1996 /* Structure for MB Command REG_LOGIN64 (0x93) */
1997
1998 typedef struct {
1999 #ifdef __BIG_ENDIAN_BITFIELD
2000         uint16_t rsvd1;
2001         uint16_t rpi;
2002         uint32_t rsvd2:8;
2003         uint32_t did:24;
2004 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2005         uint16_t rpi;
2006         uint16_t rsvd1;
2007         uint32_t did:24;
2008         uint32_t rsvd2:8;
2009 #endif
2010
2011         union {
2012                 struct ulp_bde sp;
2013                 struct ulp_bde64 sp64;
2014         } un;
2015
2016 } REG_LOGIN_VAR;
2017
2018 /* Word 30 contents for REG_LOGIN */
2019 typedef union {
2020         struct {
2021 #ifdef __BIG_ENDIAN_BITFIELD
2022                 uint16_t rsvd1:12;
2023                 uint16_t wd30_class:4;
2024                 uint16_t xri;
2025 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2026                 uint16_t xri;
2027                 uint16_t wd30_class:4;
2028                 uint16_t rsvd1:12;
2029 #endif
2030         } f;
2031         uint32_t word;
2032 } REG_WD30;
2033
2034 /* Structure for MB Command UNREG_LOGIN (20) */
2035
2036 typedef struct {
2037 #ifdef __BIG_ENDIAN_BITFIELD
2038         uint16_t rsvd1;
2039         uint16_t rpi;
2040 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2041         uint16_t rpi;
2042         uint16_t rsvd1;
2043 #endif
2044 } UNREG_LOGIN_VAR;
2045
2046 /* Structure for MB Command UNREG_D_ID (0x23) */
2047
2048 typedef struct {
2049         uint32_t did;
2050 } UNREG_D_ID_VAR;
2051
2052 /* Structure for MB Command READ_LA (21) */
2053 /* Structure for MB Command READ_LA64 (0x95) */
2054
2055 typedef struct {
2056         uint32_t eventTag;      /* Event tag */
2057 #ifdef __BIG_ENDIAN_BITFIELD
2058         uint32_t rsvd1:22;
2059         uint32_t pb:1;
2060         uint32_t il:1;
2061         uint32_t attType:8;
2062 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2063         uint32_t attType:8;
2064         uint32_t il:1;
2065         uint32_t pb:1;
2066         uint32_t rsvd1:22;
2067 #endif
2068
2069 #define AT_RESERVED    0x00     /* Reserved - attType */
2070 #define AT_LINK_UP     0x01     /* Link is up */
2071 #define AT_LINK_DOWN   0x02     /* Link is down */
2072
2073 #ifdef __BIG_ENDIAN_BITFIELD
2074         uint8_t granted_AL_PA;
2075         uint8_t lipAlPs;
2076         uint8_t lipType;
2077         uint8_t topology;
2078 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2079         uint8_t topology;
2080         uint8_t lipType;
2081         uint8_t lipAlPs;
2082         uint8_t granted_AL_PA;
2083 #endif
2084
2085 #define TOPOLOGY_PT_PT 0x01     /* Topology is pt-pt / pt-fabric */
2086 #define TOPOLOGY_LOOP  0x02     /* Topology is FC-AL */
2087
2088         union {
2089                 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2090                                            to */
2091                 /* store the LILP AL_PA position map into */
2092                 struct ulp_bde64 lilpBde64;
2093         } un;
2094
2095 #ifdef __BIG_ENDIAN_BITFIELD
2096         uint32_t Dlu:1;
2097         uint32_t Dtf:1;
2098         uint32_t Drsvd2:14;
2099         uint32_t DlnkSpeed:8;
2100         uint32_t DnlPort:4;
2101         uint32_t Dtx:2;
2102         uint32_t Drx:2;
2103 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2104         uint32_t Drx:2;
2105         uint32_t Dtx:2;
2106         uint32_t DnlPort:4;
2107         uint32_t DlnkSpeed:8;
2108         uint32_t Drsvd2:14;
2109         uint32_t Dtf:1;
2110         uint32_t Dlu:1;
2111 #endif
2112
2113 #ifdef __BIG_ENDIAN_BITFIELD
2114         uint32_t Ulu:1;
2115         uint32_t Utf:1;
2116         uint32_t Ursvd2:14;
2117         uint32_t UlnkSpeed:8;
2118         uint32_t UnlPort:4;
2119         uint32_t Utx:2;
2120         uint32_t Urx:2;
2121 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2122         uint32_t Urx:2;
2123         uint32_t Utx:2;
2124         uint32_t UnlPort:4;
2125         uint32_t UlnkSpeed:8;
2126         uint32_t Ursvd2:14;
2127         uint32_t Utf:1;
2128         uint32_t Ulu:1;
2129 #endif
2130
2131 #define LA_UNKNW_LINK  0x0    /* lnkSpeed */
2132 #define LA_1GHZ_LINK   0x04   /* lnkSpeed */
2133 #define LA_2GHZ_LINK   0x08   /* lnkSpeed */
2134 #define LA_4GHZ_LINK   0x10   /* lnkSpeed */
2135 #define LA_8GHZ_LINK   0x20   /* lnkSpeed */
2136 #define LA_10GHZ_LINK  0x40   /* lnkSpeed */
2137
2138 } READ_LA_VAR;
2139
2140 /* Structure for MB Command CLEAR_LA (22) */
2141
2142 typedef struct {
2143         uint32_t eventTag;      /* Event tag */
2144         uint32_t rsvd1;
2145 } CLEAR_LA_VAR;
2146
2147 /* Structure for MB Command DUMP */
2148
2149 typedef struct {
2150 #ifdef __BIG_ENDIAN_BITFIELD
2151         uint32_t rsvd:25;
2152         uint32_t ra:1;
2153         uint32_t co:1;
2154         uint32_t cv:1;
2155         uint32_t type:4;
2156         uint32_t entry_index:16;
2157         uint32_t region_id:16;
2158 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2159         uint32_t type:4;
2160         uint32_t cv:1;
2161         uint32_t co:1;
2162         uint32_t ra:1;
2163         uint32_t rsvd:25;
2164         uint32_t region_id:16;
2165         uint32_t entry_index:16;
2166 #endif
2167
2168         uint32_t rsvd1;
2169         uint32_t word_cnt;
2170         uint32_t resp_offset;
2171 } DUMP_VAR;
2172
2173 #define  DMP_MEM_REG             0x1
2174 #define  DMP_NV_PARAMS           0x2
2175
2176 #define  DMP_REGION_VPD          0xe
2177 #define  DMP_VPD_SIZE            0x400  /* maximum amount of VPD */
2178 #define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
2179 #define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
2180
2181 /* Structure for MB Command CONFIG_PORT (0x88) */
2182
2183 typedef struct {
2184         uint32_t pcbLen;
2185         uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
2186         uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
2187         uint32_t hbainit[5];
2188 } CONFIG_PORT_VAR;
2189
2190 /* SLI-2 Port Control Block */
2191
2192 /* SLIM POINTER */
2193 #define SLIMOFF 0x30            /* WORD */
2194
2195 typedef struct _SLI2_RDSC {
2196         uint32_t cmdEntries;
2197         uint32_t cmdAddrLow;
2198         uint32_t cmdAddrHigh;
2199
2200         uint32_t rspEntries;
2201         uint32_t rspAddrLow;
2202         uint32_t rspAddrHigh;
2203 } SLI2_RDSC;
2204
2205 typedef struct _PCB {
2206 #ifdef __BIG_ENDIAN_BITFIELD
2207         uint32_t type:8;
2208 #define TYPE_NATIVE_SLI2       0x01;
2209         uint32_t feature:8;
2210 #define FEATURE_INITIAL_SLI2   0x01;
2211         uint32_t rsvd:12;
2212         uint32_t maxRing:4;
2213 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2214         uint32_t maxRing:4;
2215         uint32_t rsvd:12;
2216         uint32_t feature:8;
2217 #define FEATURE_INITIAL_SLI2   0x01;
2218         uint32_t type:8;
2219 #define TYPE_NATIVE_SLI2       0x01;
2220 #endif
2221
2222         uint32_t mailBoxSize;
2223         uint32_t mbAddrLow;
2224         uint32_t mbAddrHigh;
2225
2226         uint32_t hgpAddrLow;
2227         uint32_t hgpAddrHigh;
2228
2229         uint32_t pgpAddrLow;
2230         uint32_t pgpAddrHigh;
2231         SLI2_RDSC rdsc[MAX_RINGS];
2232 } PCB_t;
2233
2234 /* NEW_FEATURE */
2235 typedef struct {
2236 #ifdef __BIG_ENDIAN_BITFIELD
2237         uint32_t rsvd0:27;
2238         uint32_t discardFarp:1;
2239         uint32_t IPEnable:1;
2240         uint32_t nodeName:1;
2241         uint32_t portName:1;
2242         uint32_t filterEnable:1;
2243 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2244         uint32_t filterEnable:1;
2245         uint32_t portName:1;
2246         uint32_t nodeName:1;
2247         uint32_t IPEnable:1;
2248         uint32_t discardFarp:1;
2249         uint32_t rsvd:27;
2250 #endif
2251
2252         uint8_t portname[8];    /* Used to be struct lpfc_name */
2253         uint8_t nodename[8];
2254         uint32_t rsvd1;
2255         uint32_t rsvd2;
2256         uint32_t rsvd3;
2257         uint32_t IPAddress;
2258 } CONFIG_FARP_VAR;
2259
2260 /* Union of all Mailbox Command types */
2261 #define MAILBOX_CMD_WSIZE       32
2262 #define MAILBOX_CMD_SIZE        (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2263
2264 typedef union {
2265         uint32_t varWords[MAILBOX_CMD_WSIZE - 1];
2266         LOAD_SM_VAR varLdSM;    /* cmd =  1 (LOAD_SM)        */
2267         READ_NV_VAR varRDnvp;   /* cmd =  2 (READ_NVPARMS)   */
2268         WRITE_NV_VAR varWTnvp;  /* cmd =  3 (WRITE_NVPARMS)  */
2269         BIU_DIAG_VAR varBIUdiag;        /* cmd =  4 (RUN_BIU_DIAG)   */
2270         INIT_LINK_VAR varInitLnk;       /* cmd =  5 (INIT_LINK)      */
2271         DOWN_LINK_VAR varDwnLnk;        /* cmd =  6 (DOWN_LINK)      */
2272         CONFIG_LINK varCfgLnk;  /* cmd =  7 (CONFIG_LINK)    */
2273         PART_SLIM_VAR varSlim;  /* cmd =  8 (PART_SLIM)      */
2274         CONFIG_RING_VAR varCfgRing;     /* cmd =  9 (CONFIG_RING)    */
2275         RESET_RING_VAR varRstRing;      /* cmd = 10 (RESET_RING)     */
2276         READ_CONFIG_VAR varRdConfig;    /* cmd = 11 (READ_CONFIG)    */
2277         READ_RCONF_VAR varRdRConfig;    /* cmd = 12 (READ_RCONFIG)   */
2278         READ_SPARM_VAR varRdSparm;      /* cmd = 13 (READ_SPARM(64)) */
2279         READ_STATUS_VAR varRdStatus;    /* cmd = 14 (READ_STATUS)    */
2280         READ_RPI_VAR varRdRPI;  /* cmd = 15 (READ_RPI(64))   */
2281         READ_XRI_VAR varRdXRI;  /* cmd = 16 (READ_XRI)       */
2282         READ_REV_VAR varRdRev;  /* cmd = 17 (READ_REV)       */
2283         READ_LNK_VAR varRdLnk;  /* cmd = 18 (READ_LNK_STAT)  */
2284         REG_LOGIN_VAR varRegLogin;      /* cmd = 19 (REG_LOGIN(64))  */
2285         UNREG_LOGIN_VAR varUnregLogin;  /* cmd = 20 (UNREG_LOGIN)    */
2286         READ_LA_VAR varReadLA;  /* cmd = 21 (READ_LA(64))    */
2287         CLEAR_LA_VAR varClearLA;        /* cmd = 22 (CLEAR_LA)       */
2288         DUMP_VAR varDmp;        /* Warm Start DUMP mbx cmd   */
2289         UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID)   */
2290         CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)  NEW_FEATURE */
2291         CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT)  */
2292 } MAILVARIANTS;
2293
2294 /*
2295  * SLI-2 specific structures
2296  */
2297
2298 struct lpfc_hgp {
2299         __le32 cmdPutInx;
2300         __le32 rspGetInx;
2301 };
2302
2303 struct lpfc_pgp {
2304         __le32 cmdGetInx;
2305         __le32 rspPutInx;
2306 };
2307
2308 typedef struct _SLI2_DESC {
2309         struct lpfc_hgp host[MAX_RINGS];
2310         uint32_t unused1[16];
2311         struct lpfc_pgp port[MAX_RINGS];
2312 } SLI2_DESC;
2313
2314 typedef union {
2315         SLI2_DESC s2;
2316 } SLI_VAR;
2317
2318 typedef struct {
2319 #ifdef __BIG_ENDIAN_BITFIELD
2320         uint16_t mbxStatus;
2321         uint8_t mbxCommand;
2322         uint8_t mbxReserved:6;
2323         uint8_t mbxHc:1;
2324         uint8_t mbxOwner:1;     /* Low order bit first word */
2325 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2326         uint8_t mbxOwner:1;     /* Low order bit first word */
2327         uint8_t mbxHc:1;
2328         uint8_t mbxReserved:6;
2329         uint8_t mbxCommand;
2330         uint16_t mbxStatus;
2331 #endif
2332
2333         MAILVARIANTS un;
2334         SLI_VAR us;
2335 } MAILBOX_t;
2336
2337 /*
2338  *    Begin Structure Definitions for IOCB Commands
2339  */
2340
2341 typedef struct {
2342 #ifdef __BIG_ENDIAN_BITFIELD
2343         uint8_t statAction;
2344         uint8_t statRsn;
2345         uint8_t statBaExp;
2346         uint8_t statLocalError;
2347 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2348         uint8_t statLocalError;
2349         uint8_t statBaExp;
2350         uint8_t statRsn;
2351         uint8_t statAction;
2352 #endif
2353         /* statRsn  P/F_RJT reason codes */
2354 #define RJT_BAD_D_ID       0x01 /* Invalid D_ID field */
2355 #define RJT_BAD_S_ID       0x02 /* Invalid S_ID field */
2356 #define RJT_UNAVAIL_TEMP   0x03 /* N_Port unavailable temp. */
2357 #define RJT_UNAVAIL_PERM   0x04 /* N_Port unavailable perm. */
2358 #define RJT_UNSUP_CLASS    0x05 /* Class not supported */
2359 #define RJT_DELIM_ERR      0x06 /* Delimiter usage error */
2360 #define RJT_UNSUP_TYPE     0x07 /* Type not supported */
2361 #define RJT_BAD_CONTROL    0x08 /* Invalid link conrtol */
2362 #define RJT_BAD_RCTL       0x09 /* R_CTL invalid */
2363 #define RJT_BAD_FCTL       0x0A /* F_CTL invalid */
2364 #define RJT_BAD_OXID       0x0B /* OX_ID invalid */
2365 #define RJT_BAD_RXID       0x0C /* RX_ID invalid */
2366 #define RJT_BAD_SEQID      0x0D /* SEQ_ID invalid */
2367 #define RJT_BAD_DFCTL      0x0E /* DF_CTL invalid */
2368 #define RJT_BAD_SEQCNT     0x0F /* SEQ_CNT invalid */
2369 #define RJT_BAD_PARM       0x10 /* Param. field invalid */
2370 #define RJT_XCHG_ERR       0x11 /* Exchange error */
2371 #define RJT_PROT_ERR       0x12 /* Protocol error */
2372 #define RJT_BAD_LENGTH     0x13 /* Invalid Length */
2373 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
2374 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
2375 #define RJT_TOO_MANY_SEQ   0x17 /* Excessive sequences */
2376 #define RJT_XCHG_NOT_STRT  0x18 /* Exchange not started */
2377 #define RJT_UNSUP_SEC_HDR  0x19 /* Security hdr not supported */
2378 #define RJT_UNAVAIL_PATH   0x1A /* Fabric Path not available */
2379 #define RJT_VENDOR_UNIQUE  0xFF /* Vendor unique error */
2380
2381 #define IOERR_SUCCESS                 0x00      /* statLocalError */
2382 #define IOERR_MISSING_CONTINUE        0x01
2383 #define IOERR_SEQUENCE_TIMEOUT        0x02
2384 #define IOERR_INTERNAL_ERROR          0x03
2385 #define IOERR_INVALID_RPI             0x04
2386 #define IOERR_NO_XRI                  0x05
2387 #define IOERR_ILLEGAL_COMMAND         0x06
2388 #define IOERR_XCHG_DROPPED            0x07
2389 #define IOERR_ILLEGAL_FIELD           0x08
2390 #define IOERR_BAD_CONTINUE            0x09
2391 #define IOERR_TOO_MANY_BUFFERS        0x0A
2392 #define IOERR_RCV_BUFFER_WAITING      0x0B
2393 #define IOERR_NO_CONNECTION           0x0C
2394 #define IOERR_TX_DMA_FAILED           0x0D
2395 #define IOERR_RX_DMA_FAILED           0x0E
2396 #define IOERR_ILLEGAL_FRAME           0x0F
2397 #define IOERR_EXTRA_DATA              0x10
2398 #define IOERR_NO_RESOURCES            0x11
2399 #define IOERR_RESERVED                0x12
2400 #define IOERR_ILLEGAL_LENGTH          0x13
2401 #define IOERR_UNSUPPORTED_FEATURE     0x14
2402 #define IOERR_ABORT_IN_PROGRESS       0x15
2403 #define IOERR_ABORT_REQUESTED         0x16
2404 #define IOERR_RECEIVE_BUFFER_TIMEOUT  0x17
2405 #define IOERR_LOOP_OPEN_FAILURE       0x18
2406 #define IOERR_RING_RESET              0x19
2407 #define IOERR_LINK_DOWN               0x1A
2408 #define IOERR_CORRUPTED_DATA          0x1B
2409 #define IOERR_CORRUPTED_RPI           0x1C
2410 #define IOERR_OUT_OF_ORDER_DATA       0x1D
2411 #define IOERR_OUT_OF_ORDER_ACK        0x1E
2412 #define IOERR_DUP_FRAME               0x1F
2413 #define IOERR_LINK_CONTROL_FRAME      0x20      /* ACK_N received */
2414 #define IOERR_BAD_HOST_ADDRESS        0x21
2415 #define IOERR_RCV_HDRBUF_WAITING      0x22
2416 #define IOERR_MISSING_HDR_BUFFER      0x23
2417 #define IOERR_MSEQ_CHAIN_CORRUPTED    0x24
2418 #define IOERR_ABORTMULT_REQUESTED     0x25
2419 #define IOERR_BUFFER_SHORTAGE         0x28
2420 #define IOERR_DEFAULT                 0x29
2421 #define IOERR_CNT                     0x2A
2422
2423 #define IOERR_DRVR_MASK               0x100
2424 #define IOERR_SLI_DOWN                0x101  /* ulpStatus  - Driver defined */
2425 #define IOERR_SLI_BRESET              0x102
2426 #define IOERR_SLI_ABORTED             0x103
2427 } PARM_ERR;
2428
2429 typedef union {
2430         struct {
2431 #ifdef __BIG_ENDIAN_BITFIELD
2432                 uint8_t Rctl;   /* R_CTL field */
2433                 uint8_t Type;   /* TYPE field */
2434                 uint8_t Dfctl;  /* DF_CTL field */
2435                 uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
2436 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2437                 uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
2438                 uint8_t Dfctl;  /* DF_CTL field */
2439                 uint8_t Type;   /* TYPE field */
2440                 uint8_t Rctl;   /* R_CTL field */
2441 #endif
2442
2443 #define BC      0x02            /* Broadcast Received  - Fctl */
2444 #define SI      0x04            /* Sequence Initiative */
2445 #define LA      0x08            /* Ignore Link Attention state */
2446 #define LS      0x80            /* Last Sequence */
2447         } hcsw;
2448         uint32_t reserved;
2449 } WORD5;
2450
2451 /* IOCB Command template for a generic response */
2452 typedef struct {
2453         uint32_t reserved[4];
2454         PARM_ERR perr;
2455 } GENERIC_RSP;
2456
2457 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
2458 typedef struct {
2459         struct ulp_bde xrsqbde[2];
2460         uint32_t xrsqRo;        /* Starting Relative Offset */
2461         WORD5 w5;               /* Header control/status word */
2462 } XR_SEQ_FIELDS;
2463
2464 /* IOCB Command template for ELS_REQUEST */
2465 typedef struct {
2466         struct ulp_bde elsReq;
2467         struct ulp_bde elsRsp;
2468
2469 #ifdef __BIG_ENDIAN_BITFIELD
2470         uint32_t word4Rsvd:7;
2471         uint32_t fl:1;
2472         uint32_t myID:24;
2473         uint32_t word5Rsvd:8;
2474         uint32_t remoteID:24;
2475 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2476         uint32_t myID:24;
2477         uint32_t fl:1;
2478         uint32_t word4Rsvd:7;
2479         uint32_t remoteID:24;
2480         uint32_t word5Rsvd:8;
2481 #endif
2482 } ELS_REQUEST;
2483
2484 /* IOCB Command template for RCV_ELS_REQ */
2485 typedef struct {
2486         struct ulp_bde elsReq[2];
2487         uint32_t parmRo;
2488
2489 #ifdef __BIG_ENDIAN_BITFIELD
2490         uint32_t word5Rsvd:8;
2491         uint32_t remoteID:24;
2492 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2493         uint32_t remoteID:24;
2494         uint32_t word5Rsvd:8;
2495 #endif
2496 } RCV_ELS_REQ;
2497
2498 /* IOCB Command template for ABORT / CLOSE_XRI */
2499 typedef struct {
2500         uint32_t rsvd[3];
2501         uint32_t abortType;
2502 #define ABORT_TYPE_ABTX  0x00000000
2503 #define ABORT_TYPE_ABTS  0x00000001
2504         uint32_t parm;
2505 #ifdef __BIG_ENDIAN_BITFIELD
2506         uint16_t abortContextTag; /* ulpContext from command to abort/close */
2507         uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
2508 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2509         uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
2510         uint16_t abortContextTag; /* ulpContext from command to abort/close */
2511 #endif
2512 } AC_XRI;
2513
2514 /* IOCB Command template for ABORT_MXRI64 */
2515 typedef struct {
2516         uint32_t rsvd[3];
2517         uint32_t abortType;
2518         uint32_t parm;
2519         uint32_t iotag32;
2520 } A_MXRI64;
2521
2522 /* IOCB Command template for GET_RPI */
2523 typedef struct {
2524         uint32_t rsvd[4];
2525         uint32_t parmRo;
2526 #ifdef __BIG_ENDIAN_BITFIELD
2527         uint32_t word5Rsvd:8;
2528         uint32_t remoteID:24;
2529 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2530         uint32_t remoteID:24;
2531         uint32_t word5Rsvd:8;
2532 #endif
2533 } GET_RPI;
2534
2535 /* IOCB Command template for all FCP Initiator commands */
2536 typedef struct {
2537         struct ulp_bde fcpi_cmnd;       /* FCP_CMND payload descriptor */
2538         struct ulp_bde fcpi_rsp;        /* Rcv buffer */
2539         uint32_t fcpi_parm;
2540         uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
2541 } FCPI_FIELDS;
2542
2543 /* IOCB Command template for all FCP Target commands */
2544 typedef struct {
2545         struct ulp_bde fcpt_Buffer[2];  /* FCP_CMND payload descriptor */
2546         uint32_t fcpt_Offset;
2547         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
2548 } FCPT_FIELDS;
2549
2550 /* SLI-2 IOCB structure definitions */
2551
2552 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
2553 typedef struct {
2554         ULP_BDL bdl;
2555         uint32_t xrsqRo;        /* Starting Relative Offset */
2556         WORD5 w5;               /* Header control/status word */
2557 } XMT_SEQ_FIELDS64;
2558
2559 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
2560 typedef struct {
2561         struct ulp_bde64 rcvBde;
2562         uint32_t rsvd1;
2563         uint32_t xrsqRo;        /* Starting Relative Offset */
2564         WORD5 w5;               /* Header control/status word */
2565 } RCV_SEQ_FIELDS64;
2566
2567 /* IOCB Command template for ELS_REQUEST64 */
2568 typedef struct {
2569         ULP_BDL bdl;
2570 #ifdef __BIG_ENDIAN_BITFIELD
2571         uint32_t word4Rsvd:7;
2572         uint32_t fl:1;
2573         uint32_t myID:24;
2574         uint32_t word5Rsvd:8;
2575         uint32_t remoteID:24;
2576 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2577         uint32_t myID:24;
2578         uint32_t fl:1;
2579         uint32_t word4Rsvd:7;
2580         uint32_t remoteID:24;
2581         uint32_t word5Rsvd:8;
2582 #endif
2583 } ELS_REQUEST64;
2584
2585 /* IOCB Command template for GEN_REQUEST64 */
2586 typedef struct {
2587         ULP_BDL bdl;
2588         uint32_t xrsqRo;        /* Starting Relative Offset */
2589         WORD5 w5;               /* Header control/status word */
2590 } GEN_REQUEST64;
2591
2592 /* IOCB Command template for RCV_ELS_REQ64 */
2593 typedef struct {
2594         struct ulp_bde64 elsReq;
2595         uint32_t rcvd1;
2596         uint32_t parmRo;
2597
2598 #ifdef __BIG_ENDIAN_BITFIELD
2599         uint32_t word5Rsvd:8;
2600         uint32_t remoteID:24;
2601 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2602         uint32_t remoteID:24;
2603         uint32_t word5Rsvd:8;
2604 #endif
2605 } RCV_ELS_REQ64;
2606
2607 /* IOCB Command template for all 64 bit FCP Initiator commands */
2608 typedef struct {
2609         ULP_BDL bdl;
2610         uint32_t fcpi_parm;
2611         uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
2612 } FCPI_FIELDS64;
2613
2614 /* IOCB Command template for all 64 bit FCP Target commands */
2615 typedef struct {
2616         ULP_BDL bdl;
2617         uint32_t fcpt_Offset;
2618         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
2619 } FCPT_FIELDS64;
2620
2621 typedef struct _IOCB {  /* IOCB structure */
2622         union {
2623                 GENERIC_RSP grsp;       /* Generic response */
2624                 XR_SEQ_FIELDS xrseq;    /* XMIT / BCAST / RCV_SEQUENCE cmd */
2625                 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
2626                 RCV_ELS_REQ rcvels;     /* RCV_ELS_REQ template */
2627                 AC_XRI acxri;   /* ABORT / CLOSE_XRI template */
2628                 A_MXRI64 amxri; /* abort multiple xri command overlay */
2629                 GET_RPI getrpi; /* GET_RPI template */
2630                 FCPI_FIELDS fcpi;       /* FCP Initiator template */
2631                 FCPT_FIELDS fcpt;       /* FCP target template */
2632
2633                 /* SLI-2 structures */
2634
2635                 struct ulp_bde64 cont64[2];     /* up to 2 64 bit continuation
2636                                            bde_64s */
2637                 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
2638                 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
2639                 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
2640                 XMT_SEQ_FIELDS64 xseq64;        /* XMIT / BCAST cmd */
2641                 FCPI_FIELDS64 fcpi64;   /* FCP 64 bit Initiator template */
2642                 FCPT_FIELDS64 fcpt64;   /* FCP 64 bit target template */
2643
2644                 uint32_t ulpWord[IOCB_WORD_SZ - 2];     /* generic 6 'words' */
2645         } un;
2646         union {
2647                 struct {
2648 #ifdef __BIG_ENDIAN_BITFIELD
2649                         uint16_t ulpContext;    /* High order bits word 6 */
2650                         uint16_t ulpIoTag;      /* Low  order bits word 6 */
2651 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2652                         uint16_t ulpIoTag;      /* Low  order bits word 6 */
2653                         uint16_t ulpContext;    /* High order bits word 6 */
2654 #endif
2655                 } t1;
2656                 struct {
2657 #ifdef __BIG_ENDIAN_BITFIELD
2658                         uint16_t ulpContext;    /* High order bits word 6 */
2659                         uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
2660                         uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
2661 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2662                         uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
2663                         uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
2664                         uint16_t ulpContext;    /* High order bits word 6 */
2665 #endif
2666                 } t2;
2667         } un1;
2668 #define ulpContext un1.t1.ulpContext
2669 #define ulpIoTag   un1.t1.ulpIoTag
2670 #define ulpIoTag0  un1.t2.ulpIoTag0
2671
2672 #ifdef __BIG_ENDIAN_BITFIELD
2673         uint32_t ulpTimeout:8;
2674         uint32_t ulpXS:1;
2675         uint32_t ulpFCP2Rcvy:1;
2676         uint32_t ulpPU:2;
2677         uint32_t ulpIr:1;
2678         uint32_t ulpClass:3;
2679         uint32_t ulpCommand:8;
2680         uint32_t ulpStatus:4;
2681         uint32_t ulpBdeCount:2;
2682         uint32_t ulpLe:1;
2683         uint32_t ulpOwner:1;    /* Low order bit word 7 */
2684 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2685         uint32_t ulpOwner:1;    /* Low order bit word 7 */
2686         uint32_t ulpLe:1;
2687         uint32_t ulpBdeCount:2;
2688         uint32_t ulpStatus:4;
2689         uint32_t ulpCommand:8;
2690         uint32_t ulpClass:3;
2691         uint32_t ulpIr:1;
2692         uint32_t ulpPU:2;
2693         uint32_t ulpFCP2Rcvy:1;
2694         uint32_t ulpXS:1;
2695         uint32_t ulpTimeout:8;
2696 #endif
2697
2698 #define PARM_UNUSED        0    /* PU field (Word 4) not used */
2699 #define PARM_REL_OFF       1    /* PU field (Word 4) = R. O. */
2700 #define PARM_READ_CHECK    2    /* PU field (Word 4) = Data Transfer Length */
2701 #define CLASS1             0    /* Class 1 */
2702 #define CLASS2             1    /* Class 2 */
2703 #define CLASS3             2    /* Class 3 */
2704 #define CLASS_FCP_INTERMIX 7    /* FCP Data->Cls 1, all else->Cls 2 */
2705
2706 #define IOSTAT_SUCCESS         0x0      /* ulpStatus  - HBA defined */
2707 #define IOSTAT_FCP_RSP_ERROR   0x1
2708 #define IOSTAT_REMOTE_STOP     0x2
2709 #define IOSTAT_LOCAL_REJECT    0x3
2710 #define IOSTAT_NPORT_RJT       0x4
2711 #define IOSTAT_FABRIC_RJT      0x5
2712 #define IOSTAT_NPORT_BSY       0x6
2713 #define IOSTAT_FABRIC_BSY      0x7
2714 #define IOSTAT_INTERMED_RSP    0x8
2715 #define IOSTAT_LS_RJT          0x9
2716 #define IOSTAT_BA_RJT          0xA
2717 #define IOSTAT_RSVD1           0xB
2718 #define IOSTAT_RSVD2           0xC
2719 #define IOSTAT_RSVD3           0xD
2720 #define IOSTAT_RSVD4           0xE
2721 #define IOSTAT_RSVD5           0xF
2722 #define IOSTAT_DRIVER_REJECT   0x10   /* ulpStatus  - Driver defined */
2723 #define IOSTAT_DEFAULT         0xF    /* Same as rsvd5 for now */
2724 #define IOSTAT_CNT             0x11
2725
2726 } IOCB_t;
2727
2728
2729 #define SLI1_SLIM_SIZE   (4 * 1024)
2730
2731 /* Up to 498 IOCBs will fit into 16k
2732  * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
2733  */
2734 #define SLI2_SLIM_SIZE   (16 * 1024)
2735
2736 /* Maximum IOCBs that will fit in SLI2 slim */
2737 #define MAX_SLI2_IOCB    498
2738
2739 struct lpfc_sli2_slim {
2740         MAILBOX_t mbx;
2741         PCB_t pcb;
2742         IOCB_t IOCBs[MAX_SLI2_IOCB];
2743 };
2744
2745 /*******************************************************************
2746 This macro check PCI device to allow special handling for LC HBAs.
2747
2748 Parameters:
2749 device : struct pci_dev 's device field
2750
2751 return 1 => TRUE
2752        0 => FALSE
2753  *******************************************************************/
2754 static inline int
2755 lpfc_is_LC_HBA(unsigned short device)
2756 {
2757         if ((device == PCI_DEVICE_ID_TFLY) ||
2758             (device == PCI_DEVICE_ID_PFLY) ||
2759             (device == PCI_DEVICE_ID_LP101) ||
2760             (device == PCI_DEVICE_ID_BMID) ||
2761             (device == PCI_DEVICE_ID_BSMB) ||
2762             (device == PCI_DEVICE_ID_ZMID) ||
2763             (device == PCI_DEVICE_ID_ZSMB) ||
2764             (device == PCI_DEVICE_ID_RFLY))
2765                 return 1;
2766         else
2767                 return 0;
2768 }