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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / net / tulip / uli526x.c
blobca2548eb7d63196f1edd1bd02ee5830d6c007c53
1 /*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
12
13 */
14
15 #define DRV_NAME "uli526x"
16 #define DRV_VERSION "0.9.3"
17 #define DRV_RELDATE "2005-7-29"
18
19 #include <linux/module.h>
20
21 #include <linux/kernel.h>
22 #include <linux/string.h>
23 #include <linux/timer.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/skbuff.h>
34 #include <linux/delay.h>
35 #include <linux/spinlock.h>
36 #include <linux/dma-mapping.h>
37
38 #include <asm/processor.h>
39 #include <asm/bitops.h>
40 #include <asm/io.h>
41 #include <asm/dma.h>
42 #include <asm/uaccess.h>
43
44
45 /* Board/System/Debug information/definition ---------------- */
46 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
47 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
48
49 #define ULI526X_IO_SIZE 0x100
50 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
51 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
52 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
53 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
54 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
55 #define TX_BUF_ALLOC 0x600
56 #define RX_ALLOC_SIZE 0x620
57 #define ULI526X_RESET 1
58 #define CR0_DEFAULT 0
59 #define CR6_DEFAULT 0x22200000
60 #define CR7_DEFAULT 0x180c1
61 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
62 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
63 #define MAX_PACKET_SIZE 1514
64 #define ULI5261_MAX_MULTICAST 14
65 #define RX_COPY_SIZE 100
66 #define MAX_CHECK_PACKET 0x8000
67
68 #define ULI526X_10MHF 0
69 #define ULI526X_100MHF 1
70 #define ULI526X_10MFD 4
71 #define ULI526X_100MFD 5
72 #define ULI526X_AUTO 8
73
74 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
75 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
76 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
77 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
78 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
79 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
80
81 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
82 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
83 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
84
85 #define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
86
87 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
88
89
90 /* CR9 definition: SROM/MII */
91 #define CR9_SROM_READ 0x4800
92 #define CR9_SRCS 0x1
93 #define CR9_SRCLK 0x2
94 #define CR9_CRDOUT 0x8
95 #define SROM_DATA_0 0x0
96 #define SROM_DATA_1 0x4
97 #define PHY_DATA_1 0x20000
98 #define PHY_DATA_0 0x00000
99 #define MDCLKH 0x10000
100
101 #define PHY_POWER_DOWN 0x800
102
103 #define SROM_V41_CODE 0x14
104
105 #define SROM_CLK_WRITE(data, ioaddr) \
106 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
107 udelay(5); \
108 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
109 udelay(5); \
110 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
111 udelay(5);
112
113 /* Structure/enum declaration ------------------------------- */
114 struct tx_desc {
115 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
116 char *tx_buf_ptr; /* Data for us */
117 struct tx_desc *next_tx_desc;
118 } __attribute__(( aligned(32) ));
119
120 struct rx_desc {
121 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
122 struct sk_buff *rx_skb_ptr; /* Data for us */
123 struct rx_desc *next_rx_desc;
124 } __attribute__(( aligned(32) ));
125
126 struct uli526x_board_info {
127 u32 chip_id; /* Chip vendor/Device ID */
128 struct net_device *next_dev; /* next device */
129 struct pci_dev *pdev; /* PCI device */
130 spinlock_t lock;
131
132 long ioaddr; /* I/O base address */
133 u32 cr0_data;
134 u32 cr5_data;
135 u32 cr6_data;
136 u32 cr7_data;
137 u32 cr15_data;
138
139 /* pointer for memory physical address */
140 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
141 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
142 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
143 dma_addr_t first_tx_desc_dma;
144 dma_addr_t first_rx_desc_dma;
145
146 /* descriptor pointer */
147 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
148 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
149 unsigned char *desc_pool_ptr; /* descriptor pool memory */
150 struct tx_desc *first_tx_desc;
151 struct tx_desc *tx_insert_ptr;
152 struct tx_desc *tx_remove_ptr;
153 struct rx_desc *first_rx_desc;
154 struct rx_desc *rx_insert_ptr;
155 struct rx_desc *rx_ready_ptr; /* packet come pointer */
156 unsigned long tx_packet_cnt; /* transmitted packet count */
157 unsigned long rx_avail_cnt; /* available rx descriptor count */
158 unsigned long interval_rx_cnt; /* rx packet count a callback time */
159
160 u16 dbug_cnt;
161 u16 NIC_capability; /* NIC media capability */
162 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
163
164 u8 media_mode; /* user specify media mode */
165 u8 op_mode; /* real work media mode */
166 u8 phy_addr;
167 u8 link_failed; /* Ever link failed */
168 u8 wait_reset; /* Hardware failed, need to reset */
169 struct timer_list timer;
170
171 /* System defined statistic counter */
172 struct net_device_stats stats;
173
174 /* Driver defined statistic counter */
175 unsigned long tx_fifo_underrun;
176 unsigned long tx_loss_carrier;
177 unsigned long tx_no_carrier;
178 unsigned long tx_late_collision;
179 unsigned long tx_excessive_collision;
180 unsigned long tx_jabber_timeout;
181 unsigned long reset_count;
182 unsigned long reset_cr8;
183 unsigned long reset_fatal;
184 unsigned long reset_TXtimeout;
185
186 /* NIC SROM data */
187 unsigned char srom[128];
188 u8 init;
189 };
190
191 enum uli526x_offsets {
192 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
193 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
194 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
195 DCR15 = 0x78
196 };
197
198 enum uli526x_CR6_bits {
199 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
200 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
201 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
202 };
203
204 /* Global variable declaration ----------------------------- */
205 static int __devinitdata printed_version;
206 static char version[] __devinitdata =
207 KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
208 DRV_VERSION " (" DRV_RELDATE ")\n";
209
210 static int uli526x_debug;
211 static unsigned char uli526x_media_mode = ULI526X_AUTO;
212 static u32 uli526x_cr6_user_set;
213
214 /* For module input parameter */
215 static int debug;
216 static u32 cr6set;
217 static int mode = 8;
218
219 /* function declaration ------------------------------------- */
220 static int uli526x_open(struct net_device *);
221 static int uli526x_start_xmit(struct sk_buff *, struct net_device *);
222 static int uli526x_stop(struct net_device *);
223 static struct net_device_stats * uli526x_get_stats(struct net_device *);
224 static void uli526x_set_filter_mode(struct net_device *);
225 static const struct ethtool_ops netdev_ethtool_ops;
226 static u16 read_srom_word(long, int);
227 static irqreturn_t uli526x_interrupt(int, void *);
228 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
229 static void allocate_rx_buffer(struct uli526x_board_info *);
230 static void update_cr6(u32, unsigned long);
231 static void send_filter_frame(struct net_device *, int);
232 static u16 phy_read(unsigned long, u8, u8, u32);
233 static u16 phy_readby_cr10(unsigned long, u8, u8);
234 static void phy_write(unsigned long, u8, u8, u16, u32);
235 static void phy_writeby_cr10(unsigned long, u8, u8, u16);
236 static void phy_write_1bit(unsigned long, u32, u32);
237 static u16 phy_read_1bit(unsigned long, u32);
238 static u8 uli526x_sense_speed(struct uli526x_board_info *);
239 static void uli526x_process_mode(struct uli526x_board_info *);
240 static void uli526x_timer(unsigned long);
241 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
242 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
243 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
244 static void uli526x_dynamic_reset(struct net_device *);
245 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
246 static void uli526x_init(struct net_device *);
247 static void uli526x_set_phyxcer(struct uli526x_board_info *);
248
249 /* ULI526X network board routine ---------------------------- */
250
251 /*
252 * Search ULI526X board, allocate space and register it
253 */
254
255 static int __devinit uli526x_init_one (struct pci_dev *pdev,
256 const struct pci_device_id *ent)
257 {
258 struct uli526x_board_info *db; /* board information structure */
259 struct net_device *dev;
260 int i, err;
261
262 ULI526X_DBUG(0, "uli526x_init_one()", 0);
263
264 if (!printed_version++)
265 printk(version);
266
267 /* Init network device */
268 dev = alloc_etherdev(sizeof(*db));
269 if (dev == NULL)
270 return -ENOMEM;
271 SET_MODULE_OWNER(dev);
272 SET_NETDEV_DEV(dev, &pdev->dev);
273
274 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
275 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
276 err = -ENODEV;
277 goto err_out_free;
278 }
279
280 /* Enable Master/IO access, Disable memory access */
281 err = pci_enable_device(pdev);
282 if (err)
283 goto err_out_free;
284
285 if (!pci_resource_start(pdev, 0)) {
286 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
287 err = -ENODEV;
288 goto err_out_disable;
289 }
290
291 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
292 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
293 err = -ENODEV;
294 goto err_out_disable;
295 }
296
297 if (pci_request_regions(pdev, DRV_NAME)) {
298 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
299 err = -ENODEV;
300 goto err_out_disable;
301 }
302
303 /* Init system & device */
304 db = netdev_priv(dev);
305
306 /* Allocate Tx/Rx descriptor memory */
307 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
308 if(db->desc_pool_ptr == NULL)
309 {
310 err = -ENOMEM;
311 goto err_out_nomem;
312 }
313 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
314 if(db->buf_pool_ptr == NULL)
315 {
316 err = -ENOMEM;
317 goto err_out_nomem;
318 }
319
320 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
321 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
322 db->buf_pool_start = db->buf_pool_ptr;
323 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
324
325 db->chip_id = ent->driver_data;
326 db->ioaddr = pci_resource_start(pdev, 0);
327
328 db->pdev = pdev;
329 db->init = 1;
330
331 dev->base_addr = db->ioaddr;
332 dev->irq = pdev->irq;
333 pci_set_drvdata(pdev, dev);
334
335 /* Register some necessary functions */
336 dev->open = &uli526x_open;
337 dev->hard_start_xmit = &uli526x_start_xmit;
338 dev->stop = &uli526x_stop;
339 dev->get_stats = &uli526x_get_stats;
340 dev->set_multicast_list = &uli526x_set_filter_mode;
341 dev->ethtool_ops = &netdev_ethtool_ops;
342 spin_lock_init(&db->lock);
343
344
345 /* read 64 word srom data */
346 for (i = 0; i < 64; i++)
347 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
348
349 /* Set Node address */
350 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
351 {
352 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
353 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
354 outl(0, db->ioaddr + DCR14); //Clear reset port
355 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
356 outl(0, db->ioaddr + DCR14); //Clear reset port
357 outl(0, db->ioaddr + DCR13); //Clear CR13
358 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
359 //Read MAC address from CR14
360 for (i = 0; i < 6; i++)
361 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
362 //Read end
363 outl(0, db->ioaddr + DCR13); //Clear CR13
364 outl(0, db->ioaddr + DCR0); //Clear CR0
365 udelay(10);
366 }
367 else /*Exist SROM*/
368 {
369 for (i = 0; i < 6; i++)
370 dev->dev_addr[i] = db->srom[20 + i];
371 }
372 err = register_netdev (dev);
373 if (err)
374 goto err_out_res;
375
376 printk(KERN_INFO "%s: ULi M%04lx at pci%s,",dev->name,ent->driver_data >> 16,pci_name(pdev));
377
378 for (i = 0; i < 6; i++)
379 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
380 printk(", irq %d.\n", dev->irq);
381
382 pci_set_master(pdev);
383
384 return 0;
385
386 err_out_res:
387 pci_release_regions(pdev);
388 err_out_nomem:
389 if(db->desc_pool_ptr)
390 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
391 db->desc_pool_ptr, db->desc_pool_dma_ptr);
392
393 if(db->buf_pool_ptr != NULL)
394 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
395 db->buf_pool_ptr, db->buf_pool_dma_ptr);
396 err_out_disable:
397 pci_disable_device(pdev);
398 err_out_free:
399 pci_set_drvdata(pdev, NULL);
400 free_netdev(dev);
401
402 return err;
403 }
404
405
406 static void __devexit uli526x_remove_one (struct pci_dev *pdev)
407 {
408 struct net_device *dev = pci_get_drvdata(pdev);
409 struct uli526x_board_info *db = netdev_priv(dev);
410
411 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
412
413 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
414 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
415 db->desc_pool_dma_ptr);
416 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
417 db->buf_pool_ptr, db->buf_pool_dma_ptr);
418 unregister_netdev(dev);
419 pci_release_regions(pdev);
420 free_netdev(dev); /* free board information */
421 pci_set_drvdata(pdev, NULL);
422 pci_disable_device(pdev);
423 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
424 }
425
426
427 /*
428 * Open the interface.
429 * The interface is opened whenever "ifconfig" activates it.
430 */
431
432 static int uli526x_open(struct net_device *dev)
433 {
434 int ret;
435 struct uli526x_board_info *db = netdev_priv(dev);
436
437 ULI526X_DBUG(0, "uli526x_open", 0);
438
439 ret = request_irq(dev->irq, &uli526x_interrupt, IRQF_SHARED, dev->name, dev);
440 if (ret)
441 return ret;
442
443 /* system variable init */
444 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
445 db->tx_packet_cnt = 0;
446 db->rx_avail_cnt = 0;
447 db->link_failed = 1;
448 netif_carrier_off(dev);
449 db->wait_reset = 0;
450
451 db->NIC_capability = 0xf; /* All capability*/
452 db->PHY_reg4 = 0x1e0;
453
454 /* CR6 operation mode decision */
455 db->cr6_data |= ULI526X_TXTH_256;
456 db->cr0_data = CR0_DEFAULT;
457
458 /* Initialize ULI526X board */
459 uli526x_init(dev);
460
461 /* Active System Interface */
462 netif_wake_queue(dev);
463
464 /* set and active a timer process */
465 init_timer(&db->timer);
466 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
467 db->timer.data = (unsigned long)dev;
468 db->timer.function = &uli526x_timer;
469 add_timer(&db->timer);
470
471 return 0;
472 }
473
474
475 /* Initialize ULI526X board
476 * Reset ULI526X board
477 * Initialize TX/Rx descriptor chain structure
478 * Send the set-up frame
479 * Enable Tx/Rx machine
480 */
481
482 static void uli526x_init(struct net_device *dev)
483 {
484 struct uli526x_board_info *db = netdev_priv(dev);
485 unsigned long ioaddr = db->ioaddr;
486 u8 phy_tmp;
487 u16 phy_value;
488 u16 phy_reg_reset;
489
490 ULI526X_DBUG(0, "uli526x_init()", 0);
491
492 /* Reset M526x MAC controller */
493 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
494 udelay(100);
495 outl(db->cr0_data, ioaddr + DCR0);
496 udelay(5);
497
498 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
499 db->phy_addr = 1;
500 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
501 {
502 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
503 if(phy_value != 0xffff&&phy_value!=0)
504 {
505 db->phy_addr = phy_tmp;
506 break;
507 }
508 }
509 if(phy_tmp == 32)
510 printk(KERN_WARNING "Can not find the phy address!!!");
511 /* Parser SROM and media mode */
512 db->media_mode = uli526x_media_mode;
513
514 /* Phyxcer capability setting */
515 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
516 phy_reg_reset = (phy_reg_reset | 0x8000);
517 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
518 udelay(500);
519
520 /* Process Phyxcer Media Mode */
521 uli526x_set_phyxcer(db);
522
523 /* Media Mode Process */
524 if ( !(db->media_mode & ULI526X_AUTO) )
525 db->op_mode = db->media_mode; /* Force Mode */
526
527 /* Initialize Transmit/Receive decriptor and CR3/4 */
528 uli526x_descriptor_init(db, ioaddr);
529
530 /* Init CR6 to program M526X operation */
531 update_cr6(db->cr6_data, ioaddr);
532
533 /* Send setup frame */
534 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
535
536 /* Init CR7, interrupt active bit */
537 db->cr7_data = CR7_DEFAULT;
538 outl(db->cr7_data, ioaddr + DCR7);
539
540 /* Init CR15, Tx jabber and Rx watchdog timer */
541 outl(db->cr15_data, ioaddr + DCR15);
542
543 /* Enable ULI526X Tx/Rx function */
544 db->cr6_data |= CR6_RXSC | CR6_TXSC;
545 update_cr6(db->cr6_data, ioaddr);
546 }
547
548
549 /*
550 * Hardware start transmission.
551 * Send a packet to media from the upper layer.
552 */
553
554 static int uli526x_start_xmit(struct sk_buff *skb, struct net_device *dev)
555 {
556 struct uli526x_board_info *db = netdev_priv(dev);
557 struct tx_desc *txptr;
558 unsigned long flags;
559
560 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
561
562 /* Resource flag check */
563 netif_stop_queue(dev);
564
565 /* Too large packet check */
566 if (skb->len > MAX_PACKET_SIZE) {
567 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
568 dev_kfree_skb(skb);
569 return 0;
570 }
571
572 spin_lock_irqsave(&db->lock, flags);
573
574 /* No Tx resource check, it never happen nromally */
575 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
576 spin_unlock_irqrestore(&db->lock, flags);
577 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt);
578 return 1;
579 }
580
581 /* Disable NIC interrupt */
582 outl(0, dev->base_addr + DCR7);
583
584 /* transmit this packet */
585 txptr = db->tx_insert_ptr;
586 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
587 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
588
589 /* Point to next transmit free descriptor */
590 db->tx_insert_ptr = txptr->next_tx_desc;
591
592 /* Transmit Packet Process */
593 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
594 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
595 db->tx_packet_cnt++; /* Ready to send */
596 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
597 dev->trans_start = jiffies; /* saved time stamp */
598 }
599
600 /* Tx resource check */
601 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
602 netif_wake_queue(dev);
603
604 /* Restore CR7 to enable interrupt */
605 spin_unlock_irqrestore(&db->lock, flags);
606 outl(db->cr7_data, dev->base_addr + DCR7);
607
608 /* free this SKB */
609 dev_kfree_skb(skb);
610
611 return 0;
612 }
613
614
615 /*
616 * Stop the interface.
617 * The interface is stopped when it is brought.
618 */
619
620 static int uli526x_stop(struct net_device *dev)
621 {
622 struct uli526x_board_info *db = netdev_priv(dev);
623 unsigned long ioaddr = dev->base_addr;
624
625 ULI526X_DBUG(0, "uli526x_stop", 0);
626
627 /* disable system */
628 netif_stop_queue(dev);
629
630 /* deleted timer */
631 del_timer_sync(&db->timer);
632
633 /* Reset & stop ULI526X board */
634 outl(ULI526X_RESET, ioaddr + DCR0);
635 udelay(5);
636 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
637
638 /* free interrupt */
639 free_irq(dev->irq, dev);
640
641 /* free allocated rx buffer */
642 uli526x_free_rxbuffer(db);
643
644 #if 0
645 /* show statistic counter */
646 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
647 db->tx_fifo_underrun, db->tx_excessive_collision,
648 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
649 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
650 db->reset_fatal, db->reset_TXtimeout);
651 #endif
652
653 return 0;
654 }
655
656
657 /*
658 * M5261/M5263 insterrupt handler
659 * receive the packet to upper layer, free the transmitted packet
660 */
661
662 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
663 {
664 struct net_device *dev = dev_id;
665 struct uli526x_board_info *db = netdev_priv(dev);
666 unsigned long ioaddr = dev->base_addr;
667 unsigned long flags;
668
669 if (!dev) {
670 ULI526X_DBUG(1, "uli526x_interrupt() without DEVICE arg", 0);
671 return IRQ_NONE;
672 }
673
674 spin_lock_irqsave(&db->lock, flags);
675 outl(0, ioaddr + DCR7);
676
677 /* Got ULI526X status */
678 db->cr5_data = inl(ioaddr + DCR5);
679 outl(db->cr5_data, ioaddr + DCR5);
680 if ( !(db->cr5_data & 0x180c1) ) {
681 spin_unlock_irqrestore(&db->lock, flags);
682 outl(db->cr7_data, ioaddr + DCR7);
683 return IRQ_HANDLED;
684 }
685
686 /* Check system status */
687 if (db->cr5_data & 0x2000) {
688 /* system bus error happen */
689 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
690 db->reset_fatal++;
691 db->wait_reset = 1; /* Need to RESET */
692 spin_unlock_irqrestore(&db->lock, flags);
693 return IRQ_HANDLED;
694 }
695
696 /* Received the coming packet */
697 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
698 uli526x_rx_packet(dev, db);
699
700 /* reallocate rx descriptor buffer */
701 if (db->rx_avail_cnt<RX_DESC_CNT)
702 allocate_rx_buffer(db);
703
704 /* Free the transmitted descriptor */
705 if ( db->cr5_data & 0x01)
706 uli526x_free_tx_pkt(dev, db);
707
708 /* Restore CR7 to enable interrupt mask */
709 outl(db->cr7_data, ioaddr + DCR7);
710
711 spin_unlock_irqrestore(&db->lock, flags);
712 return IRQ_HANDLED;
713 }
714
715
716 /*
717 * Free TX resource after TX complete
718 */
719
720 static void uli526x_free_tx_pkt(struct net_device *dev, struct uli526x_board_info * db)
721 {
722 struct tx_desc *txptr;
723 u32 tdes0;
724
725 txptr = db->tx_remove_ptr;
726 while(db->tx_packet_cnt) {
727 tdes0 = le32_to_cpu(txptr->tdes0);
728 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
729 if (tdes0 & 0x80000000)
730 break;
731
732 /* A packet sent completed */
733 db->tx_packet_cnt--;
734 db->stats.tx_packets++;
735
736 /* Transmit statistic counter */
737 if ( tdes0 != 0x7fffffff ) {
738 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
739 db->stats.collisions += (tdes0 >> 3) & 0xf;
740 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
741 if (tdes0 & TDES0_ERR_MASK) {
742 db->stats.tx_errors++;
743 if (tdes0 & 0x0002) { /* UnderRun */
744 db->tx_fifo_underrun++;
745 if ( !(db->cr6_data & CR6_SFT) ) {
746 db->cr6_data = db->cr6_data | CR6_SFT;
747 update_cr6(db->cr6_data, db->ioaddr);
748 }
749 }
750 if (tdes0 & 0x0100)
751 db->tx_excessive_collision++;
752 if (tdes0 & 0x0200)
753 db->tx_late_collision++;
754 if (tdes0 & 0x0400)
755 db->tx_no_carrier++;
756 if (tdes0 & 0x0800)
757 db->tx_loss_carrier++;
758 if (tdes0 & 0x4000)
759 db->tx_jabber_timeout++;
760 }
761 }
762
763 txptr = txptr->next_tx_desc;
764 }/* End of while */
765
766 /* Update TX remove pointer to next */
767 db->tx_remove_ptr = txptr;
768
769 /* Resource available check */
770 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
771 netif_wake_queue(dev); /* Active upper layer, send again */
772 }
773
774
775 /*
776 * Receive the come packet and pass to upper layer
777 */
778
779 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
780 {
781 struct rx_desc *rxptr;
782 struct sk_buff *skb;
783 int rxlen;
784 u32 rdes0;
785
786 rxptr = db->rx_ready_ptr;
787
788 while(db->rx_avail_cnt) {
789 rdes0 = le32_to_cpu(rxptr->rdes0);
790 if (rdes0 & 0x80000000) /* packet owner check */
791 {
792 break;
793 }
794
795 db->rx_avail_cnt--;
796 db->interval_rx_cnt++;
797
798 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
799 if ( (rdes0 & 0x300) != 0x300) {
800 /* A packet without First/Last flag */
801 /* reuse this SKB */
802 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
803 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
804 } else {
805 /* A packet with First/Last flag */
806 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
807
808 /* error summary bit check */
809 if (rdes0 & 0x8000) {
810 /* This is a error packet */
811 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
812 db->stats.rx_errors++;
813 if (rdes0 & 1)
814 db->stats.rx_fifo_errors++;
815 if (rdes0 & 2)
816 db->stats.rx_crc_errors++;
817 if (rdes0 & 0x80)
818 db->stats.rx_length_errors++;
819 }
820
821 if ( !(rdes0 & 0x8000) ||
822 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
823 skb = rxptr->rx_skb_ptr;
824
825 /* Good packet, send to upper layer */
826 /* Shorst packet used new SKB */
827 if ( (rxlen < RX_COPY_SIZE) &&
828 ( (skb = dev_alloc_skb(rxlen + 2) )
829 != NULL) ) {
830 /* size less than COPY_SIZE, allocate a rxlen SKB */
831 skb_reserve(skb, 2); /* 16byte align */
832 memcpy(skb_put(skb, rxlen),
833 skb_tail_pointer(rxptr->rx_skb_ptr),
834 rxlen);
835 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
836 } else
837 skb_put(skb, rxlen);
838
839 skb->protocol = eth_type_trans(skb, dev);
840 netif_rx(skb);
841 dev->last_rx = jiffies;
842 db->stats.rx_packets++;
843 db->stats.rx_bytes += rxlen;
844
845 } else {
846 /* Reuse SKB buffer when the packet is error */
847 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
848 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
849 }
850 }
851
852 rxptr = rxptr->next_rx_desc;
853 }
854
855 db->rx_ready_ptr = rxptr;
856 }
857
858
859 /*
860 * Get statistics from driver.
861 */
862
863 static struct net_device_stats * uli526x_get_stats(struct net_device *dev)
864 {
865 struct uli526x_board_info *db = netdev_priv(dev);
866
867 ULI526X_DBUG(0, "uli526x_get_stats", 0);
868 return &db->stats;
869 }
870
871
872 /*
873 * Set ULI526X multicast address
874 */
875
876 static void uli526x_set_filter_mode(struct net_device * dev)
877 {
878 struct uli526x_board_info *db = dev->priv;
879 unsigned long flags;
880
881 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
882 spin_lock_irqsave(&db->lock, flags);
883
884 if (dev->flags & IFF_PROMISC) {
885 ULI526X_DBUG(0, "Enable PROM Mode", 0);
886 db->cr6_data |= CR6_PM | CR6_PBF;
887 update_cr6(db->cr6_data, db->ioaddr);
888 spin_unlock_irqrestore(&db->lock, flags);
889 return;
890 }
891
892 if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) {
893 ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count);
894 db->cr6_data &= ~(CR6_PM | CR6_PBF);
895 db->cr6_data |= CR6_PAM;
896 spin_unlock_irqrestore(&db->lock, flags);
897 return;
898 }
899
900 ULI526X_DBUG(0, "Set multicast address", dev->mc_count);
901 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
902 spin_unlock_irqrestore(&db->lock, flags);
903 }
904
905 static void
906 ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
907 {
908 ecmd->supported = (SUPPORTED_10baseT_Half |
909 SUPPORTED_10baseT_Full |
910 SUPPORTED_100baseT_Half |
911 SUPPORTED_100baseT_Full |
912 SUPPORTED_Autoneg |
913 SUPPORTED_MII);
914
915 ecmd->advertising = (ADVERTISED_10baseT_Half |
916 ADVERTISED_10baseT_Full |
917 ADVERTISED_100baseT_Half |
918 ADVERTISED_100baseT_Full |
919 ADVERTISED_Autoneg |
920 ADVERTISED_MII);
921
922
923 ecmd->port = PORT_MII;
924 ecmd->phy_address = db->phy_addr;
925
926 ecmd->transceiver = XCVR_EXTERNAL;
927
928 ecmd->speed = 10;
929 ecmd->duplex = DUPLEX_HALF;
930
931 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
932 {
933 ecmd->speed = 100;
934 }
935 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
936 {
937 ecmd->duplex = DUPLEX_FULL;
938 }
939 if(db->link_failed)
940 {
941 ecmd->speed = -1;
942 ecmd->duplex = -1;
943 }
944
945 if (db->media_mode & ULI526X_AUTO)
946 {
947 ecmd->autoneg = AUTONEG_ENABLE;
948 }
949 }
950
951 static void netdev_get_drvinfo(struct net_device *dev,
952 struct ethtool_drvinfo *info)
953 {
954 struct uli526x_board_info *np = netdev_priv(dev);
955
956 strcpy(info->driver, DRV_NAME);
957 strcpy(info->version, DRV_VERSION);
958 if (np->pdev)
959 strcpy(info->bus_info, pci_name(np->pdev));
960 else
961 sprintf(info->bus_info, "EISA 0x%lx %d",
962 dev->base_addr, dev->irq);
963 }
964
965 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
966 struct uli526x_board_info *np = netdev_priv(dev);
967
968 ULi_ethtool_gset(np, cmd);
969
970 return 0;
971 }
972
973 static u32 netdev_get_link(struct net_device *dev) {
974 struct uli526x_board_info *np = netdev_priv(dev);
975
976 if(np->link_failed)
977 return 0;
978 else
979 return 1;
980 }
981
982 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
983 {
984 wol->supported = WAKE_PHY | WAKE_MAGIC;
985 wol->wolopts = 0;
986 }
987
988 static const struct ethtool_ops netdev_ethtool_ops = {
989 .get_drvinfo = netdev_get_drvinfo,
990 .get_settings = netdev_get_settings,
991 .get_link = netdev_get_link,
992 .get_wol = uli526x_get_wol,
993 };
994
995 /*
996 * A periodic timer routine
997 * Dynamic media sense, allocate Rx buffer...
998 */
999
1000 static void uli526x_timer(unsigned long data)
1001 {
1002 u32 tmp_cr8;
1003 unsigned char tmp_cr12=0;
1004 struct net_device *dev = (struct net_device *) data;
1005 struct uli526x_board_info *db = netdev_priv(dev);
1006 unsigned long flags;
1007 u8 TmpSpeed=10;
1008
1009 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1010 spin_lock_irqsave(&db->lock, flags);
1011
1012
1013 /* Dynamic reset ULI526X : system error or transmit time-out */
1014 tmp_cr8 = inl(db->ioaddr + DCR8);
1015 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1016 db->reset_cr8++;
1017 db->wait_reset = 1;
1018 }
1019 db->interval_rx_cnt = 0;
1020
1021 /* TX polling kick monitor */
1022 if ( db->tx_packet_cnt &&
1023 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) {
1024 outl(0x1, dev->base_addr + DCR1); // Tx polling again
1025
1026 // TX Timeout
1027 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) {
1028 db->reset_TXtimeout++;
1029 db->wait_reset = 1;
1030 printk( "%s: Tx timeout - resetting\n",
1031 dev->name);
1032 }
1033 }
1034
1035 if (db->wait_reset) {
1036 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1037 db->reset_count++;
1038 uli526x_dynamic_reset(dev);
1039 db->timer.expires = ULI526X_TIMER_WUT;
1040 add_timer(&db->timer);
1041 spin_unlock_irqrestore(&db->lock, flags);
1042 return;
1043 }
1044
1045 /* Link status check, Dynamic media type change */
1046 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1047 tmp_cr12 = 3;
1048
1049 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1050 /* Link Failed */
1051 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1052 netif_carrier_off(dev);
1053 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1054 db->link_failed = 1;
1055
1056 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1057 /* AUTO don't need */
1058 if ( !(db->media_mode & 0x8) )
1059 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1060
1061 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1062 if (db->media_mode & ULI526X_AUTO) {
1063 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1064 update_cr6(db->cr6_data, db->ioaddr);
1065 }
1066 } else
1067 if ((tmp_cr12 & 0x3) && db->link_failed) {
1068 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1069 db->link_failed = 0;
1070
1071 /* Auto Sense Speed */
1072 if ( (db->media_mode & ULI526X_AUTO) &&
1073 uli526x_sense_speed(db) )
1074 db->link_failed = 1;
1075 uli526x_process_mode(db);
1076
1077 if(db->link_failed==0)
1078 {
1079 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
1080 {
1081 TmpSpeed = 100;
1082 }
1083 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
1084 {
1085 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed);
1086 }
1087 else
1088 {
1089 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed);
1090 }
1091 netif_carrier_on(dev);
1092 }
1093 /* SHOW_MEDIA_TYPE(db->op_mode); */
1094 }
1095 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1096 {
1097 if(db->init==1)
1098 {
1099 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1100 netif_carrier_off(dev);
1101 }
1102 }
1103 db->init=0;
1104
1105 /* Timer active again */
1106 db->timer.expires = ULI526X_TIMER_WUT;
1107 add_timer(&db->timer);
1108 spin_unlock_irqrestore(&db->lock, flags);
1109 }
1110
1111
1112 /*
1113 * Dynamic reset the ULI526X board
1114 * Stop ULI526X board
1115 * Free Tx/Rx allocated memory
1116 * Reset ULI526X board
1117 * Re-initialize ULI526X board
1118 */
1119
1120 static void uli526x_dynamic_reset(struct net_device *dev)
1121 {
1122 struct uli526x_board_info *db = netdev_priv(dev);
1123
1124 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1125
1126 /* Sopt MAC controller */
1127 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1128 update_cr6(db->cr6_data, dev->base_addr);
1129 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1130 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1131
1132 /* Disable upper layer interface */
1133 netif_stop_queue(dev);
1134
1135 /* Free Rx Allocate buffer */
1136 uli526x_free_rxbuffer(db);
1137
1138 /* system variable init */
1139 db->tx_packet_cnt = 0;
1140 db->rx_avail_cnt = 0;
1141 db->link_failed = 1;
1142 db->init=1;
1143 db->wait_reset = 0;
1144
1145 /* Re-initialize ULI526X board */
1146 uli526x_init(dev);
1147
1148 /* Restart upper layer interface */
1149 netif_wake_queue(dev);
1150 }
1151
1152
1153 /*
1154 * free all allocated rx buffer
1155 */
1156
1157 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1158 {
1159 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1160
1161 /* free allocated rx buffer */
1162 while (db->rx_avail_cnt) {
1163 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1164 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1165 db->rx_avail_cnt--;
1166 }
1167 }
1168
1169
1170 /*
1171 * Reuse the SK buffer
1172 */
1173
1174 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1175 {
1176 struct rx_desc *rxptr = db->rx_insert_ptr;
1177
1178 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1179 rxptr->rx_skb_ptr = skb;
1180 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1181 skb_tail_pointer(skb),
1182 RX_ALLOC_SIZE,
1183 PCI_DMA_FROMDEVICE));
1184 wmb();
1185 rxptr->rdes0 = cpu_to_le32(0x80000000);
1186 db->rx_avail_cnt++;
1187 db->rx_insert_ptr = rxptr->next_rx_desc;
1188 } else
1189 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1190 }
1191
1192
1193 /*
1194 * Initialize transmit/Receive descriptor
1195 * Using Chain structure, and allocate Tx/Rx buffer
1196 */
1197
1198 static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1199 {
1200 struct tx_desc *tmp_tx;
1201 struct rx_desc *tmp_rx;
1202 unsigned char *tmp_buf;
1203 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1204 dma_addr_t tmp_buf_dma;
1205 int i;
1206
1207 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1208
1209 /* tx descriptor start pointer */
1210 db->tx_insert_ptr = db->first_tx_desc;
1211 db->tx_remove_ptr = db->first_tx_desc;
1212 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1213
1214 /* rx descriptor start pointer */
1215 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1216 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1217 db->rx_insert_ptr = db->first_rx_desc;
1218 db->rx_ready_ptr = db->first_rx_desc;
1219 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1220
1221 /* Init Transmit chain */
1222 tmp_buf = db->buf_pool_start;
1223 tmp_buf_dma = db->buf_pool_dma_start;
1224 tmp_tx_dma = db->first_tx_desc_dma;
1225 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1226 tmp_tx->tx_buf_ptr = tmp_buf;
1227 tmp_tx->tdes0 = cpu_to_le32(0);
1228 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1229 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1230 tmp_tx_dma += sizeof(struct tx_desc);
1231 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1232 tmp_tx->next_tx_desc = tmp_tx + 1;
1233 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1234 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1235 }
1236 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1237 tmp_tx->next_tx_desc = db->first_tx_desc;
1238
1239 /* Init Receive descriptor chain */
1240 tmp_rx_dma=db->first_rx_desc_dma;
1241 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1242 tmp_rx->rdes0 = cpu_to_le32(0);
1243 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1244 tmp_rx_dma += sizeof(struct rx_desc);
1245 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1246 tmp_rx->next_rx_desc = tmp_rx + 1;
1247 }
1248 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1249 tmp_rx->next_rx_desc = db->first_rx_desc;
1250
1251 /* pre-allocate Rx buffer */
1252 allocate_rx_buffer(db);
1253 }
1254
1255
1256 /*
1257 * Update CR6 value
1258 * Firstly stop ULI526X, then written value and start
1259 */
1260
1261 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1262 {
1263
1264 outl(cr6_data, ioaddr + DCR6);
1265 udelay(5);
1266 }
1267
1268
1269 /*
1270 * Send a setup frame for M5261/M5263
1271 * This setup frame initialize ULI526X address filter mode
1272 */
1273
1274 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1275 {
1276 struct uli526x_board_info *db = netdev_priv(dev);
1277 struct dev_mc_list *mcptr;
1278 struct tx_desc *txptr;
1279 u16 * addrptr;
1280 u32 * suptr;
1281 int i;
1282
1283 ULI526X_DBUG(0, "send_filter_frame()", 0);
1284
1285 txptr = db->tx_insert_ptr;
1286 suptr = (u32 *) txptr->tx_buf_ptr;
1287
1288 /* Node address */
1289 addrptr = (u16 *) dev->dev_addr;
1290 *suptr++ = addrptr[0];
1291 *suptr++ = addrptr[1];
1292 *suptr++ = addrptr[2];
1293
1294 /* broadcast address */
1295 *suptr++ = 0xffff;
1296 *suptr++ = 0xffff;
1297 *suptr++ = 0xffff;
1298
1299 /* fit the multicast address */
1300 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1301 addrptr = (u16 *) mcptr->dmi_addr;
1302 *suptr++ = addrptr[0];
1303 *suptr++ = addrptr[1];
1304 *suptr++ = addrptr[2];
1305 }
1306
1307 for (; i<14; i++) {
1308 *suptr++ = 0xffff;
1309 *suptr++ = 0xffff;
1310 *suptr++ = 0xffff;
1311 }
1312
1313 /* prepare the setup frame */
1314 db->tx_insert_ptr = txptr->next_tx_desc;
1315 txptr->tdes1 = cpu_to_le32(0x890000c0);
1316
1317 /* Resource Check and Send the setup packet */
1318 if (db->tx_packet_cnt < TX_DESC_CNT) {
1319 /* Resource Empty */
1320 db->tx_packet_cnt++;
1321 txptr->tdes0 = cpu_to_le32(0x80000000);
1322 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1323 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1324 update_cr6(db->cr6_data, dev->base_addr);
1325 dev->trans_start = jiffies;
1326 } else
1327 printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n");
1328 }
1329
1330
1331 /*
1332 * Allocate rx buffer,
1333 * As possible as allocate maxiumn Rx buffer
1334 */
1335
1336 static void allocate_rx_buffer(struct uli526x_board_info *db)
1337 {
1338 struct rx_desc *rxptr;
1339 struct sk_buff *skb;
1340
1341 rxptr = db->rx_insert_ptr;
1342
1343 while(db->rx_avail_cnt < RX_DESC_CNT) {
1344 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1345 break;
1346 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1347 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1348 skb_tail_pointer(skb),
1349 RX_ALLOC_SIZE,
1350 PCI_DMA_FROMDEVICE));
1351 wmb();
1352 rxptr->rdes0 = cpu_to_le32(0x80000000);
1353 rxptr = rxptr->next_rx_desc;
1354 db->rx_avail_cnt++;
1355 }
1356
1357 db->rx_insert_ptr = rxptr;
1358 }
1359
1360
1361 /*
1362 * Read one word data from the serial ROM
1363 */
1364
1365 static u16 read_srom_word(long ioaddr, int offset)
1366 {
1367 int i;
1368 u16 srom_data = 0;
1369 long cr9_ioaddr = ioaddr + DCR9;
1370
1371 outl(CR9_SROM_READ, cr9_ioaddr);
1372 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1373
1374 /* Send the Read Command 110b */
1375 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1376 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1377 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1378
1379 /* Send the offset */
1380 for (i = 5; i >= 0; i--) {
1381 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1382 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1383 }
1384
1385 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1386
1387 for (i = 16; i > 0; i--) {
1388 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1389 udelay(5);
1390 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1391 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1392 udelay(5);
1393 }
1394
1395 outl(CR9_SROM_READ, cr9_ioaddr);
1396 return srom_data;
1397 }
1398
1399
1400 /*
1401 * Auto sense the media mode
1402 */
1403
1404 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1405 {
1406 u8 ErrFlag = 0;
1407 u16 phy_mode;
1408
1409 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1410 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1411
1412 if ( (phy_mode & 0x24) == 0x24 ) {
1413
1414 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1415 if(phy_mode&0x8000)
1416 phy_mode = 0x8000;
1417 else if(phy_mode&0x4000)
1418 phy_mode = 0x4000;
1419 else if(phy_mode&0x2000)
1420 phy_mode = 0x2000;
1421 else
1422 phy_mode = 0x1000;
1423
1424 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1425 switch (phy_mode) {
1426 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1427 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1428 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1429 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1430 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1431 }
1432 } else {
1433 db->op_mode = ULI526X_10MHF;
1434 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1435 ErrFlag = 1;
1436 }
1437
1438 return ErrFlag;
1439 }
1440
1441
1442 /*
1443 * Set 10/100 phyxcer capability
1444 * AUTO mode : phyxcer register4 is NIC capability
1445 * Force mode: phyxcer register4 is the force media
1446 */
1447
1448 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1449 {
1450 u16 phy_reg;
1451
1452 /* Phyxcer capability setting */
1453 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1454
1455 if (db->media_mode & ULI526X_AUTO) {
1456 /* AUTO Mode */
1457 phy_reg |= db->PHY_reg4;
1458 } else {
1459 /* Force Mode */
1460 switch(db->media_mode) {
1461 case ULI526X_10MHF: phy_reg |= 0x20; break;
1462 case ULI526X_10MFD: phy_reg |= 0x40; break;
1463 case ULI526X_100MHF: phy_reg |= 0x80; break;
1464 case ULI526X_100MFD: phy_reg |= 0x100; break;
1465 }
1466
1467 }
1468
1469 /* Write new capability to Phyxcer Reg4 */
1470 if ( !(phy_reg & 0x01e0)) {
1471 phy_reg|=db->PHY_reg4;
1472 db->media_mode|=ULI526X_AUTO;
1473 }
1474 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1475
1476 /* Restart Auto-Negotiation */
1477 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1478 udelay(50);
1479 }
1480
1481
1482 /*
1483 * Process op-mode
1484 AUTO mode : PHY controller in Auto-negotiation Mode
1485 * Force mode: PHY controller in force mode with HUB
1486 * N-way force capability with SWITCH
1487 */
1488
1489 static void uli526x_process_mode(struct uli526x_board_info *db)
1490 {
1491 u16 phy_reg;
1492
1493 /* Full Duplex Mode Check */
1494 if (db->op_mode & 0x4)
1495 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1496 else
1497 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1498
1499 update_cr6(db->cr6_data, db->ioaddr);
1500
1501 /* 10/100M phyxcer force mode need */
1502 if ( !(db->media_mode & 0x8)) {
1503 /* Forece Mode */
1504 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1505 if ( !(phy_reg & 0x1) ) {
1506 /* parter without N-Way capability */
1507 phy_reg = 0x0;
1508 switch(db->op_mode) {
1509 case ULI526X_10MHF: phy_reg = 0x0; break;
1510 case ULI526X_10MFD: phy_reg = 0x100; break;
1511 case ULI526X_100MHF: phy_reg = 0x2000; break;
1512 case ULI526X_100MFD: phy_reg = 0x2100; break;
1513 }
1514 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1515 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1516 }
1517 }
1518 }
1519
1520
1521 /*
1522 * Write a word to Phy register
1523 */
1524
1525 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1526 {
1527 u16 i;
1528 unsigned long ioaddr;
1529
1530 if(chip_id == PCI_ULI5263_ID)
1531 {
1532 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1533 return;
1534 }
1535 /* M5261/M5263 Chip */
1536 ioaddr = iobase + DCR9;
1537
1538 /* Send 33 synchronization clock to Phy controller */
1539 for (i = 0; i < 35; i++)
1540 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1541
1542 /* Send start command(01) to Phy */
1543 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1544 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1545
1546 /* Send write command(01) to Phy */
1547 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1548 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1549
1550 /* Send Phy address */
1551 for (i = 0x10; i > 0; i = i >> 1)
1552 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1553
1554 /* Send register address */
1555 for (i = 0x10; i > 0; i = i >> 1)
1556 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1557
1558 /* written trasnition */
1559 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1560 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1561
1562 /* Write a word data to PHY controller */
1563 for ( i = 0x8000; i > 0; i >>= 1)
1564 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1565
1566 }
1567
1568
1569 /*
1570 * Read a word data from phy register
1571 */
1572
1573 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1574 {
1575 int i;
1576 u16 phy_data;
1577 unsigned long ioaddr;
1578
1579 if(chip_id == PCI_ULI5263_ID)
1580 return phy_readby_cr10(iobase, phy_addr, offset);
1581 /* M5261/M5263 Chip */
1582 ioaddr = iobase + DCR9;
1583
1584 /* Send 33 synchronization clock to Phy controller */
1585 for (i = 0; i < 35; i++)
1586 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1587
1588 /* Send start command(01) to Phy */
1589 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1590 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1591
1592 /* Send read command(10) to Phy */
1593 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1594 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1595
1596 /* Send Phy address */
1597 for (i = 0x10; i > 0; i = i >> 1)
1598 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1599
1600 /* Send register address */
1601 for (i = 0x10; i > 0; i = i >> 1)
1602 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1603
1604 /* Skip transition state */
1605 phy_read_1bit(ioaddr, chip_id);
1606
1607 /* read 16bit data */
1608 for (phy_data = 0, i = 0; i < 16; i++) {
1609 phy_data <<= 1;
1610 phy_data |= phy_read_1bit(ioaddr, chip_id);
1611 }
1612
1613 return phy_data;
1614 }
1615
1616 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1617 {
1618 unsigned long ioaddr,cr10_value;
1619
1620 ioaddr = iobase + DCR10;
1621 cr10_value = phy_addr;
1622 cr10_value = (cr10_value<<5) + offset;
1623 cr10_value = (cr10_value<<16) + 0x08000000;
1624 outl(cr10_value,ioaddr);
1625 udelay(1);
1626 while(1)
1627 {
1628 cr10_value = inl(ioaddr);
1629 if(cr10_value&0x10000000)
1630 break;
1631 }
1632 return (cr10_value&0x0ffff);
1633 }
1634
1635 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1636 {
1637 unsigned long ioaddr,cr10_value;
1638
1639 ioaddr = iobase + DCR10;
1640 cr10_value = phy_addr;
1641 cr10_value = (cr10_value<<5) + offset;
1642 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1643 outl(cr10_value,ioaddr);
1644 udelay(1);
1645 }
1646 /*
1647 * Write one bit data to Phy Controller
1648 */
1649
1650 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1651 {
1652 outl(phy_data , ioaddr); /* MII Clock Low */
1653 udelay(1);
1654 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1655 udelay(1);
1656 outl(phy_data , ioaddr); /* MII Clock Low */
1657 udelay(1);
1658 }
1659
1660
1661 /*
1662 * Read one bit phy data from PHY controller
1663 */
1664
1665 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1666 {
1667 u16 phy_data;
1668
1669 outl(0x50000 , ioaddr);
1670 udelay(1);
1671 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1672 outl(0x40000 , ioaddr);
1673 udelay(1);
1674
1675 return phy_data;
1676 }
1677
1678
1679 static struct pci_device_id uli526x_pci_tbl[] = {
1680 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1681 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1682 { 0, }
1683 };
1684 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1685
1686
1687 static struct pci_driver uli526x_driver = {
1688 .name = "uli526x",
1689 .id_table = uli526x_pci_tbl,
1690 .probe = uli526x_init_one,
1691 .remove = __devexit_p(uli526x_remove_one),
1692 };
1693
1694 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1695 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1696 MODULE_LICENSE("GPL");
1697
1698 module_param(debug, int, 0644);
1699 module_param(mode, int, 0);
1700 module_param(cr6set, int, 0);
1701 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1702 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1703
1704 /* Description:
1705 * when user used insmod to add module, system invoked init_module()
1706 * to register the services.
1707 */
1708
1709 static int __init uli526x_init_module(void)
1710 {
1711
1712 printk(version);
1713 printed_version = 1;
1714
1715 ULI526X_DBUG(0, "init_module() ", debug);
1716
1717 if (debug)
1718 uli526x_debug = debug; /* set debug flag */
1719 if (cr6set)
1720 uli526x_cr6_user_set = cr6set;
1721
1722 switch (mode) {
1723 case ULI526X_10MHF:
1724 case ULI526X_100MHF:
1725 case ULI526X_10MFD:
1726 case ULI526X_100MFD:
1727 uli526x_media_mode = mode;
1728 break;
1729 default:
1730 uli526x_media_mode = ULI526X_AUTO;
1731 break;
1732 }
1733
1734 return pci_register_driver(&uli526x_driver);
1735 }
1736
1737
1738 /*
1739 * Description:
1740 * when user used rmmod to delete module, system invoked clean_module()
1741 * to un-register all registered services.
1742 */
1743
1744 static void __exit uli526x_cleanup_module(void)
1745 {
1746 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1747 pci_unregister_driver(&uli526x_driver);
1748 }
1749
1750 module_init(uli526x_init_module);
1751 module_exit(uli526x_cleanup_module);
Tomato firmware and modifications.